Logic Design Review – 3 Basic Sequential Circuits Lecture L14.3 Verilog.

Logic Design Review – 3 Basic Sequential Circuits

Lecture L14.3

Verilog

Basic Sequential Circuits

• Latches

• Flip-Flops

• Registers

• Counters

• Shift Registers

• Datapaths

• State Machines

R-S Latch

R-S Latch

R

S

Q

Q is set to 1 when S is asserted, and remains unchanged when S is disasserted.

Q is reset to 0 when R is asserted, and remains unchanged when R is disasserted.

Assertions can be active HIGH or active LOW

R-S Latch

R

S

Q

Active HIGH

module RSlatch ( Q ,R ,S );

input R ;wire R ;input S ;wire S ;

output Q ;reg Q ;

always @(R or S) begin

if(S == 1 && R == 0)Q = 1;

else if(S == 0 && R == 1)Q = 0;

end endmodule

R-S Latch -- Active High

R-S Latch

R

S

Q

Active LOW

module RSlatch ( Q ,R ,S );


output Q ;reg Q ;

always @(R or S) begin

if(S == 0 && R == 1)Q = 1;

else if(S == 1 && R == 0)Q = 0;

end endmodule

R-S Latch -- Active Low

F1

F2

R

S

Q

Note that this is different from the "textbook" RS latch

module RSlatchNOR ( Q ,R ,S );


output Q ;wire Q ;wire F1, F2;

nor #10 (F1,F2,R);nor #10 (F2,F1,S);

assign Q = F1; endmodule

10ns propagation delay

F1

F2

R

S

QR S Q0 0 Q0 store0 1 1 set1 0 0 reset1 1 0 disallowed

How can you make this R-S latch from gates?

R-S Latch

R

S

Q

Q is set to 1 when S is asserted, and remains unchanged when S is disasserted.

Q is reset to 0 when R is asserted, and remains unchanged when R is disasserted.

Assertions can be active HIGH or active LOW

R S Q Q0 0 0 00 0 1 10 1 0 10 1 1 11 0 0 01 0 1 01 1 0 01 1 1 1

R-S LatchR

S

Q

Q is set to 1 when S is asserted (1), and remains unchanged when S is disasserted (0).

Q is reset to 0 when R is asserted (1), and remains unchanged when R is disasserted (0).

RSQ

00 01 11 10

0

1

Q = ~R & Q | ~R & S | S & Q

1 1

1

1store

set

reset

store

Q

S

R

R S Q Q0 0 0 00 0 1 10 1 0 10 1 1 11 0 0 01 0 1 01 1 0 01 1 1 1

Q = ~R & Q | ~R & S | S & Q

store

set

reset

store

R-S LatchR

S

Q

RS Latch

module RSlatchGates ( Q ,R ,S );


output Q ;wire Q ;

assign #10 Q = ~R & Q | ~R & S | S & Q; endmodule

Q

S

R

Q

S

R

D Latch

D Latch

D

EN

Q

Q follows D when EN is high, and remains unchanged when EN is low..

D Latch

D

EN

Q

module Dlatch ( Q ,EN ,D );

input EN ;wire EN ;input D ;wire D ;

output Q ;reg Q ;

always @(D or EN)if(EN == 1) Q = D;

endmodule

D Latch


• Latches

• Flip-Flops

• Registers

• Counters

• Shift Registers

• Datapaths

• State Machines

D Flip-Flop

0 0 11 1 0X 0 Q0 !Q0

D clk Q !Q

D gets latched to Q on the rising edge of the clock.

Positive edge triggered

always @(posedge clk)Q <= D;

Behavior

clk

D Q

!Q

clk

D Q

!Q

module DFF (D, clk, Q, notQ );

input clk ;wire clk ;input D ;wire D ;

output Q ;reg Q ;output notQ ;wire notQ ;

always @(posedge clk)Q <= D;

assign notQ = ~Q;

endmodule

DFF.v

Note non-blocking assignment

D Flip-Flop

module DFFclr (D, clk, clr, Q, notQ );

input clk ;wire clk ;input clr ;wire clr ;input D ;wire D ;

output Q ;reg Q ;output notQ ;wire notQ ;

always @(posedge clk or posedge clr)if(clr == 1)

Q <= 0;else

Q <= D;

assign notQ = ~Q;

endmodule

clk

D Q

!Qclk

D Q

!Q

clr

DFFclr.v

Asynchronous clear

D Flip-Flop with Asynchronous Clear


• Latches

• Flip-Flops

• Registers

• Counters

• Shift Registers

• Datapaths

• State Machines

A 1-Bit Register

reg1Q0

!Q0

LOAD

INP0

CLK

Behavior

always @(posedge clk) if(LOAD == 1)

Q0 <= INP0;

A 4-Bit Register

reg1Q0

!Q0

LOAD

INP0

reg1Q1

!Q1INP1

reg1Q2

!Q2INP2

reg1Q3

!Q3INP3

CLK

reg1Q0

!Q0

LOAD

INP0

CLK

// An n-bit register with asynchronous clear and load

module register(clk,clr,load,d,q);parameter n = 8;input [n-1:0] d;input clk,clr,load;output [n-1:0] q;reg [n-1:0] q;

always @(posedge clk or posedge clr) if(clr == 1)

q <= 0; else if(load)

q <= d;

endmodule

q(n-1 downto 0)

clk clr

load

d(n-1 downto 0)

reg

A Generic Register

q(n-1 downto 0)

clk clr

load

d(n-1 downto 0)

reg

A Generic Register


• Latches

• Flip-Flops

• Registers

• Counters

• Shift Registers

• Datapaths

• State Machines

3-Bit Counter

always @(posedge clk or posedge clr) begin if(clr == 1)

Q <= 0; else

Q <= Q + 1; end

Behavior

count3clr

clkQ(2 downto 0)

module counter3 (clk, clr, Q );

input clr ;wire clr ;input clk ;wire clk ;

output [2:0] Q ;reg [2:0] Q ;

// 3-bit counteralways @(posedge clk or posedge clr) begin if(clr == 1)

Q <= 0; else

Q <= Q + 1; end

endmodule

counter3.v

Asynchronous clear

Output count incrementson rising edge of clk

counter3 Simulation

Clock DividerClk4 = 4 MHz clock

Q3CLK

Clock DividerCounter Q7..Q0

4 MHz Clock

Q3CLK

Q3CLK


4 MHz Clock


4 MHz Clock

Q1

Q0

1.0 MHz

Q2 0.5 MHz

Q3 0.25 MHz

2.0 MHz

Clock 4.0 MHz


• Latches

• Flip-Flops

• Registers

• Counters

• Shift Registers

• Datapaths

• State Machines

4-Bit Shift Register

CLK

D Q

!Q CLK

D Q

!Q CLK

D Q

!Q CLK

D Q

!Q

data_in

CLK

Q0Q1Q2Q3

shift4.vmodule ShiftReg(clk,clr,data_in,Q); input clk; input clr; input data_in; output [3:0] Q;

reg [3:0] Q;

// 4-bit Shift Register always @(posedge clk or posedge clr)begin if(clr == 1)

Q <= 0; else

begin Q[3] <= data_in; Q[2:0] <= Q[3:1];end

endendmodule

CLK

D Q

!Q CLK

D Q

!Q CLK

D Q

!Q CLK

D Q

!Q

data_in

CLK

Q0Q1Q2Q3

Note non-blocking assignment

shift4 simulation

Ring Counter

CLK

D Q

!Q CLK

D Q

!Q CLK

D Q

!Q CLK

D Q

!Q

CLK

Q0Q1Q2Q3

ring4.vmodule ring4(clk,clr,Q); input clk; input clr; output [3:0] Q;

reg [3:0] Q;

// 4-bit Ring Counter always @(posedge clk or posedge clr)begin if(clr == 1)

Q <= 1; else

begin Q[3] <= Q[0]; Q[2:0] <= Q[3:1];end

endendmodule

ring4 simulation

Johnson Counter

CLK

D Q

!Q CLK

D Q

!Q CLK

D Q

!Q CLK

D Q

!Q

CLK

Q3 Q2 Q1 Q0

module johnson4(clk,clr,Q); input clk; input clr; output [3:0] Q;

reg [3:0] Q;

// 4-bit Johnson Counter always @(posedge clk or posedge clr)begin if(clr == 1)

Q <= 0; else

begin Q[3] <= ~Q[0]; Q[2:0] <= Q[3:1];end

endendmodule

johnson4.v

Johnson Counter

CLK

D Q

!Q CLK

D Q

!Q CLK

D Q

!Q CLK

D Q

!Q

CLK

Q3 Q2 Q1 Q0

A Random Number Generator

CLK

D Q

!Q CLK

D Q

!Q CLK

D Q

!Q CLK

D Q

!Q

CLK

Q3 Q2 Q1 Q0

Q3 Q2 Q1 Q0

0 0 0 1 11 0 0 0 81 1 0 0 C1 1 1 0 E1 1 1 1 F0 1 1 1 71 0 1 1 B0 1 0 1 5

Q3 Q2 Q1 Q0

1 0 1 0 A1 1 0 1 D0 1 1 0 60 0 1 1 31 0 0 1 90 1 0 0 40 0 1 0 20 0 0 1 1

module rand4(clk,clr,Q); input clk; input clr; output [3:0] Q;

reg [3:0] Q;

// 4-bit Random number generator always @(posedge clk or posedge clr)begin if(clr == 1)

Q <= 1; else

begin Q[3] <= Q[3] ^ Q[0]; Q[2:0] <= Q[3:1];end

endendmodule

rand4.v

A Random Number Generator

clk

inp

Q2

Q0

Q1

outp

Clock Pulse

module clk_pulse(clk,clr,inp,outp); input clk; input clr; input inp; output outp;

wire outp; reg [2:0] Q;

// clock pulse generator always @(posedge clk or posedge clr)begin if(clr == 1)

Q <= 0; else

begin Q[2] <= inp; Q[1:0] <= Q[2:1];end

endassign outp = Q[2] & Q[1] & ~Q[0];

endmodule

clk_pulse.v

clk

inpQ2

Q0Q1

outp


• Latches

• Flip-Flops

• Registers

• Counters

• Shift Registers

• Datapaths

• State Machines

a square delta

outreg

<= D2M1

+2+

clr

clk

clr

clk

clr

clk

clr

clkoutld

ald sqld dld

lteflg

R(3:0)

delta(4:0)

SW(7:0)

4

58 9

DatapathControl Unit

lteflg

clr clk clr clk

ald

R[3:0]

S[7:0]

outld

dld

sqld

start

Lab 8

unsigned long sqrt(unsigned long a){ unsigned long square = 1; unsigned long delta = 3; while(square <= a){

square += delta; delta += 2;

} return (delta/2 - 1);}


• Latches

• Flip-Flops

• Registers

• Counters

• Shift Registers

• Datapaths

• State Machines

A canonical sequential network

clear

clk

Presentstate

Nextstate

Presentinput

Presentoutput

x(t)

s(t)s(t+1)

z(t)S

tate

Re

gist

er

Com

bina

tiona

lN

etw

ork

A Mealy state machine

clear

clk

Presentstate

Nextstate

Presentinput Present

output

x(t)

s(t)

s(t+1)

z(t)

Sta

te R

egis

ter

C1

C2

A Moore state machine

C1 C2

clear

clk

Presentstate

Nextstate

Presentinput

Presentoutputx(t)

s(t)

s(t+1)

z(t)

Sta

te R

egis

ter

SQRTctl

start

test

updatedone

!strt

strt

lteflg

!lteflgsquare += delta

delta += 2

delta / 2 - 1

start

test

updatedone

!strt

strt

lteflg


delta += 2

delta / 2 - 1

a square delta

outreg

<= D2M1

+2+

clr

clk

clr

clk

clr

clk

clr

clkoutld

ald sqld dld

lteflg

R(3:0)

delta(4:0)

SW(7:0)

4

58 9


lteflg

clr clk clr clk

ald

R[3:0]

S[7:0]

outld

dld

sqld

start

Lab 8


C1 C2

clear

clk

Presentstate

Nextstate

Presentinput

Presentoutputx(t)

s(t)

s(t+1)

z(t)

Sta

te R

egis

ter

start

test

updatedone

!strt

strt

lteflg


delta += 2

delta / 2 - 1

// Square root controlmodule SQRTctrl(Clk, Clear, lteflg, strt, ald,

sqld, dld, outld); input Clk, Clear, lteflg, strt;output ald, sqld, dld, outld;reg ald, sqld, dld, outld;reg[1:0] present_state, next_state;parameter start = 2'b00, test = 2'b01,

update = 2'b10, done = 2'b11;

// State registeralways @(posedge Clk or posedge Clear) begin if (Clear == 1) present_state <= start; else present_state <= next_state; end


C1 C2

clear

clk

Presentstate

Nextstate

Presentinput

Presentoutputx(t)

s(t)

s(t+1)

z(t)

Sta

te R

egis

ter

start

test

updatedone

!strt

strt

lteflg


delta += 2

delta / 2 - 1

// C1: next statealways @(present_state or start or lteflg) begin case(present_state)

strt: if(strt == 1) next_state <= test; else next_state <=start;test: if(lteflg == 1) next_state <= update; else next_state <= done;update: next_state <= test;done: next_state <= done;default next_state <= start;

endcase end


C1 C2

clear

clk

Presentstate

Nextstate

Presentinput

Presentoutputx(t)

s(t)

s(t+1)

z(t)

Sta

te R

egis

ter

// C2: outputsalways @(present_state) begin case(present_state)

strt: beginald = 1; sqld = 0; dld = 0; outld = 0;

endtest: begin

ald = 0; sqld = 0; dld = 0; outld = 0;end

update: begin ald = 0; sqld = 1; dld = 1; outld = 0;

enddone: begin

ald = 0; sqld = 0; dld = 0; outld = 1;end

default begin ald = 0; sqld = 0; dld = 0; outld = 0; end

endcase end endmodule

a square delta

outreg

<= D2M1

+2+

clr

clk

clr

clk

clr

clk

clr

clkoutld

ald sqld dld

lteflg

R(3:0)

delta(4:0)

SW(7:0)

4

58 9

start

test

updatedone

!strt

strt

lteflg


delta += 2

delta / 2 - 1

a square delta

outreg

<= D2M1

+2+

clr

clk

clr

clk

clr

clk

clr

clkoutld

ald sqld dld

lteflg

R(3:0)

delta(4:0)

SW(7:0)

4

58 9


lteflg

clr clk clr clk

ald

R[3:0]

S[7:0]

outld

dld

sqld

start

Lab 8

Logic Design Review – 3 Basic Sequential Circuits Lecture L14.3 Verilog.

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