Record-Performance In(Ga)As MOSFETs

Targeting ITRS High-Performance

and Low-Power Logic

227th Electrochemical Society Meeting, Chicago, May 24-28, 2015

M. Rodwell, C. Y. Huang, S. Lee, V. Chobpattana, B. Thibeault, W. Mitchell, S. Stemmer, A. Gossard University of California, Santa Barbara

Why III-V MOS ?

III-V vs. Si: Low m*→ higher velocity. Fewer states→ less scattering → higher current. Can then trade for lower voltage or smaller FETs.

Problems: Low m*→ less charge. Low m* → more S/D tunneling. Narrow bandgap→ more band-band tunneling, impact ionization.

2

InGaAs/InAs FETs are leaky!

3

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.510

-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

gm (

mS

/m

)

Cu

rre

nt

De

ns

ity

(m

A/

m)

Gate Bias (V)

0.0

0.5

1.0

1.5

2.0

2.5

3.0L

g = 25 nm

SS~ 72 mV/dec.

SS~ 77 mV/dec.

Ion= 500 A/m at Ioff

=100 nA/m

and VD=0.5V

10 100

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

S. Lee, VLSI 2014

J. Lin, IEDM 2013

T. Kim, IEDM 2013

Intel, IEDM 2009

J. Gu, IEDM 2012

D. Kim, IEDM 2012

I on (

mA

/m

)

Gate Length (nm)

VDS

= 0.5 V

Ioff

=100 nA/m

HP = High Performance: Ioff =100 nA/m

GP = General Purpose: Ioff =1 nA/m

LP = Low Power: Ioff =30 pA/m

ULP = Ultra Low Power: Ioff =10 pA/m

Device Structures: Lateral Spacers & Tunneling

Small S/D contact pitch MOS-HEMT with large contact pitch

UCSB

no lateral gate-drain space

Lin, IEDM2013

~70 nm gate-drain space

4

We must build devices with small S/D pitch.

contact pitch ~ 3 times lithographic half-pitch (technology node dimension)

Small S/D pitch hard to realize if we require ~20-50nm lateral gate-drain spacers !

Intel 35nm NMOS

5

Reducing leakage (1)

375 nm InAlAs N.I.D buffer

Semi-insulating InP substrate

50 nm

N+ InGaAs

50 nm

N+ InGaAs

25 nm AlAsSb N.I.D barrier

3 nm AlAsSb N.I.D spacer

3 nm Si-doped InAlAs

Ni/AuTi/Pd/

Au

Ti/Pd/

Au

10 nm InGaAs N.I.D channel

Wide band-gap barriers or P-doped back barriers reduces bottom leakage path.

Solution 1: AlAsSb barriers (Sample B) reduces subthreshold leakage.

Solution 2: P-doped InAlAs barriers also work well.

C. Y. Huang et al., APL., 103, 203502 (2013) 6

Reducing leakage (1)

375 nm InAlAs N.I.D buffer

Semi-insulating InP substrate

50 nm

N+ InGaAs

50 nm

N+ InGaAs

25 nm AlAsSb N.I.D barrier

3 nm AlAsSb N.I.D spacer

3 nm Si-doped InAlAs

Ni/AuTi/Pd/

Au

Ti/Pd/

Au

10 nm InGaAs N.I.D channel

Wide band-gap barriers or P-doped back barriers reduces bottom leakage path.

Solution 1: AlAsSb barriers (Sample B) reduces subthreshold leakage.

Solution 2: P-doped InAlAs barriers also work well.

C. Y. Huang et al., APL., 103, 203502 (2013) 7

Reducing leakage (2): Source/Drain Vertical Spacer

S. Lee et al., APL 103, 233503 (2013)

C. Y. Huang et al., DRC 2014.

Vertical spacers reduce the peak electric field, improve electrostatics, and reduce BTBT floor.

8

Source

Substrate

Barrier

Channel

DrainSpacer

Gate

Spacer

Spacer

Vertical spacers: some details

Minimum S/D contact pitch: depends upon regrowth angle vertical growth reported in literature our recent results: vertical Spacer sidewalls are gated through the high-K. Capacitance to UID sidewalls is small. added gate length→ adds ~0.3 fF/m. Capacitance to N+ contacts layers is large. easy to eliminate: low-er sidewall spacer.

Deliberate band offset between spacer & channel compensates offset from strong quantization in channel.

9

Reducing leakage (3): Ultra-thin channel

*Heavy elements look brighter Courtesy of S. Kraemer (UCSB) Lee et al., 2014 VSLI Symposium

Reducing leakage (3): Ultra-thin channel

11

10 100

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

S. Lee, VLSI 2014

J. Lin, IEDM 2013

T. Kim, IEDM 2013

Intel, IEDM 2009

J. Gu, IEDM 2012

D. Kim, IEDM 2012

I on (

mA

/m

)

Gate Length (nm)

VDS

= 0.5 V

Ioff

=100 nA/m

S. Lee et al., VLSI 2014

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.510

-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

DIBL = 76 mV/V

VT = -85 mV at 1 A/m

SSmin

~ 72 mV/dec. (at VDS

= 0.1 V)

SSmin

~ 77 mV/dec. (at VDS

= 0.5 V)

Lg = 25 nm

VDS

= 0.1 to 0.7 V

0.2 V increment

Cu

rre

nt

De

ns

ity

(m

A/

m)

Gate Bias (V)

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.70.0

0.2

0.4

0.6

0.8

1.0

1.2

Cu

rre

nt

De

ns

ity

(m

A/

m)

Drain Bias (V)

Ron

= 303 Ohm-m

at VGS

= 0.7 V

VGS

= -0.4 V to 0.7 V

0.1 V increment

0.01 0.1 160

70

80

90

100

110

120 [2]

[4]

[3]

[7]

[1]

[6]

[5]

Solid: VDS

= 0.5 V

Open: VDS

= 0.1 V

Gate Length (m)

SS

min (

mV

/de

c.)

This work

[1] Lin IEDM 2013,[2] T.-W. Kim IEDM 2013,[3] Chang IEDM 2013,[4] Kim IEDM 2013 [5] Lee APL 2013 (UCSB), [6] D. H. Kim IEDM 2012,[7] Gu IEDM 2012,[8] Radosavljevic IEDM 2009

MOSFET: 2.5nm ZrO2/ 1nm Al2O3 / 2.5nm InAs

-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.710

-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

|Ga

te L

ea

ka

ge

| (A

/cm

2)

Cu

rre

nt

De

ns

ity

(m

A/

m)

Gate Bias (V)

10-5

10-4

10-3

10-2

10-1

100

101

SSmin

~ 61 mV/dec.

(at VDS

= 0.1 V)

SSmin

~ 63 mV/dec.

(at VDS

= 0.5 V)

Dot : Reverse Sweep

Solid: Forward Sweep

Lg = 1 m

61 mV/dec Subthreshold swing at VDS=0.1 V

Negligible hysteresis 12

Compared to Intel 14nm finFET

Ioff=10nA/m, Ion=0.45mA/m @VDS=0.5V per m of fin footprint

Re-normalizing to fin periphery: ~0.24 mA/m

S. Natarajan et al, IEDM 2014, December, San Francisco

13

Off-state comparison: 2.5 nm vs. 5.0 nm-thick InAs channel

-0.2 0.0 0.2 0.410

-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

100

IG

SS ~ 60 mV/dec

at VDS

=0.1 V

Cu

rre

nt

De

ns

ity

(m

A/

m)

Gate Bias (V)

ID

-0.2 0.0 0.2 0.4

IG

SS ~ 64 mV/dec

at VDS

=0.1 V

Gate Bias (V)

ID

5.0 nm InAs 2.5 nm InAs

0.01 0.1 160

70

80

90

100

110

5.0 nm InAs

2.5 nm InAs

Open: VDS

= 0.1 V

Solid: VDS

= 0.5 V

Gate Length (m)

SS

min (

mV

/de

c)

Better SS at all gate lengths

Better electrostatics (aspect ratio) and reduced BTBT (quantized Eg)

~10:1 reduction in minimum off-state leakage

~5:1 increase in gate leakage increased eigenstate

Lg =500 nm Lg =500 nm

14

On-state comparison: 2.5 nm vs. 5.0 nm-thick InAs channel

0.01 0.1 10.0

0.4

0.8

1.2

1.6

2.0

2.4

2.8InAs channel thickness

2.5 nm

5.0 nm

VDS

= 0.5 V

Gate Length (m)

Pe

ak

gm (

mS

/m

)

0 1 2 3 4 5 6 70

200

400

600

800

1000

1200

x 1012

e

ff (

cm

2/s

-V)

Carrier Density (/cm2)

2.5 nm InAs

5.0 nm InAs

-0.2 0.0 0.2 0.4 0.60.0

0.5

1.0

1.5

2.0

2.5

Cox

= 4.2 F/cm2

EOT= 0.8 nm

W/L= 25m/21 m

Freq: 200kHz

2.5 nm InAs

5.0 nm InAs

Ga

te C

ap

ac

ita

nc

e (F

/cm

2)

Gate Bias (V)

0

1

2

3

4

5

6

7

x 1

01

2

Ca

rrie

r D

en

sit

y (

/cm

2)

0.4

0.2

-0.2

0.0

-0.4

-0.6

0.6

0.8

EF

E1En

erg

y (

eV

)

Position (nm)10 20 30

EF

E1

Position (nm)10 20 30

~1.25 nm ~2.5 nm

2.5 nm thick 5 nm thick

1D-Possion Schrodinger solver (coded by W. Frensley, UT Dallas)

15

ZrO2 vs. HfO2: Peak gm, SS, split-CV, and mobility

0.01 0.1 10.0

0.4

0.8

1.2

1.6

2.0

2.4

0425A1 (30A ZrO2)

0425A2 (30A HfO2)

VLSI (30A ZrO2)

VDS

= 0.5 V

Gate Length (m)

Pe

ak

gm (

mS

/m

)

0.01 0.1 1

60

65

70

75

80

85

90 VLSI (30A ZrO2)

0425A1 (30A ZrO2)

0425A2 (30A HfO2)

Open: VDS

= 0.1 V

Solid: VDS

= 0.5 V

Gate Length (m)

SS

min (

mV

/de

c)

0.0 0.2 0.4 0.60.0

0.5

1.0

1.5

2.0

2.5W/L= 25m/21 m

Freq: 200kHz

ZrO2

HfO2

Ga

te C

ap

ac

ita

nc

e (F

/cm

2)

Gate Bias (V)

0

1

2

3

4

5

6

7

x 1

01

2

Ca

rrie

r D

en

sit

y (

/cm

2)

16 (1) ZrO2 higher capacitance than HfO2 , (2) ZrO2 results are reproducible

Comparison: two process runs ZrO2 , one run HfO2 , both 2nm (on 1nm Al2O3)

Reducing leakage (4): Thin InGaAs Channel

-0.2 0.0 0.2 0.4 0.610

-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

gm (m

S/

m)I D

S (

mA

/m

)

VGS

(V)

0.0

0.4

0.8

1.2

1.6

2.0

2.4

VDS

= 0.1 V (solid)

0.5 V (dash)

Sample A: black

Sample B: red

Lg=22 nm

Reducing channel thickness improves electrostatics, increases

confinement bandgap and reduces BTBT.

-0.4 -0.2 0.0 0.2 0.4 0.610

-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

|IG|

Sample B

Lg~22 nm

VDS

= 0.1 to 0.7 V

0.2 V increment

I D,

|IG|

(mA

/m

)

VGS

(V)

ID

Spacer

BTBT limited

17

Tch

E1

E2

E1

E2

InGaAs vs. InAs Channel

similar mobility in 2-3 nm thick quantum well

InGaAs has lower on-current in FET with 3nm thick channel ?!?

Huang: IPRM 2015

18

E-field and BTBT contour

J. Lin et al., EDL 35, 1203 (2014) R. Chu et al., EDL 29, 974 (2008)

Concentrated electric field at the drain end of the channel

Solution: Replace InGaAs with wide band-gap InP (Eg~1.35 eV)

19

Reducing leakage (5): Doping-graded InP spacer

Doping-graded InP spacer reduces parasitic source/drain resistance and improves Gm.

Gate leakage limits Ioff~300 pA/μm. 20

-0.2 0.0 0.2 0.4 0.610

-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

gm (m

S/

m)

I D,

|IG|

(mA

/m

)

VGS

(V)

0.0

0.4

0.8

1.2

1.6

2.0

2.4

|IG|

VDS

= 0.1 to 0.7 V

0.2 V increment

ID

Ron at

zero Lg

(Ω∙μm)

5 nm UID InP

13 nm UID InP

Doping graded InP

~199 ~364 ~270

Lg-30 nm, 30Å ZrO2

4.5 nm InGaAs

50 nm InAlAs U.I.D buffer

S.I. InP substrate

2 nm 1E19 cm-3

N+InAlAs

Ni/AuTi/Pd/Au Ti/Pd/Au

250 nm 1E17 cm-3

P-InAlAs

100 nm InAlAs U.I.D. buffer

5 nm InAlAs U.I.D. spacer

ZrO2

50 nm N+InGaAs 50 nm N+InGaAs

3 nm

10 nm N+InP

8 nm doping-graded InP

5 nm U.I.D InP5 nm U.I.D InP

Ni/Au

10 nm N+InP

8 nm doping graded InP

C-Y Huang, 2014 IEDM

Reducing leakage (6): Thicker Dielectric

-0.6 -0.3 0.0 0.3 0.610

-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

gm (m

S/

m)

I D,

|IG|

(mA

/m

)

VGS

(V)

ID

|IG|

0.0

0.4

0.8

1.2

1.6

2.0

2.4

VDS

= 0.1 to 0.7 V

0.2 V increment

Minimum Ioff~ 60 pA/μm at VD=0.5V for Lg-30 nm

100:1 smaller Ioff compared to InGaAs spacer

InP graded spacer

21

60 pA/μm

38Å ZrO2

-0.2 0.0 0.2 0.4 0.610

-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

gm (m

S/

m)I D

(m

A/

m)

VGS

(V)

0.0

0.4

0.8

1.2

1.6

2.0

2.4V

DS = 0.1 to 0.7 V

0.2 V increment

InGaAs spacer

C-Y Huang, 2014 IEDM

Leakage now dominated by imperfect isolation

22

Leakage current is independent of gate width → leakage now dominated by imperfect device isolation, by edges of device mesa.

0 100 200 300 400 500 6000

25

50

75

100

3.5x

Wg = 7 um

Wg = 10 um

Wg = 25 um

IO

FF

,min (

pA

/m

)

Gate length (nm)

VDS

= 0.5 V

2.5x

Refractory Contacts to In(Ga)As

Refractory: robust under high-current operation / Low penetration depth: ~ 1 nm / Performance sufficient for 32 nm /2.8 THz node.

10-10

10-9

10-8

10-7

10-6

10-5

1018

1019

1020

1021

N-InGaAs

B=0.6 eV

0.4 eV0.2 eV

0 eV

Electron Concentration, cm-3

Co

nta

ct

Re

sis

tivit

y,

cm

2

step-barrierLandauer

1018

1019

1020

1021

N-InAs

Electron Concentration, cm-3

0.2 eV

B=0.3 eV

step-barrier

B=0 eV

0.1 eV

Landauer

1018

1019

1020

1021

P-InGaAs

Hole Concentration, cm-3

B=0.8 eV

0.6 eV0.4 eV0.2 eV

step-barrierLandauer

Baraskar et al, Journal of Applied Physics, 2013

State-of-art in III-V contacts: ~5*10-9 -cm2 Key: high doping, clean surfaces, high indium content for N-type

23

III-V on Si

Ultrathin InAs-Channel MOSFETs on Si Substrates

Cheng-Ying Huang1, Xinyu Bao2, Zhiyuan Ye2, Sanghoon Lee1,

Hanwei Chiang1, Haoran Li1, Varistha Chobpattana3, Brian

Thibeault1, William Mitchell1, Susanne Stemmer3, Arthur

Gossard1,3, Errol Sanchez2, and Mark Rodwell1

1ECE, University of California, Santa Barbara 2Applied Materials, Santa Clara

3Materials Department, University of California, Santa Barbara

VLSI-TSA 2015

HsinChu, Taiwan

Applied Materials III-V buffer on Si

Rq=3.1 nm RHEED in MBE

26

UCSB III-V FET epitaxy

Rq= 6.9 nm

Surface roughness is degraded after FET epitaxy.

27

TEM images of III-V FET on Si

Lg~20nm 28

Lg~20nm

Short gate length: Lg-20 nm

-0.2 0.0 0.2 0.4 0.610

-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

gm (m

S/

m)I D

(m

A/

m)

VGS

(V)

0.0

0.4

0.8

1.2

1.6

2.0

2.4

SS ~ 142.4 mV

SS ~ 100.8 mV

VDS

= 0.1 to 0.7 V, step 0.2 V

• High Gm~2.0 mS/μm at VD=0.5 V.

• SS~140 mV/dec. at VD=0.5 V and 101 mV/dec. at VD=0.1 V

• High Ion >1.4 mA/um at VGS=1V.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.70.0

0.5

1.0

1.5

I D (

mA

/m

)V

DS (V)

Ron

= 294 Ohm-m

at VGS

= 1.0 V

VGS

= -0.2 V to 1.0 V

0.2 V increment

29

Future Work

Future Work: High Current & Low Leakage

Wide-gap spacer near channel: reduces BTBT

Upper spacer: improves electrostatics

Thick InP spacers add source resistance, reduce Ion.

Solution: composite InP/InGaAs spacer with InGaAsP grades

31

Future Work: High Current & Low Leakage

finFETs: better electostatics→ thick spacers not needed

Need only thin InP spacer to supress BTBT

→ improved on-current

InP spacer formed during S/D regrowth.

32

finFET with surface vs. bulk inversion.

33

16 meV energy splitting

3nm InAs well 3nm InAs well

1.5

nm

AlA

s

bar

rie

r

Cohen-Elias et al., DRC 2013

Next: Superlattice Steep FETs

Objective: low-power VLSI 0.1-0.2 V operation >10:1 less switching energy

Approach: superlattice FET energy filter in source MOVCD regrowth

Impact: low-voltage, high on-current (>> than T-FET) → fast, ultra-low-power VLSI logic

We can make it work.

Long et al., (Purdue/UCSB) IEEE EDL, December 2014

34

How we might build a superlattice FET

A simple extension of present planar III-V MOS process flow...

III-V MOS

For high-performance applications (Ioff=100nA/m) on-currents substantially better than Si at VDD=0.5V

Lower-power applications (SP/LP/UPL) target off-currents as small as 10pA/m InP spacers can provide such small leakage Problem: incrased access resistance, reduced Ion

Best solution: Thin (2-5nm) InP spacers in finFETs fin geometry fixes electrostatics InP spacers fix BTBT.

36

(end)