PIDS: Poster Session 2002 ITRS Changes and 2003 ITRS Key Issues ITRS Open Meeting Dec. 5, 2002...
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Transcript of PIDS: Poster Session 2002 ITRS Changes and 2003 ITRS Key Issues ITRS Open Meeting Dec. 5, 2002...
PIDS: Poster Session2002 ITRS Changes and 2003 ITRS
Key Issues
ITRS Open MeetingDec. 5, 2002
Tokyo
Outline
• PIDS Scope
• 2002 changes
• 2003 key issues
• Focused discussion of logic: 2001 ITRS scaling
PIDS Scope• PIDS = Process Integration, Devices, and
Structures• Deals with
– Process integration and full process flows– MOSFET and passive devices and structures– Device physical and electrical characteristics and
requirements– Reliability
• Subcategories– Memory and logic– RF and Mixed-signal devices– Reliability– Also includes Emerging Research Devices Section (new
in 2001 ITRS)
Changes in 2002 PIDS Chapter• Low Standby Power (LSTP) technology requirements:
physical gate length scaling is slowed by one year compared to 2001 ITRS (see dark boxes, next two slides)– As a result, performance and power dissipation scaling are
slowed
– This more accurately reflects real LSTP technology scaling
• Other changes are relatively minor – Updates
– Clearer explanations in the notes and wording
• Major changes, issues will be dealt with in 2003 ITRS
LSTP Changes for 2002: Near-termYear of Production 2001 2002 2003 2004 2005 2006 2007
DRAM ½ Pitch (nm) 130 115 100 90 80 70 65
MPU / ASIC ½ Pitch (nm) 150 130 107 90 80 70 65
MPU Printed Gate Length (nm) 90 75 65 53 45 40 35
MPU Physical Gate Length (nm) 65 53 45 37 32 28 25
Was Physical gate length low-standby power (LSTP) (nm) [1] 90 75 65 53 45 37 32
I s Physical gate length low-standby power (LSTP) (nm) [1] 100 90 75 65 53 45 37
Was Equivalent physical oxide thickness for LSTP T ox (EOT) (nm) [2] 2.4–2.8 2.2–2.6 2.0–2.4 1.8–2.2 1.6–2.0 1.4–1.8 1.2–1.6
I s Equivalent physical oxide thickness for LSTP T ox (EOT) (nm) [2]
Was Electrical thickness adjustment factor (gate depletion and quantum effects) (nm) [3] 0.8 0.8 0.8 0.8 0.8 0.8 0.5
I s Electrical thickness adjustment factor (gate depletion and quantum effects) (nm) [3]
Was T ox electrical equivalent (nm) [4] 3.4 3.2 3 2.8 2.6 2.4 1.9
I s T ox electrical equivalent (nm) [4]
Was Nominal LSTP power supply voltage (V dd ) (V) [5] 1.2 1.2 1.2 1.2 1.2 1.2 1.1
I s Nominal LSTP power supply voltage (V dd ) (V) [5]
Was Nominal LSTP NMOS sub-threshold current (at 25 C) (pA/ m) [6] 1 1 1 1 1 1 1
I s Nominal LSTP NMOS sub-threshold current (at 25 C) (pA/ m) [6]
Was Nominal LSTP NMOS saturation current drive (I dd ) (at V dd , at 25 C) (mA/ m) [7] 300 300 400 400 400 400 500
I s Nominal LSTP NMOS saturation current drive (I dd ) (at V dd , at 25 C) (mA/ m) [7]
Was Required percent current-drive "mobility/transconductance improvement" [8] 0% 0% 0% 0% 0% 0% 0%
I s Required percent current-drive "mobility/transconductance improvement" [8]
Was LSTP NMOS device (C gate * V dd / Id-NMOS) (ps) [9] 4.61 4.41 2.96 2.68 2.51 2.32 1.81
I s LSTP NMOS device (C gate * V dd / Id-NMOS) (ps) [9] 5.02 4.84 3.31 3.12 2.83 2.66 2.01
Was LSTP relative device performance [10] 1 1.05 1.6 1.7 1.8 2 2.6
I s LSTP relative device performance [10] 1 1.04 1.52 1.61 1.77 1.89 2.50
Was Energy per (W/L gate =3) device switching transition (C gate *(3*L gate )*V2
) (fJ/device) [11] 0.448 0.381 0.277 0.204 0.163 0.123 0.095
I s Energy per (W/L gate =3) device switching transition (C gate *(3*L gate )*V2
) (fJ/device) [11] 0.542 0.471 0.357 0.292 0.216 0.172 0.122
Was Static power dissipation per (W/L gate =3) device (Watts/device) [12] 3.20E-13 2.90E-13 2.30E-13 1.90E-13 1.60E-13 1.30E-13 1.10E-13
I s Static power dissipation per (W/L gate =3) device (Watts/device) [12] 3.60E-13 3.24E-13 2.70E-13 2.34E-13 1.91E-13 1.62E-13 1.22E-13
Table 36c Low Standby Power (LSTP) Technology Requirements—Near-term
LSTP Table Changes for 2002: Long-TermYear of Production 2010 2013 2016
DRAM ½ Pitch (nm) 45 32 22
MPU / ASIC ½ Pitch (nm) 50 35 25
MPU Printed Gate Length (nm) 25 18 13
MPU Physical Gate Length (nm) 18 13 9
Was Physical gate length low-standby power (LSTP) (nm) [1] 22 16 11
I s Physical gate length low-standby power (LSTP) (nm) [1] 28 20 16
Was Equivalent physical oxide thickness for LSTP T ox (EOT) (nm) [2] 0.9-1.3 0.8-1.2 0.7-1.1
I s Equivalent physical oxide thickness for LSTP T ox (EOT) (nm) [2]
Was Electrical thickness adjustment factor (gate depletion and quantum effects) (nm) [3] 0.5 0.5 0.5
I s Electrical thickness adjustment factor (gate depletion and quantum effects) (nm) [3]
Was T ox electrical equivalent (nm) [4] 1.6 1.5 1.4
I s T ox electrical equivalent (nm) [4]
Was Nominal LSTP power supply voltage (V dd ) (V) [5] 1 0.9 0.9
I s Nominal LSTP power supply voltage (V dd ) (V) [5]
Was Nominal LSTP NMOS sub-threshold current (at 25 C) (pA/ m) [6] 3 7 10
I s Nominal LSTP NMOS sub-threshold current (at 25 C) (pA/ m) [6]
Was Nominal LSTP NMOS saturation current drive (Idd) (at V dd , at 25° C) ( A/ m) [7] 500 600 700
I s Nominal LSTP NMOS saturation current drive (Idd) (at V dd , at 25° C) ( A/ m) [7]
Was Required percent current-drive "mobility/transconductance improvement" [8] 10% 30% 50%
I s Required percent current-drive "mobility/transconductance improvement" [8]
Was LSTP NMOS device (C gate * V dd / Id-NMOS) (ps) [9] 1.43 0.91 0.66
I s LSTP NMOS device (C gate * V dd / Id-NMOS) (ps) [9] 1.69 1.05 0.82
Was LSTP relative device performance [10] 3.2 5.1 7
I s LSTP relative device performance [10] 2.97 4.78 6.15
Was Energy per (W/L gate =3) device switching transition (Cgate*(3*Lgate)*V 2 ) (fJ/device) [11] 0.047 0.024 0.014
I s Energy per (W/L gate =3) device switching transition (Cgate*(3*Lgate)*V 2 ) (fJ/device) [11] 0.071 0.034 0.025
Was Static power dissipation per (W/L gate =3) device (Watts/device) [12] 2.00E-13 3.00E-13 3.00E-13
I s Static power dissipation per (W/L gate =3) device (Watts/device) [12] 2.52E-13 3.78E-13 4.32E-13
Table 36d Low Standby Power (LSTP) Technology Requirements—Long-term
Key PIDS Issues for 2003 ITRS• Re-do model-based logic scaling
– Re-examine, improve models: for example, add S/D capacitance to formula for – Re-evaluation of assumptions, requirements for high-performance and low-power
logic, especially maximum gate leakage current limits for high-performance logic
• Begin to evaluate non-classical CMOS technology requirements
• With Design TWG– Review of model-based scaling from a circuit point of view
– Re-evaluation of maximum gate leakage current limit for high-performance logic
– Evaluation of static power dissipation issues for high-performance logic– Use of multi-Vt, multi-Tox: multiple transistor types on a chip
– Circuit design, architecture power conditioning techniques
– Dynamic or electrically alterable Vt
Key PIDS Issues for 2003 ITRS (con’t)• With FEP TWG
– Parasitic Rs,d modeling: PMOS and NMOS– Re-evaluation of maximum gate leakage current for high-performance logic– Leff process control requirements– Review of poly depletion requirements– SOI requirements– Begin to evaluate process and material requirements for non-classical
CMOS
• Memory– Re-evaluation of DRAM scaling: half pitch, EOT, cell size, cell size “a”
factor, number of bits per chip, word line voltage – NVM (flash and FeRAM): changes in scaling of half pitch, cell size and cell
size factor
• Mixed signal– Re-evaluation of overall requirements– Isolation
• Reliability: expand technology requirements
Model-Based MOSFET Scaling Approach: 2001 ITRS• Simple models capture essential MOSFET
physicsembedded in a spreadsheet
– Initial choice of scaled MOSFET parameters is made
– Using spreadsheet, MOSFET parameters are iteratively varied to meet ITRS targets
• High Performance: historical 17%/year performance increase
• Low Power: specific, low level of leakage current
Assumptions for All Logic Types• All modeling is done for nominal devices, room T• Models are simplified (spreadsheet-based), assume basic
transistor functioning doesn’t change– No dynamic Vt– S=85 mV/decade– EOTelectrical = EOT + 0.8 nm/0.5nm0.8 nm for poly gate, 0.5 nm for metal
gate (in 2007 or beyond)– Log(Isd,leak)~-Vt/S
• Gate leakage and junction leakage are each less than Isd,leak for all temperatures
– Id,sat~gm,eff (Vdd-Vt)– Cideal = ox/(EOTelectrical); Cgate = Cideal + Cparasitic– =(Cgate Vdd)/(Id,sat)= intrinsic transistor delay – Parasitic Rs,d is included (20-30% of Vdd/Id,sat = Ron)– PMOS is like NMOS, except PMOS Id,sat is 40-50% of NMOS Id,sat – S/D capacitance is ignored in calculating DIBL is ignored in calculating
Isd,leak
Drivers for High-Performance and Low-Power Logic • High performance chips (MPU, for example)
– Driver: maximize chip speedmaximize transistor performance• Goal of ITRS scaling: 1/ increases at ~ 17% per year,
historical rate–Must maximize Ion
–Consequently, Ileak is relatively high
• Low power chips (mobile applications)– Driver: minimize chip powerminimize Ileak (to conserve
battery power)• Goal of ITRS scaling: specific, low level of Ileak
• Consequently, 1/ is relatively reduced
Scaling of Leakage Current and 1/
Isd,leak, High Perf.
Isd,leak, Low Power (LSTP)
1/, Low Power (LSTP)
1/ , High Perf.
Key MOSFET Scaling Results
• High-performance logic– Average 17%/yr improvement in 1/is attained– Isd,leak is very high, particularly for 2007 and
beyond chip static power dissipation scaling is an issue
• Assumption: Igate Isd,leak uncomfortably large Igate
• Low-power logic (particularly LSTP)– Very low Isd,leak target is met
• Igate Isd,leak Igate is very low: difficult to meet this
– 1/scales considerably slower than for high-performance
Difficult Transistor Scaling Issues• Previously discussed scaling results involve high-level,
idealized MOSFET physics– Assumption: highly scaled MOSFETs with required characteristics
can be successfully fabricated
• All lateral and vertical MOSFET dimensions (EOT [gate dielectric equivalent oxide thickness], xj’s, spacer width, etc.) are scaling down rapidly along with physical gate length (Lg)
• With scaling, increasing difficulty is expected in meeting transistor requirements
– High gate leakage• Direct tunneling increases rapidly as EOT is reduced
– Poly depletion in gate electrodeincreased effective EOT, reduced Ion
– Scaling S/D extension: xj – s-high Rseries,s/d, reduced Ion
– Etc.
• Material and process solutions needed
Difficult Transistor Scaling Issues: Key Potential Solutions• High gate leakage
– Direct tunneling increases rapidly as EOT is reduced– Potential solution: high-k gate dielectric (2005, low
power logic)• Poly depletion in gate electrodeincreased
effective EOT, reduced Ion
– Potential solution: metal gate electrode (2007 and beyond)
• Scaling S/D: xj – s-high Rseries,s/d, reduced Ion
– Potential solutions• S/D extension: alternate annealing, doping (2007 and
beyond)• Deep S/D: raised S/D, alternate contacts (2007 and
beyond)
2001 ITRS Projections Versus Simulations of Direct Tunneling Gate Leakage Current Density for LSTP Logic
1.E-07
Implementation of high K will likely be driven by LSTP in ~2005
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
2001 2003 2005 2007 2009 2011 2013 2015
Year
Jg
ate
(A
/cm
2 )
0
0.5
1
1.5
2
2.5
3
EO
T (nm
)
Simulated Jgate, oxynitride
Specified Jgate, ITRS
EOT
Beyond this point, oxynitride too leaky; high K needed
(Simulations courtesy of C. Osburn, NCSU and ITRS)
Limits of Scaling Planar, Bulk MOSFETs• 65 nm tech. generation (2007) and beyond: increased difficulty in
meeting all device requirements with classical planar, bulk CMOS (even with material and process solutions: high K, metal electrodes, ….)
– Control of SCE – Impact of quantum effects and statistical variation– Impact of high substrate doping– Control of series S/D resistance (Rseries,s/d)– Others
• Alternative device structures (non-classical CMOS) may be utilized: being pursued by industry in parallel with material and process solutions
– Band engineered transistorsimproved transport/mobility– Ultra thin body SOI & Double gate SOI - Including FinFET and Vertical
FETs
Band Engineered MOSFETs: Surface-channel Strained-Si MOSFET Structures
Graded Layer 0.05
= x
Drain
p+
n- Si1-yGeyy =
y
n+ Si Substrate
n+ poly
n Strained Si
Source
SiO
p- Si1-yGey Graded Layer y = 0.05
y = x
p+ Si Substrate
n+ poly
p Strained Si
Source DrainSiO2
Gate
n+ n+
high mo bilitychannels
p- Relaxed Si1-xGex
2
Gate
n- Relaxed Si1-xGex
Strained Si1-xGex
Courtesy of J. Hoyt - MIT
p+
+ Increased effective mobility, increased Ion
- Difficult integration issues: manufacturability
- Compatibility with ultra-thin body SOI
- Cost
Schematic Cross Sections of Non-Classical CMOS Devices
Bulk MOSFET Ultra-Thin Body MOSFET Double-Gate SOI MOSFET
Electron Current Flow
Ultra-thin silicon body
Top & bottom gates
Vertical MOSFET
Double gates
Drain
Source
SiO2
Simplified Views of FinFET Double-Gate Device
T-J. King and C. Hu, UC/Berkeley
Key advantage: relatively conventional processing, largely compatible with current techniques
FinFET(one type of double-gate
MOSFET)
S G DS G DSiO2
BOXBOX
GateGate
DrainDrainSourceSource
SiOSiO22 SiOSiO22
Schematic Cross-Section
Source Drain
Poly Gate
Fin
Source Drain
Poly Gate
Fin
Top View