Source: Google Earth SSIR* CoGAA MOSFETs DG MOSFETs 0.31 …
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Previous Approaches Dong-Il Moon, Jin-Woo Han, and Meyya Meyyappan Center for Nanotechnology, NASA Ames Research Center E-mail: [email protected] Introduction Fabrication of Suspended SiNWs Conclusions SiNW by One-Step Etching Route (This Work) Electrical Characteristics Space Applications CMOS Technology in Space Radiation Effects on SiNW GAA FETs ` Artificial satellites Source: Google Earth Satellite industry SSIR* • Thousands of the artificial satellites are on orbit. • Continuous growth of the satellite industry is expected. *SSIR: Sate of the Satellite Industry Report, satellite industry association (2012) Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor Reliability Performance On Earth Reliability Performance In Space Gate Gate Gate Bulk silicon Single-gate Tri-gate Gate-all-around Buried oxide Planar Non-planar Reliability Performance Excellent channel controllability Buried oxide (BOX) Si substrate SiGe Si substrate Top silicon Silicon Hard mask SOI process SEG process SOI: silicon-on-insulator SEG: selective epitaxial growth SiNW: silicon nanowire SEG layers Hard mask Anisotropic etching Suspended SiNW Sacrificial layer Si substrate Sacrificial layer removal • Suspended SiNW: basic building block for GAA FETs • Previous approaches: SOI substrate or epitaxial growth on bulk - CMOS low-compatible, high cost, and low throughput PR PR SF 6 Bulk-Si Bulk-Si Polymer C 4 F 8 *PR: photo-resist Anisotropic etching Polymerization (passivation: C 4 F 8 ) Isotropic etching (SF 6 ) TCP 9400DFM Exelan HPT Reactive Ion Etching Si bulk substrate S D SiNW G I D I leak Si bulk substrate S D G I leak -1.0 -0.5 0.0 0.5 1.0 10 -13 10 -11 10 -9 10 -7 10 -5 Drain current, I D (A) Gate voltage, V G (V) 0.0 0.5 1.0 0 2 4 6 8 Drain current, I D (A) Drain voltage, V D (V) V G = 0 V ~ 1 V 0.25 V step 25 50 75 100 0.00 0.05 0.10 0.15 0.20 W NW / H NW 6 / 10 nm 10 / 13 nm 13 / 16 nm 16 / 19 nm DIBL (V/V) Gate length, L G (nm) 25 50 75 100 60 70 80 90 100 W NW / H NW 6 / 10 nm 10 / 13 nm 13 / 16 nm 16 / 19 nm SS (mV/dec) Gate length, L G (nm) Process Optimization Process Flow of SiNW GAA FETs Increment of isotropic etching time Optimization of height and width of SiNWs • Bulk substrate • Suspended SiNW by one-step etching route • Sacrificial oxidation • Oxide dep. and CMP • Partial oxide etching (STI) • Thermal oxidation • in-situ n + poly-Si dep. • Poly-Si CMP and HM dep. • Gate patterning • Spacer formation • S/D implantation • RTA and H 2 annealing SiNW Gate S D (100) p-type a-a’ b-b’ 100 nm • SiNW GAA FET on a bulk substrate DIBL: 150 mV/V, SS: 87 mV/dec, I ON /I OFF > 10 6 • Excellent immunity against SCEs GAA structure with SiNW channel ` 60 27 Co 60 28 Ni 0.31 MeV b - 1.48 MeV b - 1.1732 MeV g • 60 Co (Cobalt-60) - Common radiation source - g-ray with around 1.3 MeV c.f.) Part of cosmic ray • Specific radiation condition - Total dose : 1, 5, 10 Mrad(SiO 2 ) - Dose rate : 460 rad(SiO 2 )/s c.f.) 1 Mrad : typical tolerance of radiation hardened circuit 1 10 -180 -150 -120 -90 -60 -30 0 V TH (mV) Total dose (Mrad) L g = 25 nm L g = 30 nm L g = 35 nm L g = 50 nm L g = 100 nm 1 10 0 5 10 15 20 SS (mV/dec) Total dose (Mrad) L g = 25 nm L g = 30 nm L g = 35 nm L g = 50 nm L g = 100 nm 20 40 60 80 100 0 5 10 15 20 SS (mV/dec) Gate length, L g (nm) GAA MOSFETs 1 Mrad 5 Mrad 10 Mrad DG MOSFETs (J. Nam et al) 0.5 Mrad 20 40 60 80 100 -150 -120 -90 -60 -30 0 V TH (mV) Gate length, L g (nm) GAA MOSFETs 1 Mrad 5 Mrad 10 Mrad DG MOSFETs (J. Nam et al) 0.5 Mrad “Rebound effect” Radiation Source Dose Dependency Advantage of GAA Gate SiNW * Isolation oxide Bulk substrate N f & N it Gate Buried oxide Bulk substrate Channel HM ** N f & N it GAA MOSFETs DG MOSFETs • GAA MOSFETs - All N f and N it were screened out by the gate. • DG MOSFETs - Some portions of N f and N it influenced the channel. *SiNW: Silicon nanowire **HM: Hard mask ` Junction Modification Channel (p) Drain (n+) Gate -20 -10 0 10 20 30 10 14 10 16 10 18 10 20 10 Location (nm) -20 -10 0 10 20 30 10 14 10 16 10 18 10 20 10 22 Net doping concentration (cm -3 ) Location (nm) SCEs ↑ TID Drain (n+) Gate p Spacer n+ p Spacer n+ N f & N it N f & N it L ext Original GAA MOSFETs Junction-modified GAA MOSFETs ( Additional RTP : 1000 C o for 5 s) Increase SCEs, but suppress TID effects Silvaco simulation Optimization of SiNW GAA FETs -1.2 -0.9 -0.6 -0.3 0.0 0.3 10 -13 10 -11 10 -9 10 -7 10 -5 10 -3 Drain current, I d (A) Gate voltage, V g (V) Original GAA MOSFETs Initial, 10 Mrad Junction-modified GAA MOSFETs Initial, 10 Mrad V d = 1 V L g = 25 nm Original GAA FETs Junction-modified GAA FETs V TH,initial -0.332 V -0.600 V SS initial 76.9 mV/dec 108.5 mV/dec • Increased short-channel effects (SCEs) Original GAA FETs Junction-modified GAA FETs V TH - 60 mV - 0.2 mV SS 10.9 mV/dec 3.3 mV/dec • Suppressed total ionizing dose (TID) effects Gate L G W NW *source: F. Laermer et al., US-Patent No. 5501893 * • An one-step plasma etching route was developed to form a suspended silicon nanowire on a bulk substrate. • A gate-all-around field-effect transistor was fabricated and characterized for radiation hardening applications. • The fabricated devices showed stronger radiation-tolerance than the double-gate MOSFETs due to the separation between the channel and the isolation oxide. • The role of the gate spacer on TID effects was observed and verified through the overlapped junction profile. Optical litho. SiNW from one time loading Cleaning PR ashing Aniso. etch Polymer dep. Iso. etch HM etch
Transcript of Source: Google Earth SSIR* CoGAA MOSFETs DG MOSFETs 0.31 …
Previous Approaches
Dong-Il Moon, Jin-Woo Han, and Meyya Meyyappan
Center for Nanotechnology, NASA Ames Research Center
E-mail: [email protected]
Fabrication of Suspended SiNWs
Conclusions
SiNW by One-Step Etching Route (This Work)
Electrical Characteristics
Space Applications CMOS Technology in Space
Radiation Effects on SiNW GAA FETs
`
Artificial satellites
Source: Google Earth
Satellite industry
SSIR*
• Thousands of the
artificial satellites
are on orbit.
• Continuous
growth of the
satellite industry
is expected.
*SSIR: Sate of the Satellite
Industry Report, satellite
industry association (2012)
Fabrication of a Silicon Nanowire on a Bulk Substrateby Use of a Plasma Etching and Total Ionizing Dose Effects
on a Gate-All-Around Field-Effect Transistor
Reliability
Performance
On Earth
Reliability
Performance
In Space Gate GateGate
Bulk silicon
Single-gate Tri-gate Gate-all-around
Buried oxide
Planar Non-planar
Reliability Performance
Excellent
channel controllability
Buried oxide (BOX)
Si substrate
SiGe
Si substrate
Top silicon Silicon
Hard mask
SOI process SEG process
SOI: silicon-on-insulator
SEG: selective epitaxial growth
SiNW: silicon nanowire
SEG layers
Hard mask
Anisotropic
etching
Suspended SiNWSacrificial layer
Si substrate
Sacrificial layer
removal
• Suspended SiNW: basic building block for GAA FETs• Previous approaches: SOI substrate and epitaxial growth
- CMOS low-compatible, high cost, and low throughput
• Suspended SiNW: basic
building block for GAA
FETs
• Previous approaches:
SOI substrate or
epitaxial growth on bulk
- CMOS low-compatible,
high cost, and low
throughput
PR PRSF6
Bulk-Si Bulk-Si
PolymerC4F8
*PR: photo-resist
Anisotropic etching
Polymerization
(passivation: C4F8)
Isotropic etching (SF6)
TCP 9400DFM
Exelan HPT
Reactive Ion Etching
Si bulk substrate
S DSiNW
GID
Ileak
Si bulk substrate
S DG
Ileak
-1.0 -0.5 0.0 0.5 1.010
-13
10-11
10-9
10-7
10-5
Dra
in c
urr
en
t, I
D (
A)
Gate voltage, VG (V)
0.0 0.5 1.0
0
2
4
6
8
Dra
in c
urr
en
t, I
D (A
)
Drain voltage, VD (V)
VG = 0 V ~ 1 V
0.25 V stepSi bulk substrate
S DSiNW
GID
Ileak
Si bulk substrate
S DG
Ileak
-1.0 -0.5 0.0 0.5 1.010
-13
10-11
10-9
10-7
10-5
Dra
in c
urr
en
t, I
D (
A)
Gate voltage, VG (V)
0.0 0.5 1.0
0
2
4
6
8
Dra
in c
urr
en
t, I
D (A
)
Drain voltage, VD (V)
VG = 0 V ~ 1 V
0.25 V step
25 50 75 1000.00
0.05
0.10
0.15
0.20 W
NW / H
NW
6 / 10 nm
10 / 13 nm
13 / 16 nm
16 / 19 nm
DIB
L (
V/V
)
Gate length, LG (nm)
25 50 75 10060
70
80
90
100
WNW
/ H
NW
6 / 10 nm
10 / 13 nm
13 / 16 nm
16 / 19 nm
SS
(m
V/d
ec
)
Gate length, LG (nm)
25 50 75 1000.00
0.05
0.10
0.15
0.20 W
NW / H
NW
6 / 10 nm
10 / 13 nm
13 / 16 nm
16 / 19 nm
DIB
L (
V/V
)
Gate length, LG (nm)
25 50 75 10060
70
80
90
100
WNW
/ H
NW
6 / 10 nm
10 / 13 nm
13 / 16 nm
16 / 19 nm
SS
(m
V/d
ec
)
Gate length, LG (nm)
Process Optimization
Process Flow of SiNW GAA FETs
Increment of isotropic etching time
Optimization of height and width of SiNWs
• Bulk substrate
• Suspended SiNW
by one-step etching route
• Sacrificial oxidation
• Oxide dep. and CMP
• Partial oxide etching (STI)
• Thermal oxidation
• in-situ n+ poly-Si dep.
• Poly-Si CMP and HM dep.
• Gate patterning
• Spacer formation
• S/D implantation
• RTA and H2 annealing
SiNW
Gate
S
D
(100) p-type
a-a’
b-b’
100 nm
• SiNW GAA FET on a bulk substrate
DIBL: 150 mV/V, SS: 87 mV/dec, ION/IOFF > 106
• Excellent immunity against SCEs
GAA structure with SiNW channel
`
60
27Co
60
28Ni
0.31 MeV b-
1.48 MeV b-
1.1732 MeV g
• 60Co (Cobalt-60)
- Common radiation source
- g-ray with around 1.3 MeV
c.f.) Part of cosmic ray
• Specific radiation condition
- Total dose : 1, 5, 10 Mrad(SiO2)
- Dose rate : 460 rad(SiO2)/s
c.f.) 1 Mrad : typical tolerance of
radiation hardened circuit
1 10-180
-150
-120
-90
-60
-30
0
V
TH (
mV
)
Total dose (Mrad)
Lg = 25 nm
Lg = 30 nm
Lg = 35 nm
Lg = 50 nm
Lg = 100 nm
1 10
0
5
10
15
20
S
S (
mV
/de
c)
Total dose (Mrad)
Lg = 25 nm
Lg = 30 nm
Lg = 35 nm
Lg = 50 nm
Lg = 100 nm
20 40 60 80 100
0
5
10
15
20
S
S (
mV
/de
c)
Gate length, Lg (nm)
GAA MOSFETs
1 Mrad
5 Mrad
10 Mrad
DG MOSFETs (J. Nam et al)
0.5 Mrad
20 40 60 80 100-150
-120
-90
-60
-30
0
V
TH (
mV
)
Gate length, Lg (nm)
GAA MOSFETs
1 Mrad
5 Mrad
10 Mrad
DG MOSFETs (J. Nam et al)
0.5 Mrad
“Rebound effect”
Radiation Source Dose Dependency
Advantage of GAA
Gate
SiNW*
Isolation oxide
Bulk substrate
Nf & Nit
Gate
Buried oxide
Bulk substrate
Channel
HM**
Nf & Nit
GAA MOSFETs DG MOSFETs• GAA MOSFETs
- All Nf and Nit
were screened
out by the gate.
• DG MOSFETs- Some portions of
Nf and Nit
influenced
the channel.
*SiNW: Silicon nanowire
**HM: Hard mask
`
Junction Modification
Channel
(p)
Drain
(n+)
Gate
-20 -10 0 10 20 3010
14
1016
1018
1020
1022
Location (nm)-20 -10 0 10 20 30
1014
1016
1018
1020
1022
Net
do
pin
g
co
ncen
trati
on
(c
m-3)
Location (nm)
SCEs ↑TID ↓
Drain
(n+)
Gate
p
Spacer
n+ p
Spacer
n+
Nf & Nit Nf & Nit
Lext
Original GAA MOSFETsJunction-modified GAA MOSFETs
( Additional RTP : 1000 Co for 5 s)
Increase SCEs, but suppress TID effects
Silvaco simulation
Optimization of SiNW GAA FETs
-1.2 -0.9 -0.6 -0.3 0.0 0.310
-13
10-11
10-9
10-7
10-5
10-3
Dra
in c
urr
en
t, I
d (
A)
Gate voltage, Vg (V)
Original GAA MOSFETs
Initial, 10 Mrad
Junction-modified GAA MOSFETs
Initial, 10 Mrad
Vd = 1 V
Lg = 25 nm
Original GAA FETs Junction-modified GAA FETs
VTH,initial -0.332 V -0.600 V
SSinitial 76.9 mV/dec 108.5 mV/dec
• Increased short-channel effects (SCEs)
Original GAA FETs Junction-modified GAA FETs
VTH - 60 mV - 0.2 mV
SS 10.9 mV/dec 3.3 mV/dec
• Suppressed total ionizing dose (TID) effects
Gate
LG
WNW
*source: F. Laermer et al., US-Patent No. 5501893
*
Increment of isotropic etching time
Optimization of height and width of SiNWs
Increment of isotropic etching time
Optimization of height and width of SiNWs
Increment of isotropic etching time
Optimization of height and width of SiNWs
Increment of isotropic etching time
Optimization of height and width of SiNWs
Increment of isotropic etching time
Optimization of height and width of SiNWs
Increment of isotropic etching time
Optimization of height and width of SiNWs
• An one-step plasma etching route was developed to form a suspended silicon
nanowire on a bulk substrate.
• A gate-all-around field-effect transistor was fabricated and characterized for
radiation hardening applications.
• The fabricated devices showed stronger radiation-tolerance than the double-gate
MOSFETs due to the separation between the channel and the isolation oxide.
• The role of the gate spacer on TID effects was observed and verified through the
overlapped junction profile.
Optical
litho.
SiNW from one
time loadingCleaning
PR
ashing
Aniso.
etch
Polymer
dep.
Iso.
etch
HM
etch
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