RCU Status

1. RCU design

2. RCU prototypes

3. RCU-SIU-RORC integration

4. RCU system for TPC test 2002

HiB, UiB, UiO

1. RCU design –system architecture

RCU design –control flow

• State machines

RCUresource

& priority manager

TTCrxFEE bus controller

SIUcontroller DDL

commanddecoder

FEESC

Slow control

Watch dog:health agentDebugger

PCI core

Huffman encoder

RCU design - data flow

TTCrx registers

Event memory

Event fragment pointer list

TTC controller

FEE bus controller

FEE bus controller

Configuration memory

FEE bus controller

Slow control

SIU controller fifo

SIUHuffman encoder

• Shared memory modules

2. RCU prototypes

• Prototype I– Commercial OEM-PCI board

– FEE-board test (ALTRO + FEE bus)

– SIU integration

– Qtr 3, 2001 – Qtr 2, 2002

• Prototype II– Custom design

– All functional blocks

– PCB: Qtr 2, 2002

– Implementation of basic functionality (FEE-board -> SIU): Qtr 2, 2002

– Implementation of essential functionalty: Qtr 4, 2002

• Prototype III – SRAM FPGA ->

masked version or Antifuse FPGA (if needed)

• RCU production– Qtr 2, 2003

RCU prototype I• Commercial OEM-PCI board

– ALTERA FPGA APEX EP20K400– SRAM 4 x 32k x 16bits– PMC I/O connectors (178 pins)– Buffered I/O (72 pins)

RCU prototype I

• Implementation of basic test functionality– FEE-board test (ALTRO + FEE bus)

– SIU integration

PCI core

SIU card

PCI bus FPGA APEX20k400

internalSRAM

I/O

onboard SRAM

4 x 32k x 16

FLASH EEPROM

FEE-busdaughter board

PMC

FEE boards trigger

PCI coreSIU-CMCinterface

SIU

PCI bus

FPGA

internalSRAM

Memory D32

> 2 MB

FLASH EEPROM

SC TTC FEE-bus

RCU prototype II• Implementation of essential functionality

– Custom design

– All functional blocks

RCU prototype II - schematics

Programming model• Development version – status December 2001

PCLINUX RH7.1 (2.4.2)

PCI coremailboxmemory

SIU controller

FEE buscontroller

FEE bus

ALTROemulator

PCI-tools

RCU-API

device driver

ALTROemulator

PLDA board

SIU

DDL

3. SIU-RORC integration

SIU controllerPCI core

SIUinterface

PCI bus

FPGA

SRAM

LINUX/NTPLDA/PCI-

toolsRCU-API

devicer driver SIU

PCI bridge Glue logicDIU

interface

PCI bus

LINUXDDL/PCI-

toolspRORC-APIdevice driver DIU

DDL

RCU prototype I

pRORC

• SIU-controller functions implemented:– Read RCU status word

– Write register to RCU

– Read events from RCU

• Not yet implemented:– Write block to RCU

– Read block from RCU

SIU-RORC integration• System setup, Bergen, Nov./Dec. 2001

SIU-RORC integration• Result

data control

PC1:write memory block to FPGA internal SRAM

DDL

PC1 memory block

RCU internal SRAM

SIU

DIU

PC2 ”bigphys” memory area

SIU controller:wait for

READY-TO-RECEIVE

PC2:allocate bigphys area,

init link + pRORC

PC2:send DDL-FEE command READY-TO-RECEIVE

SIU controller:strobe data into SIU

pRORC:copy data into bigphys area

via DMA=

4. RCU system for TPC test 2002

• RCU requirements– Readout of 4 FEE-bus branches

• 2 RCU prototypes II• Fallback solution:

– 4 RCU prototypes I (3 boards are available)

– Basic RCU functionalty• Develop logics for readout of all FEE cards

on FEE-bus• Include external SRAM• Develop Manager SM for controlling data

transfer from FEE-bus to SIU• Include simple trigger and event-ID

– Interface to DAQ• DATE • DAQ via DDL

– 2 pRORC (including SIU + DIU)– Integrate pRORC into DATE (DAQ-group)

• Fallback solution:– DAQ via RCU-PCI

RCU system for TPC test 2002

FEE-bus controller

SIU controller

PCI core

SIUinterface

PCI bus

FPGA

SRAM

LINUX RH7.xDATE

PLDA/PCI-toolsRCU-API

devicer driver SIU

PCI bridge Glue logicDIU

interface

PCI bus

LINUX RH7.xDATE

DDL/PCI-toolspRORC-APIdevice driver DIU

DDL

RCU prototype II/I

pRORC

ext. SRAM FLASH

Manager

FEE-bus

Trigger

FEE-boards

Programming model• TPC test version – summer 2002

PCLINUX RH7.1 (2.4.2)

PCI coremailboxmemory

SIU controller

FEE buscontroller

FEE bus

FEE boards

PCI-tools

RCU-API

device driver

Prototype II(Prototype I)

SIU

DDL

DATE

FEE configurator

RCUresource

& priority manager

Open questions (1)

• Radiation induced corruption of SRAM– Configuration SRAM bit toggle rate

> O(1/hour)• Replace SRAM based FPGAs with

– masked versions (expensive)

– or Antifuse FPGAs

(additional prototyping – 6 months?)

– Configuration SRAM bit toggle rate

< O(1/hour)• External watch dog circuit

– periodical check of configuration SRAM

– reload FPGA configuration

– STAR experience• TPC and FTPC FEE: SRAM-based FPGAs

• Not a single incident observed in approx. 100 days of operation

– Estimate for ALICE• SRAM bit toggle rate < O(1/day)???

-> Quantitative study needed - wait for SIU results

Open questions (2)

• Firmware– Interface to many different subdetectors

(SC, Trigger, DDL, DAQ, FEE-bus)

– Fully debugged hardware/firmware/software not always available

-> develop emulators - needs experts and time

• Software– High level test software

– DATE applications

– Online monitoring for TPC test

-> who?