Circuiti sequenziali 1

Progettazione di circuiti e sistemi VLSIProgettazione di circuiti e sistemi VLSI

Anno Accademico 2010-2011

Lezione 7

12.4.2011

Circuiti sequenziali

Circuiti sequenziali 2

Sequential Logic

2 storage mechanisms

• positive feedback

• charge-based

COMBINATIONALLOGIC

Registers

Outputs

Next state

CLK

Q D

Current State

Inputs

Circuiti sequenziali 3

Naming Conventions

• In our text:– a latch is level sensitive– a register is edge-triggered

• There are many different naming conventions– For instance, many books call edge-

triggered elements flip-flops– This leads to confusion however

Circuiti sequenziali 4

Latch versus Register Latch

stores data when clock is low

D

Clk

Q D

Clk

Q

• Register

stores data when clock rises

Clk Clk

D D

Q Q

Circuiti sequenziali 5

Latches

In

clk

In

Out

Positive Latch

CLK

DG

Q

Out

Outstable

Outfollows In

In

clk

In

Out

Negative Latch

CLK

DG

Q

Out

Outstable

Outfollows In

Circuiti sequenziali 6

Latch-Based Design

• N latch is transparentwhen = 0

• P latch is transparent when = 1

NLatch

Logic

Logic

PLatch

Circuiti sequenziali 7

Timing Definitions

t

CLK

t

D

tc2 q

tholdtsu

t

Q DATASTABLE

DATASTABLE

Register

CLK

D Q

Circuiti sequenziali 8

Maximum Clock Frequency

FF’s

LOGIC

tp,comb

Also:tcdreg + tcdlogic > thold

tcd: contamination delay = minimum delaytclk-Q + tp,comb + tsetup =

T

Circuiti sequenziali 9

Positive Feedback: Bi-StabilityVi1 Vo2

Vo2 =Vi1

Vo1 =Vi2

Vi1

A

C

B

Vo2

Vi1=Vo2

Vo1 Vi2

Vi2=Vo1

Circuiti sequenziali 10

Meta-Stability

Gain should be larger than 1 in the transition region

A

C

B

Vi2

5V

o1

Vi1 5Vo2

A

C

B

Vi2

5V

o1

Vi1 5Vo2

Meta-Stability

Gain should be larger than 1 in the transition region

A

C

B

Vi2

5V

o1

Vi1 5Vo2

A

C

B

Vi2

5V

o1

Vi1 5Vo2

Circuiti sequenziali 11

Meta-Stability

Gain should be larger than 1 in the transition region

A

C

B

Vi2

5V

o1

Vi1 5Vo2

A

C

B

Vi2

5V

o1

Vi1 5Vo2

Circuiti sequenziali 12

Writing into a Static Latch

CLK

CLK

CLK

D

Q D

CLK

CLK

D

Converting into a MUXForcing the state(can implement as NMOS-only)

Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states

Circuiti sequenziali 13

Mux-Based LatchesNegative latch(transparent when CLK= 0)

Positive latch(transparent when CLK= 1)

CLK

1

0D

Q 0

CLK

1D

Q

InClkQClkQ InClkQClkQ

Circuiti sequenziali 14

Mux-Based Latch

CLK

CLK

CLK

D

Q

Circuiti sequenziali 15

Mux-Based Latch

CLK

CLK

CLK

CLK

QM

QM

NMOS only Non-overlapping clocks

Circuiti sequenziali 16

Master-Slave (Edge-Triggered) Register

1

0D

CLK

QM

Master

0

1

CLK

Q

Slave

QM

Q

D

Two opposite latches trigger on edge – Master negative latch/Slave positive latchAlso called master-slave latch pair

Circuiti sequenziali 17

Master-Slave Register

QM

Q

D

CLK

T2I2

T1I1

I3 T4I5

T3I4

I6

Multiplexer-based latch pair

Positive edge triggered

Circuiti sequenziali 18

Reduced Clock Load Master-Slave Register

D QT1 I1

CLK

CLK

T2

CLK

CLKI2

I3

I4

Circuiti sequenziali 19

Avoiding Clock OverlapCLK

CLK

A

B

(a) Schematic diagram

(b) Overlapping clock pairs

X

D

Q

CLK

CLK

CLK

CLK

Circuiti sequenziali 20

Overpowering the Feedback Loop ─

Cross-Coupled Pairs

Forbidden State

S

S

R

QQ

Q

QRS Q

Q00 Q

101 0

010 1

011 0RQ

NOR-based set-reset

Circuiti sequenziali 21

Cross-Coupled NAND

S

QR

Q

M1

M2

M3

M4

Q

M5S

M6CLK

M7 R

M8 CLK

VDD

Q

Cross-coupled NANDsAdded clock

This is not used in datapaths any more,but is a basic building memory cell

Circuiti sequenziali 22

Storage Mechanisms

D

CLK

CLK

Q

Dynamic (charge-based)

CLK

CLK

CLK

D

Q

Static

Circuiti sequenziali 23

Making a Dynamic Latch Pseudo-Static

D

CLK

CLK

D

Circuiti sequenziali 24

Other Latches/Registers: C2MOS

M1

D Q

M3CLK

M4

M2

CLK

VDD

CL1

X

CL2

Master Stage

M5

M7CLK

CLK M8

M6

VDD

“Keepers” can be added to make circuit pseudo-static

Circuiti sequenziali 25

Insensitive to Clock-Overlap

M1

D Q

M4

M2

0 0

VDD

X

M5

M8

M6

VDD

(a) (0-0) overlap

M3

M1

D Q

M2

1

VDD

X

M71

M5

M6

VDD

(b) (1-1) overlap

Circuiti sequenziali 26

Avoiding Clock OverlapCLK

CLK

A

B

(a) Schematic diagram

(b) Overlapping clock pairs

X

D

Q

CLK

CLK

CLK

CLK

Circuiti sequenziali 27

CLK

CLK

1/1 0/0

Circuiti sequenziali 28

Other Latches/Registers: TSPC

CLKIn

VDD

CLK

VDD

In

Out

CLK

VDD

CLK

VDD

Negative latch(transparent when CLK= 0)

Positive latch(transparent when CLK= 1)

Circuiti sequenziali 29

Circuiti sequenziali 30

Including Logic in TSPC

CLKIn CLK

VDDVDD

QPUN

PDN

CLK

VDD

Q

CLK

VDD

In1

In1 In2

AND latchExample: logic inside the latch

Circuiti sequenziali 31

TSPC Register

CLK

CLK

D

VDD

M3

M2

M1

CLK

Y

VDD

Q

Q

M9

M8

M7

CLK

X

VDD

M6

M5

M4

Circuiti sequenziali 32

Pulse-Triggered LatchesAn Alternative Approach

Master-Slave Latches

D

Clk

Q D

Clk

Q

Clk

DataD

Clk

Q

Clk

Data

Pulse-Triggered Latch

L1 L2 L

Ways to design an edge-triggered sequential cell:

Circuiti sequenziali 33

Pulsed Latches

CLKGD

VDD

M3

M2

M1

CLKG

VDD

M6

Q

M5

M4

CLK

CLKG

VDD

XMP

MN

(a) register (b) glitch generation

Circuiti sequenziali 34

Pulsed LatchesHybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :

P1

M3

M2D

CLK

M1

P3

M6

Qx

M5

M4

P2