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MSP430FR59xx/FR58xx Training

Texas Instruments 2013

1

Agenda • MSP430™ FRAM Technology • Introduction to MSP430FR59xx • MSP430FR59xx/FR58xx Architecture & Core Peripherals • Getting Started • MSP430™ DriverLib Quick Intro + Tips & Tricks • MSP430™ ADC12_B Hands-On Labs • MSP430™ MPU Overview & Hands-On Labs

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MSP430™ FRAM Technology

3

Industry’s First Ultra-Low-Power FRAM MCU

Speed up designs – Tools, software and system solution

• Easily change memory partitioning in software • Eliminate need for separate EEPROM and battery-backed SRAM

• Write more than 160x faster using >400x less energy • Unlimited write endurance • Non-volatile memory: data retention possible in ALL power modes

• Low cost development kits and code compatibility across MSP platform • Industry’s broadest RF technology & tools portfolio • Training and documentation

Experience unparalleled freedom with unified memory

More sensors in new places with ultra-low-power memory

4

All-in-one: FRAM MCU delivers max benefits FRAM SRAM EEPROM Flash

Non-volatile Retains data without power

Write speed (13 KB)

Average active Power [µA/MHz] 16bit word access by the CPU

Write endurance

Dynamic Bit-wise programmable

Unified memory Flexible code and data partitioning

5 * Based on devices from Texas Instruments

All-in-one: FRAM MCU delivers max benefits FRAM SRAM EEPROM Flash

Non-volatile Retains data without power

Write speed (13 KB)

Average active Power [µA/MHz] 16bit word access by the CPU

Write endurance

Dynamic Bit-wise programmable

Unified memory Flexible code and data partitioning

Yes

Yes

Yes

No

10ms 2secs <10ms 1 sec

50,000+ <60 100 260

10,000 100,000 Unlimited Unlimited

Yes Yes No No

Yes No No No

6 * Based on devices from Texas Instruments

FRAM | Unified Memory

One device supporting multiple options “slide the bar as needed” Multiple device variants may be required

• Easier, simpler inventory management

• Lower cost of issuance / ownership

• Faster time to market for memory modifications

Before With FRAM

To get more SRAM you may have to buy 5x the needed FLASH

1kB EEPROM

Often an additional

chip is needed

14kB Flash 2kB

SRAM

16kB Flash (Program)

2Kb SRAM

32kB Flash 6kB

SRAM

16kB Universal FRAM

Data vs. program memory partitioned as needed

7

FRAM | Endurance

Write Endurance

Trillions

10,000 cycles

> 1,000,000,000,000,000 cycles

Supports unlimited (150,000 years!) continuous data logging

8

FRAM | Industry-Leading Speeds

• 160x faster write speed than Flash technology

• SRAM-like performance • No pre-erase required for writes • No additional power is needed for

FRAM writes – CPU not held – Interrupt enabled during writes

2 MBps

12 kBps

0

500

1000

1500

2000

2500

FRAM Flash

Write Speed

9

FRAM | Lowest Energy Memory Writes

FRAM: More than 160x faster

FRA

M: 3

x le

ss c

urre

nt

Time

Cur

rent

700µA

2200µA

FRAM Write

10 ms

Flash Write

>400x lower energy than Flash

1 sec

2200µA

10

FRAM | Proven, Reliable

• Endurance – Proven data retention

to 10 years @ 85°C – > 1,000,000,000,000,000 write

cycles • Less vulnerable to attacks

– Fast access/write times • Radiation Resistance

– Terrestrial Soft Error Rate (SER) is below detection limits

– Error Correction Code (ECC) enables fail safe memory applications

• Immune to Magnetic Fields – FRAM does not contain iron!

www.ti.com/fram For more info on

TI’s FRAM technology

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http://www.ti.com/fram


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Introduction to MSP430FR59xx

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MSP430™ |FR58xx/59xx

Performance • Up to 16MHz, 16-bit RISC CPU Power (Typical target values at 25ºC) • Supply Voltage Range 1.8V to 3.6V • Active Mode: 103 uA/MHz typical execution • Standby Mode (LPM3): 0.4 uA • RTC mode (LPM3.5): 500 nA • Shutdown Mode (LPM4.5): 200 nA • Wake up from Standby Mode in <7μs

Package • 40/48-Pin QFN, 38-Pin TSSOP • Temp Range -40ºC to 85ºC

Benefits • FRAM: Ultra-low power, universal memory

• Nearly infinite (1015) write cycles • >100x faster writes than Flash (2 MB/s) • 250x less power in writes • Flexible as data or program memory

• High performance Analog • ADC12: 16ch 200 ksps and 75uA consumption • First Differential A/D (8 input) in MSP430 • Versatile analog comparator 15 external channels,

voltage hysteresis, reference generator • Unique Security offering

• Inherent FRAM security • Flexible AES256 hardware encryption • Available Code Segment Security for IP Locking • True Random Number Generator (NIST, AIS 31)

Serial Interfaces

Converters

Peripherals

Memory

Debug

Timers

Power & Clocking

Connectivity

• 32x32 Multiplier • DMA (3 Ch) • CRC16 • True Random Number Gen

• Comp_B / Vref • 12 bit ADC (up to 12 ch)

32/48/64 KB FRAM (with segment protections

For code/data)

Real Time JTAG ,

Embedded emulation Bootstrap Loader

• 3 Universal Serial Comm. Interfaces • 2 UART + IrDA or SPI • 1 I2C or SPI • AES256 Encryption (FR59xx)

• Up to 2 1x16 + 1 1x8 I/O Ports w/ Interrupt & wake up • Capacitive Touch Enabled

• Power on Reset • Brownout Reset • Low Power Vreg (1.5V) • HFXT, LFXT • VLO • DCO (±2%) • Real Time Clock Calendar

• Watch Dog Timer • 16 Bit TA1 w/ 3 CC regs • 16 bit TA2 w/ 2 CC regs • 16 bit TA3 w/ 2 CC regs • 16 Bit TB0 w/ 7 CC Shadow regs • 16 Bit TA0 w/ 3 CC regs

MSP430FR58/59xx Ultra Low Power 16 – bit MCU 16MHz

• Comp_D / Vref • 12 bit ADC (up to 16 ch) • Differential inputs • Window comparators

• Up to 40 GPIO • w/ Interrupt & wake up • Cap touch IO

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MSP430FR5969 Block Diagram

Benefits • FRAM: Universal, non-volatile memory • Fast write speeds - 160x faster than Flash/EEPROM and >400x lower energy on memory write operations • Better integrated Analog – 12 bit ADC and comparator with window • Cost efficient system implementation and fast design cycle with dynamic allocation of memory • Efficient peripheral use with all IO interruptible and 5 available timers • Extremely reliable and robust power management for critical and secure operations • FRAM standard with 5 GP Timers and fully interruptible IO pins

F2xx MSP430F5xx FR5739 FR58xx/59xx

Performance Up to 16 MHz Flash Up to 25 MHz Upto 24MHz (FRAM access @ 8MHz)

Up to 16MHz, (FRAM access @ 8MHz)

Active Mode >250 µA/MHz ~180 µA/MHz 100µA/MHz avg.@ 8MHz

103 µA/MHz typical active power

RTC Mode 0.8 µA 2.6 µA (LPM3.5): ~1.5 µA (LPM3.5): 0.5 µA

Standby Mode 0.8 µA 1.9 µA (LPM3): 6.3 µA (LPM3): 0.4 µA

(LPM4.5): (LPM4.5): ~0.3 µA (LPM4.5): 0.02 µA

Off Mode 0.3 µA 1.6 µA LPM4: 5.9 µA (LPM4): 0.3 µA

Wake-up from Standby

1 µs 25 µs 100 µs Wake up from Standby Mode in <10μs

Flex Unified Mem

16/8/4 KB FRAM 32 / 64 KB FRAM

Temp Range -40ºC to 105ºC - 40 ºC to 85 ºC -40ºC to 85ºC -40ºC to 85ºC

Package 24/40-Pin QFN, 28, 38-Pin TSSOP

40/48-Pin QFN, 38-Pin TSSOP

MSP430™ | FRAM Series Comparison

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MSP430FR59xx/FR58xx Architecture & Core Peripherals

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MSP430xv2 Orthogonal CPU

• No changes from the F5xx CPU!

• C-compiler friendly

• Memory address access up to 1MB

• CPU registers 20-bit wide

• Address-word instructions

• Direct 20-bit CPU register access

• Atomic (memory-to-memory) instructions

• Instruction compatible w/previous CPU

• Cycle count optimization for certain instructions

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Operating Modes

• Active Mode – 103 µA/MHz! – CPU active – Fast Peripherals Enabled – 32 kHz Peripherals Enabled - RTC

• LPM0 – 80 µA – CPU disabled, Fast Peripherals Enabled – Fast Wake up – 32 kHz Peripherals Enabled – RTC

• LPM3 – 0.6 µA – CPU disabled, Fast Peripherals Disabled – Slow wake up – 32 kHz Peripherals Enabled – RTC, Watchdog & SVS protection

• LPM4 – 0.3 µA – All clocks disabled – Wake on interrupt

• LPM3.5 – 0.45 µA – Regulator & all clocks disabled – Complete FRAM retention – BOR on nRST/NMI or Port I/O or RTC

• LPM4.5 – 0.02 µA

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LPM & Wakeup Time Comparison

Parameter F2xx F5xx FR57xx FR59xx

LPM0-LPM4 Yes Yes Yes Yes

LPMx.5 No Yes Yes Yes

tWAKEUP-LPM0 1µs 6µs 1µs 1µs

tWAKEUP-LPM1,2 1µs 6µs 11µs 6µs

tWAKEUP-LPM3,4 1µs 6µs/ 150µs 100µs 7µs

tWAKEUP-LPMX.5 N/A 2000µs 700µs 250µs

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PMM | Power Management & Core Voltage • What is VCORE?

– Integrated LDO provides a regulated voltage – VCORE powers digital core (CPU, memory, digital modules)

• Is this any different from the F5xx/FR57xx family? – FR59xx has only one core level [1.2V] – All MCLK frequencies possible to operate down to 1.8V! – FR59xx does NOT require an external VCORE capacitor – Simplified power management!

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DVCC VCORE REGULATOR

1.8 – 3.6V 1.2V

PMM | Power Management Module

The LDO is “predictive” and “capless” – LDO load is estimated dynamically based on

system needs – Buffered by internal capacitors

Things to remember: • Predictive LDO for VCORE reduces overhead for LDO bias Lower power consumption • No external cap for VCORE needed Lower area on board, Cost

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SVS | Supply Voltage Supervision

• Supply voltage supervision highly simplified compared to F5xx family

• Individually enabled for high (supply)/ low (core) sides

• Fixed threshold allowing safer device power-on

– Device reset tracks with SVSH

• SVSH – Enabled in all modes, cannot be disabled – Disabled in LPM4.5

• SVSL – Enabled in active, LPM0, cannot be disabled – Can be disabled in LPM1,2 (default enabled) – Disabled in LPM3,4,x.5

PMM Action at Device Power-up

CS | Clock System

• Five independent clock sources – Low Frequency

• LFXT 32768 Hz crystal – Special low power option

• VLO 9 kHz • LFMODCLK MODCLK/128

– High Frequency • HFXT 4 – 24 MHz crystal • DCO Specific CAL range • MODCLK Internal 5MHz

• Default DCO = 1MHz • ACLK = Only LF sources • MODOSC provided to ADC12 • Failsafe

– LFXT: LFMODCLK (~39kHz) – HFXT: MODCLK (5MHz)

25

26

CS | Digitally Controlled Oscillator

• 14 fixed frequency settings

DCO Frequency Selection

DCOFSEL Nominal DCO Frequency, MHz

DCORSEL = 0 DCORSEL = 1 000 1 1 001 2.67 5.33 010 3.33 6.67 011 4 8 100 5.33 16 101 6.67 21 110 8 24 111 Reserved Reserved

FRAM | FRAM Controller

Functions of FRCTL: • FRAM reads and writes like standard

RAM (but) • Read/Write frequency < 8MHz • For MCLK > 8MHz, wait states

needs to be manually added FRCTL0 = FRCTLPW | NWAITS_x;

• Seamless and transparent integration of cache

• Error checking and correction (ECC) built into FRAM read/write cycle

27

Security | Embedded Encryption

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MSP430 Device AES128 AES256 Random Seed Software

2xx, 5xx Devices

CC430

MSP430FR59x MSP430FR58x

• Hardware encryption faster & lower power • Encryption valuable in wireless applications

• Zigbee, 802.15.4, Bluetooth • Wireless key FOB • Building security/automation

• Random seed available for multiple applications • Pseudo-random number generation • Unique network ID • Network collision avoidance

Security | Random Number Generation

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• True random number seed in FR58/59xx – Written in the boot data on the device

• Documented in the User Guide – 23-bit number initially defined by Microsoft

CryptGenRandom from • http://en.wikipedia.org/wiki/CryptGenRandom • http://msdn.microsoft.com/en-

us/library/aa379942%28v=vs.85%29.aspx

• Random number generation software available (SLAA338) – Firmware generates a NIST compliant random

number – Uses difference between asynchronous VLO

and DCO clocks

http://en.wikipedia.org/wiki/CryptGenRandom

http://msdn.microsoft.com/en-us/library/aa379942(v=vs.85).aspx

http://msdn.microsoft.com/en-us/library/aa379942(v=vs.85).aspx

http://focus.ti.com/mcu/docs/litabsmultiplefilelist.tsp?sectionId=96&tabId=1502&literatureNumber=slaa338&docCategoryId=1&familyId=342

Security | Securing FR59xx/FR58xx Device

The following options are available: • JTAG

– Lock JTAG access with password protection – Disable JTAG by programming the fuse

• BSL – By default BSL is protected with password – BSL can be disabled by writing to the signature location – Note: BSL is in ROM and cannot be erased

• IP Encapsulation

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JTAG | Securing It

• There are two options for securing JTAG – Lock without Password (Electronic Fuse) – Lock with Password (can get back in on JTAG with correct password) NEW

• JTAG signatures are located at addresses 0xFF80 (Signature 1) and 0xFF82 (Signature 2)

• Signature content allows selection between the two options

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JTAG | Lock w/o Password

• Electronic Fuse is similar to 5xx/6xx family • To secure the device without password access:

– Write 0x5555 to BOTH JTAG signatures at addresses 0xFF80 and 0xFF82.

• To regain access to the device, BSL can be used

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JTAG Signature 1 JTAG Signature 2 @0xFF80: 0x5555 @0xFF82: 0x5555

JTAG | Lock w/o Password

• JTAG access on a locked device can be regained using the BSL • To undo JTAG Lock, use the BSL to overwrite the JTAG signatures

with anything but 0x5555 or 0xAAAA. – For example, write 0’s to these locations

• Note: – BSL password must be known (else device will be mass-erased) – access to BSL inputs (TST, RST lines) is needed

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BSL password Enter BSL BSL write

JTAG Signature 1 JTAG Signature 2 @0xFF80: 0x0000 @0xFF82: 0x0000

JTAG | Lock with Password

• To enable the JTAG Lock WITH password: – Write 0xAAAA to JTAG signature 1 – Write JTAG signature 2 with the user-defined length in words (except

0x5555) of the desired password – The starting point of the password is at location 0xFF88 – (Note that if you have interrupt vectors in the same place as password, you

need to use those interrupt vector values for that part of the password)

• The Password takes effect on the next BOR

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• Example: If there is a password length of 4 then the password is at 0xFF88, 0xFF8A, 0xFF8C, and 0xFF8E.

• The tool-chain can supply the correct password to access the part via JTAG – Can do a field firmware update with JTAG instead of BSL.

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JTAG Signature 1 JTAG Signature 2 @0xFF80: 0xAAAA @0xFF82: 0x0004

@FF88: @FF8A: @FF8C: @FF8E: 0x0123 0x4567 0x89AB 0xCDEF


• Tool-chain supplies password using special JTAG command • Password is compared to the password in memory • If they match, part allows access via JTAG

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JTAG Mailbox JMBIN0: 0xA55A JMBIN1: 0x1E1E

@0xFF88 @0xFF8A @0xFF8C @0xFF8E PW in FRAM 0x0123 0x4567 0x89AB 0xCDEF PW RX’d 0x0123 0x4567 0x89AB 0xCDEF

Compare Password

MATCH!

Full JTAG Access

Electronic Fuse JTAG Lock with Password

BSL access is required to get back in to part

Access possible through tool chain w/ correct password

Advantage: BSL password is longer and hence more secure

Disadvantage: password is not as long as BSL password

Disadvantage: Wiring for BSL lines, mechanism for entry sequence is required for a field firmware upgrade

Advantage: Firmware updates can be done via JTAG (no BSL interface

requred)

JTAG | Securing Comparison

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IPE | IP Encapsulation

• Target – Protection against unauthorized readout of protected memory – Protection against unauthorized write to protected memory

• When protected: – JTAG, BSL, DMA access to readout content is not possible – Instruction fetch is possible (function call to protected memory) – Data fetch is possible only from within the protected memory – Unauthorized access returns “JMP $” and triggers an interrupt, or can issue

a PUC

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IPE | Implementation

• Two IPE Signatures in FRAM – Signature 1: @0xFF88 –

0xAAAA – Signature 2: @0xFF8A – IPE

structure pointer

• User initializes an IPE structure in their code with their settings and sets Signature 2 to point to it

• Place the IPE init structure within the IPE segment to prevent modification from outside

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IPE Segment

IPE_Init_Structure

MPU IPE Register Settings

IP Encapsulated Code + Data

IPE | Implementation (cont’d)

40

Copy Init_Struct

to MPU Regs

0xAAAA @0xFF88

?

Save Signature 2

as struct pointer

Saved IPE struct pointer?

Use saved struct

pointer

Boot Code

No

Yes

Yes

No

AES256 | 256-bit Encryption or Decryption

Benefits • Hardware acceleration for

AES (Advanced Encryption Standard – FIPS PUB 197)

• Accelerates AES en- and decryption by one to two orders of magnitude (compared to software)

• Lower power (compared to software) • Off-loads CPU Performance • 128-bit of data are en- or decrypted

with a 128-bit key within 167 MCLK cycles, 256-bit encryption in 234 cycles

Features • Supports 128, 192, and 256-bit key

lengths • On-the-fly key expansion • Off-line key generation for

decryption • Shadow registers for initial key • 128-bit truly random seed to

generate the random key

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Applications include Securing of communication channels like RF links, UART communications, etc.

Digital I/O | General Purpose Pins

• 5 Digital I/P Ports P1-P4 and PJ • 4 Ports are interruptible (P1-P4) • PJ used as GPIO when debugger is not in use • Certain pins are heavily multiplexed

– PxSEL0, PxSEL1 registers are used to select peripheral functionality – Refer to datasheet schematics – When both bits need to be set/cleared at once use PxSELC register

42

Digital I/O | Cap Sense

Benefits • Low cost • No external components • Simple solution Performance • Sense caps can be in the range of

2pF to 50pF • Low power (examples w/ <10uA,

1uA)

Features • The external cap and the internal

resistor controlled by the inverted Schmitt-Trigger input form an oscillator with the oscillation frequency being a function of the ext. cap.

• Together with Timer_A or Timer_B the oscillation frequency can be measured

• The control registers allow scanning to adjacent pins easily

• Dedicated cap sense I/o registers

43

eUSCI_A | UART Mode

• Architecture is maintained mostly compatible with USCI_A • Register mapping from USCI to eUSCI available in migration document • New features include

– UCTXCPTIE interrupt similar to TXEPT flag in USART – Enhanced baud rate calculator: Increased flexibility with modulation pattern

settings – UCSTTIE interrupt for start bit detection – Increased flexibility with deglitch filter

44

45

eUSCI_A & eUSCI_B | SPI Mode

• Architecture is maintained mostly compatible with USCI_A • Register mapping from USCI to eUSCI available in migration document • Supports higher baud rates

– Up to 9MHz @ 3.0V – Up to 6MHz @ 2.0V

• Modified 4-pin SPI mode – Can now be used as a ‘true’ chip select in master mode

eUSCI_B | I2C Mode

Many new features have been added: • Multiple slave addresses • Clock low timeout for SMBus compatibility • Byte counter • Automatic stop assertion • Preload for master/slave transmitter • Address bit masking • Selectable deglitch timing • ACK/NACK selectable in software

46

47

eUSCI_B | I2C

Multiple Slave Addresses • Support four slaves in hardware • 4 unique slave address registers:

UCBxI2COAx • Each slave address has a

corresponding UCOAEN • Independent interrupt vector pairs for

TX and RX flags • Shared status flags • Dedicated DMA channels • Example application: EEPROM +

sensor

UCB0I2COA0 = 0x48; // EEPROM UCB0I2COA1 = 0x40; // ADC #pragma vector = USCI_B0_VECTOR __interrupt void USCI_B0_ISR(void) { switch() { case 0: break; case 2: break; ... case 20: // UTXIFG0 EEPROM TX case 22: // URXIFG0 EEPROM RX case 24: // UTXIFG1 ADC TX case 26: // URXIFG1 RX ... default: break; } }

48

eUSCI_B | I2C Clock Low Timeout • SCL being held low for a time>

timeout interval causes flag to be set • Interval timer based on MODOSC • 3 selectable intervals ~25, 30, 35ms • Interrupt: UCCLTOIE • Available for both master and slave • User is required to determine post-

timeout activity such as reset • Allows for SMBus compatibility

without using a timer resource • Can be leveraged for hot-plug issues

UCB0CTLW1 |= UCCLTO_2; // 25ms UCB0IE |= UCCLTOIE; #pragma vector = USCI_B0_VECTOR __interrupt void USCI_B0_ISR(void) { switch() { case 0: break; case 2: break; ... case 28: // clock low timeout UCB0CTL0 |= UCSWRST; UCB0CTL0 &= ~UCSWRST; break; } }

49

eUSCI_B | I2C

Byte Counter & Auto Stop • RX and TX bytes are counted in

hardware • The counter increments for every

byte that is on the bus • Available in master (active) and

slave (passive) mode • In master mode when used with auto

stop – eliminates the need for software counters.

• Master sends Stop condition when BCNT threshold is hit

// Master TX Mode UCB0CTLW1 |= UCASTP_2; // UCB0TBCNT |= 0x05; // 5 bytes #pragma vector = USCI_B0_VECTOR __interrupt void USCI_B0_ISR(void) { switch() { case 0: break; ... case 20: // UTXIFG0 UCB0TXBUF = *Data_ptr; Data_ptr++; break; } }

50

eUSCI_B | I2C

Early Transmit Interrupt • USCI module clock stretches in TX

mode if TX ISR is not serviced immediately

• eUSCI offers a preload feature • TXBUF is loaded on detection of

start edge prior to address compare • Software must take care of the

unloading in case of an address mismatch.

// Master TX Mode UCB0CTLW1 |= UCETXINT; // #pragma vector = USCI_B0_VECTOR __interrupt void USCI_B0_ISR(void) { switch() { case 0: break; ... case 20: // UTXIFG0 UCB0TXBUF = *Data_ptr; Data_ptr++; break; } }

51

eUSCI_B | I2C Migration Considerations

• HW clear of interrupt flags no longer available USCI_B has 4 sets of flags with associated clearing events Customers who have previously used the USCI will assume this is still

available ( Migration document) TXIFG cleared by NACK In master mode NACKIFG can be used to clear last TXIFG In slave mode STPIFG can be used. TXIFG could likely be already serviced and

user needs to ensure data pointers are re-adjusted STPIFG STTIFG Needs to be included by user in S/W

NACKIFG cleared by STP master mode only NACKIE needs to be enabled if clearing is needed (no STPIFG in master mode)

Refer to Application Report Migrating from USCI to eUSCI - SLAA522

http://www.ti.com/lit/pdf/slaa522






RTC_B | Real-Time Clock

• Calendar mode only • Low frequency crystal (LFXT) 32768Hz required • Advanced interrupt capability – alarms, OF fault,

RTCREADY and RTCEV • Selectable BCD format • Calibration • Multiple Alarms • Operation in LPM3.5

52

COMP_E | Comparator Module

• Interrupt driven for low power • Uses the REF module like ADC12_B • Up to 15 external input channels • Software selectable RC filter • Selectable reference voltage generator • Voltage Hysteresis generator

53

ADC12_B | Overview

• Up to 200ksps • Window comparator for all channel results,

shared high and low threshold between all channels

• Differential or single-ended inputs – user selectable

• Extend to 32-input channels – separate internal channels for AVcc

and TempSensor and 4 for future use – Add 16 ADC12MCTL registers – Add 16 ADC12MEMx registers

• Ultra-low current consumption – Expected Single ended typical 63uA

@ 1.8V, 200ksps – Expected Differential typical 95uA @

1.8V, 200ksps

54

ADC12_B | Features = New Feature

= Enhanced Feature

ADC12_B | New – Window Comparator

• Window Comparator – Allows you to configure input

threshold levels – The ADC conversion results

are automatically compared against the thresholds

– Hi, Lo, and In interrupts indicate which range the result falls in

– Same thresholds shared among all channels

– Useful for low power because device can stay in LPM until result falls in window

56

Set ADC12INIFG

Set ADC12HIIFG

Set ADC12LOIFG

ADC12HI threshold

ADC12LO threshold

ADC12_B | Window Comparator Example

57

ADC12HI threshold

ADC12LO threshold

Set ADC12INIFG


58

ADC12HI threshold

ADC12LO threshold

Set ADC12HIIFG


59

ADC12HI threshold

ADC12LO threshold

Set ADC12INIFG


60

ADC12HI threshold

ADC12LO threshold

Set ADC12LOIFG


61

ADC12HI threshold

ADC12LO threshold

Set ADC12LOIFG


62

ADC12HI threshold

ADC12LO threshold

Set ADC12HIIFG

Set ADC12INIFG

Set ADC12LOIFG

ADC12_B | New – Differential Mode

• Combine 2 input channels to create a differential input channel • In this mode the ADC will measure the difference between two

channels and store this value in the ADC12MEMx register

63

Vcc

Gnd

A1

A2 ∆

A1 voltage

A2 voltage Difference ADC12MEMx

Register

ADC12_B | New – Int. Channel Mapping

• A26-31 can map to either an External Input or Internal ADC input

• Internal inputs include the temperature sensor and battery monitor

• See the device datasheet to see what internal inputs are available on what channels – varies by device

64

ADC12_B | Enhancements

ADC12_A ADC12_B Supports 12 single-ended external input channels

Supports 16 single-ended external input channels that can be combined to form 8 differential inputs

16 configurable conversion memory buffers and control registers with dedicated interrupts

32 configurable conversion memory buffers and control registers with dedicated interrupts

Min Avcc 2.2V Min Avcc 1.8V

Current into Avcc ~150uA (analog portion of ADC)

Current into Avcc ~75uA (analog portion of ADC)

Clock pre-divider options of /1, /4 Clock pre-divider options of /1, /4, /32, /64

65

ADC12_B | Migrating from ADC12_A

• Other Changes – More trigger sources

(hook-up from multiple timers) – tconvert = 14ADC12CLKs (in 12-bit mode) – 3 extra interrupts for window comparator

• Migration guide: – Migrating from F5xx/6xx to FR5xx/6xx: www.ti.com/lit/pdf/slaa555 – includes a section on migrating from ADC12_A to ADC12_B

66



67

Getting Started

68

Getting Started | Lab Requirements

You will need: • MSP-TS430RGZ48C • MSP430FR5969 device • MSP-FET430UIF programmer • CCSv5.5 or greater • MSP430Ware v1.60 and above • 1 jumper wire • Multimeter • Import all labs into a CCS

workspace

69

Getting Started | Obtaining Lab Software

• Software for this lab can be obtained from the MSP430 FR59xxTraining Workshop wiki

• The link is: http://processors.wiki.ti.com/index.php?title=MSP430_FR59xx_Training_Workshop

• Download the zip file – Contains 4 folders for 4 labs

70

http://processors.wiki.ti.com/index.php?title=MSP430_FR59xx_Training_Workshop

http://processors.wiki.ti.com/index.php?title=MSP430_FR59xx_Training_Workshop

Lab 1A | Goals 1) Unboxing the MSP430FR5969 Target Board (MSP-TS430RGZ48C) 2) Setting up a CCS Project 3) Measure active power for different system frequencies 4) Understand the impact of cache on active power

71

Lab 1A | Unboxing and Plugging-In

• Plug the MSP-FET430UIF to the PC • Connect the 14-pin JTAG header to the target

board

72

73

Lab 1A | Setting Up CCS Workspace

• Open Code Composer Studio (v5.5 or newer) • Enter a desired location for Eclipse workspace. In this case,

c:\LabWorkspace is used as the workspace location

74

Lab 1A | Importing Existing Projects

• Import 4 projects using Project Import Existing CCS Project • Browse to the extracted lab project folder • Select All projects to be imported • Click Finish

75

Lab 1A | Using while(1) to Measure Power

• Lab_1A.c is setup to initialize the board • Ensure that while(1); loop in main() is included

Lab 1A | Building a Project • Right click on the project • Click on Build Project

76

Lab 1A | Download and Execute a Project

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• Once your project successfully builds • Click on this icon to automatically download and start

debugging your project

• Click Resume to start running the code • Then click Terminate from the debug session

Terminate Resume

Lab 1A | And the Power Number Is…

• Measure current across JP1 jumper

• MCLK = DCO = 8MHz • Meter reads < 510µA or

~64µA/MHz • Observations:

– Single word opcode (JMP$) Code execution is completely within the cache (SRAM)

– Hence the low active power!

78

Connect meter across Vcc

79

Lab 1A | A More Realistic Scenario

• Function activeModeTest() = combination of RAM, FRAM access + different addressing modes

• Closer to a typical application use-case • Use this function to measure ‘real world’ active power • Comment out the while(1); loop • Include activeModeTest() function call • Rebuild Project • Download & execute the code, terminate debug session Note: Remember to reconnect the jumper to program the target or

leave the meter ON


80

MSP430™ DriverLib Quick Intro + Tips & Tricks

81

DriverLib | What is it?

• MSP430™ Driver Library • Supports F5xx/6xx, FR57xx, and FR58/59xx families, and growing • Peripheral layer is abstracted • Uses API function calls for code legibility vs direct register access • Makes code more modular and portable

82

DriverLib | Coding Style Example

• Here is some code to set P1.0 as an input pin with a pull-up resistor • Instead of using direct register access, like this: P1SEL0 &= ~BIT0;

P1SEL1 &= ~BIT0;

P1DIR &= ~BIT0;

P1REN |= BIT0;

P1OUT |= BIT0;

• Use an API function call, like this: GPIO_setAsInputPinWithPullupResistor(

GPIO_PORT_P1,

GPIO_PIN0);

• Which is easier to read, the first or the second version of this code? 83

Lab 1B | Goals 1. Create a new Driver Library project 2. Finding the Documentation 3. Using Driver Library function calls to blink an LED on P1.0

84

Lab 1B | Starting a New DriverLib Project

• Open TI Resource Explorer [View – TI Resource Explorer] • Navigate to MSP430Ware > Libraries > Driver Library >

MSP430FR5xx_6xx > emptyProject and click on Step 1: Import the example project into CCS

85

• Rename the emptyProject to your target project • Rename the project (right-click > Rename)

• Rename emptyProject to Lab_1B_DriverLib


86


• All of the driverlib library files are already included in a “driverlib” folder in the project. – In addition, main.c already has #include “driverlib.h”, needed for all driverlib

projects. – All the correct include paths are already set up

• Simply change Project Properties to be the correct device variant. • Now the project should be ready to start coding with driverlib!

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Lab 1B | How do I know what APIs I can use and how to use them? • All DriverLib API is documented

in an HTML format. (MSP430Ware > Libraries > Driver Library > MSP430FR5xx_6xx > API Programmer’s Guide)

• Click “File List” and then the file for the particular module, and it will pop up an interactive list of all the functions for using that module.

• Click on a function, and it will display a description of what the function does, and what the parameters are.

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Lab 1B | Blink the LED

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void main(void) { //Stop WDT WDT_A_hold(WDT_A_BASE); //P1.0 output GPIO_setAsOutputPin( GPIO_PORT_P1, GPIO_PIN0 ); //Set P1.0 pins Low GPIO_setOutputLowOnPin( GPIO_PORT_P1, GPIO_PIN0 ); /* * Disable the GPIO power-on default high-impedance mode to activate * previously configured port settings */ PMM_unlockLPM5(PMM_BASE); while(1) { // Toggle P1.0 LED GPIO_toggleOutputOnPin( GPIO_PORT_P1, GPIO_PIN0); // Arbitrary delay to see LED blink __delay_cycles(200000); } }

• Copy and paste the following pre-created code into main.c

• The code is written using only Driver Library function calls to blink an LED on P1.0

DriverLib | Tips & Tricks

Tip #1: For easy reference while coding, have the documentation in a separate pane from the code.

• There are two ways to do this: 1. Right click on the tab with TI Resource Explorer open. Select Move >

Editor and drag it off to sit in its own area next to the code, instead of a tab in the same pane as the code.

2. In TI Resource Explorer with the API Guide open, Right-click on “Main Page” and select Open in New Window. This will open the HTML documentation in a browser window instead of inside CCS.

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DriverLib | More Tips & Tricks

Tip #2: Auto-complete is your friend! • In CCS, hitting Ctrl+Spacebar on a partially-written function name will

bring up the Auto-complete menu.

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DriverLib | More Tips & Tricks

• This also works for the parameters to function calls, and header file include statements!

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• In addition, CCS pops up a helper showing what parameters are required for a function call.

DriverLib | Reasons to use!

• It makes portable code – function calls look the same for different devices

• Create quick demos • Driverlib can be used in combination with normal direct register-access

C code • Driverlib is recommended for correct usage and errata workaround on

some of the more complex F5xx/6xx modules and FR58/59xx modules – UCS / CS – PMM – FLASH – DMA

• If you start using DriverLib, we’d love to hear any feedback that you have! We are constantly trying to make it better

93


94

MSP430™ ADC12_B Hands-On Labs

95

Lab 2A | Goals

• Basic ADC12_B usage – Software controlled method • A sample is taken on A2 (P1.2) which is Pin-3 on the MSP-

TS430RGZ48C target socket board • The conversion result is then checked if it is above or below Avcc/2 in

software. If it is high, then the LED on P1.0 is lit, if low the LED is turned off.

• ADC settings: – Avcc/Avss configured as reference – ADC12OSC (5MHz MODOSC) as conversion clock – Successive conversions are triggered by software, using ADC12SC bit – Part wakes up from LPM0 after each conversion to process results

96

Lab 2A | Program flow

97

Take an ADC

Sample

Read and store result

Is sample > Avcc/2?

Set LED on

Set LED off

Start Conversion

Hardware

Software

Yes

No

Interrupt ISR

Return to main

Go to LPM

= Software = Hardware

Lab 2A | Procedure

1. Fill in the blanks in Lab_1_Part_1_ADC12_B.c, using the comments as a guide.

1. Remember Ctrl + Spacebar for auto-complete 2. Use the DriverLib documentation to help select the correct parameters

2. Once the code builds, test it using a jumper wire to connect P1.2 (Pin 3) to VCC and GND and see if the LED behavior is correct.

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Lab 2A | Filling in the blanks – ADC init

• Look up the ADC12_B_init function in the DriverLib documentation • This function sets up the basic overall ADC settings, like the trigger,

and the clock source • The last parameter is used for mapping any of the internal channels. If

no internal channels are needed to be mapped, put a 0.

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Lab 2A | Filling in the blanks – ADC init

• Look up the ADC12_B_init function in the DriverLib documentation • This function sets up the basic overall ADC settings, like the trigger,

and the clock source • The last parameter is used for mapping any of the internal channels. If

no internal channels are needed to be mapped, put a 0.

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Lab 2A | Filling in the blanks – Sampling Timer

• Next, find the function call to enable the ADC. Ensure to check the documentation for adc12_b.c – this lists all the ADC function calls.

• Then set up the sampling timer. The number of sample/hold cycles is listed in the comments, and there should be constants defined in the DriverLib documentation that correspond to these.

101

Lab 2A | Filling in the blanks – Sampling Timer

• Next, find the function call to enable the ADC. Ensure to check the documentation for adc12_b.c – this lists all the ADC function calls.

• Then set up the sampling timer. The number of sample/hold cycles is listed in the comments, and there should be constants defined in the DriverLib documentation that correspond to these.

102

Lab 2A | Filling in the blanks – Configure Memory Buffer

• Configure the Memory Buffer for the conversion results – similar to setting up ADC12MCTL0 in direct register access. This sets up the ADC channel and the reference voltage.

• This lab uses Avcc and Avss for our reference (saves power by not enabling the internal reference, current numbers from the ADC and the CPU in these labs)

• Remember to specify that this is not the end of a sequence –this is a single sample, single conversion

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Lab 2A | Filling in the blanks – Configure Memory Buffer

• Configure the Memory Buffer for the conversion results – similar to setting up ADC12MCTL0 in direct register access. This sets up the ADC channel and the reference voltage.

• This lab uses Avcc and Avss for our reference (saves power by not enabling the internal reference, current numbers from the ADC and the CPU in these labs)

• Remember to specify that this is not the end of a sequence –this is a single sample, single conversion

104

Lab 2A | Filling in the blanks – Set up Interrupts

• Clear and enable the interrupt that is used – in this case, interrupt fires when Memory Buffer 0 is finished

• Note the structure of the DriverLib functions. The ADC12_B module has 3 Interrupt Enable Registers. See the DriverLib documentation to see how each function handles this.

• Specify which interrupt register to clear in the clear interrupt function • Enable interrupt function has the ability to set bits in all three registers

in a single function call

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Lab 2A | Filling in the blanks – Set up Interrupts

• Clear and enable the interrupt that is used – in this case, interrupt fires when Memory Buffer 0 is finished

• Note the structure of the DriverLib functions. The ADC12_B module has 3 Interrupt Enable Registers. See the DriverLib documentation to see how each function handles this.

• Specify which interrupt register to clear in the clear interrupt function • Enable interrupt function has the ability to set bits in all three registers

in a single function call

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Lab 2A | Filling in the blanks – Start Conversion and Mode

• Use the function to start the conversion • Specify the memory buffer that contains the information for the first

channel (and in this case only one) to be sampled • Remember, even though the ADC is sampling from A2, the ADC12 is

setup to insert its conversion results in Memory Buffer 0 • Specify that it is using Single Channel, Single Conversion mode • Note the structure of the main while(1) loop: it starts the conversion

cycle every time, then it waits for the interrupt to wake up the MSP430 when the result is ready, and make a decision to turn the LED on or off.

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Lab 2A | Filling in the blanks – Start Conversion and Mode

• Use the function to start the conversion • Specify the memory buffer that contains the information for the first

channel (and in this case only one) to be sampled • Remember, even though the ADC is sampling from A2, the ADC12 is

setup to insert its conversion results in Memory Buffer 0 • Specify that it is using Single Channel, Single Conversion mode • Note the structure of the main while(1) loop: it starts the conversion

cycle every time, then it waits for the interrupt to wake up the MSP430 when the result is ready, and make a decision to turn the LED on or off.

108

Lab 2A | Filling in the blanks – Decision Logic

• Fill in the main loop decision logic that happens when the application wakes up with a result

• P1.0 is the LED. Set the LED pin high when the data is high and set it low when the data is low.

• See DriverLib documentation for the correct function names for setting an output pin high and low.

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Lab 2A | Filling in the blanks – Decision Logic

• Fill in the main loop decision logic that happens when the application wakes up with a result

• P1.0 is the LED. Set the LED pin high when the data is high and set it low when the data is low.

• See DriverLib documentation for the correct function names for setting an output pin high and low.

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Lab 2A | Filling in the blanks – Data Handling in ISR

• Use DriverLib documentation to find the function call that is used to retrieve the ADC result.

• The ISR fires after every conversion. As observed, the application wakes up from low power mode when it leave the ISR.

111

Lab 2A | Filling in the blanks – Data Handling in ISR

• Use DriverLib documentation to find the function call that is used to retrieve the ADC result.

• The ISR fires after every conversion. As observed, the application wakes up from low power mode when it leave the ISR.

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Lab 2A | Measure Current

1. Once the code is working, take a current measurement.

a) Connect the jumper wire to GND (so LED is off – LED consumes a lot of current and would mask the MSP430 current consumption)

b) Make sure to terminate the debug session (debugger would affect the reading)

c) Remove jumper JP1 and hook-up a multimeter between these pins to measure the current

113

Lab 2A | Results

• Current measurement should be around ~230uA • What contributes to this current?

1. The analog for the ADC module 2. Waking up after every single sample to process results (more time in active

mode, not a great active vs sleep duty cycle). CPU is running at 1MHZ.

• In part 2, the lab uses the ADC window comparator to greatly reduce

this second source of current draw by staying asleep until it crosses the thresholds

114

Lab 2B | Goals

• Part 2: Low Power ADC12_B usage • A sample is taken on A2 (P1.2) which is Pin-3 on the MSP430FR5969 • The window comparator is configured with a threshold to check whether

A2 is above or below Avcc/2 • Timer settings:

– VLO source (~9kHz) – Generate 100Hz signal with 50% duty cycle, internally triggers ADC

• ADC settings: – Avcc/Avss as the reference – ADC12OSC (5MHz MODOSC) as conversion clock – Low power ADC mode can be used b/c low sampling freq. – Successive conversions are triggered by the Timer A module, so device can

stay asleep – Window comparator Hi and Lo interrupts

115

Lab 2B | Goals Continued

• Window Comparator settings: (Compare against Avcc/2 as in Part 1) – Hi threshold: 0x7FF – Lo threshold: 0x7FF

• One window comparator interrupt enabled at a time – Once Hi interrupt fires, it is disabled and Lo is enabled – Once Lo interrupt fires, it is disabled and Hi is enabled

• The application wakes up from LPM when it crosses the threshold of Avcc/2 and changes the LED – Stay in LPM0 for a longer period of time

116

Lab 2B | Program Flow

117

Take an ADC

Sample

Timer starts conversion

Hi or Lo

fired?

Set LED on

Set LED off

Hardware

Software

Return to main

Go to LPM

= Software = Hardware

Enable Hi,

disable Lo

Enable Lo,

disable Hi

Return to main

Interrupt

Lab 2B | Procedure

1. Fill in the blanks in Wolverine_Lab1_ADC12_B_LowPower.c, using the comments as a guide.

a) Remember Ctrl+Spacebar for auto-complete b) Use the DriverLib documentation to help select the correct parameters

2. Once the code builds, test it using a jumper wire to connect P1.2 (Pin 3) to VCC and GND and see if the LED behavior is correct.

118

Lab 2B | Filling in the blanks – Setup

• Notice that the ADC12_B configuration is slightly changed from Part 1 • Instead of using software to trigger successive conversions, the ADC is

triggered from TA0.1. Find the correct Sample Hold Source # by looking at the datasheet to find which one corresponds to TA0.1, and use DriverLib docs to find the correct parameter to put in.

• The timer setup samples slower than 50ksps, hence the ADC can be configured in power conservation mode. See DriverLib doc to find the correct function name.

119

Lab 2B | Filling in the blanks – Setup

• Notice that the ADC12_B configuration is slightly changed from Part 1 • Instead of using software to trigger successive conversions, the ADC is

triggered from TA0.1. Find the correct Sample Hold Source # by looking at the datasheet to find which one corresponds to TA0.1, and use DriverLib docs to find the correct parameter to put in.

• The timer setup samples slower than 50ksps, hence the ADC can be configured in power conservation mode. See DriverLib doc to find the correct function name.

120

Lab 2B | Filling in the blanks – Configure Memory Buffer

• Notice that the ADC12_B configuration is slightly changed from Part 1 • Enable the use of window comparator • Set-up the window comparator thresholds

121

Lab 2B | Filling in the blanks – Configure Memory Buffer

• Notice that the ADC12_B configuration is slightly changed from Part 1 • Enable the use of window comparator • Set-up the window comparator thresholds

122

Lab 2B | Filling in the blanks – Set up Interrupts

• Use the Window Comparator interrupts for Hi and Lo instead of the Memory Buffer 0 interrupt

• At the beginning of the application, the input signal level is unknown, so both the Hi and Lo is enabled for the first sample

• Later in the application, only one interrupt is enabled at a time, so that it wakes up when the signal first crosses the threshold

123

Lab 2B | Filling in the blanks – Set up Interrupts

• Use the Window Comparator interrupts for Hi and Lo instead of the Memory Buffer 0 interrupt

• At the beginning of the application, the input signal level is unknown, so both the Hi and Lo is enabled for the first sample

• Later in the application, only one interrupt is enabled at a time, so that it wakes up when the signal first crosses the threshold

124

Lab 2B | Filling in the blanks – Starting conversions

• Kick off the ADC and get it running – Start the Timer to trigger successive conversions – Start the ADC

• Note that the timer is starting the successive conversions with no CPU intervention, it is now using repeated single channel mode for the ADC.

125

Lab 2B | Filling in the blanks – Starting conversions

• Kick off the ADC and get it running – Start the Timer to trigger successive conversions – Start the ADC

• Note that the timer is starting the successive conversions with no CPU intervention, it is now using repeated single channel mode for the ADC.

126

Lab 2B | Filling in the blanks – Main loop

• In the main loop: – Set the LED based on whether Hi or Lo fired – Enable/Disable the correct interrupts to fire on next threshold crossing

• If Hi fired: – Set the LED high – Disable Hi interrupt (Don’t wake up at each sample) – Enable Lo interrupt (Wakes up when it drops below threshold)

127

Lab 2B | Filling in the blanks – Main loop


• If Hi fired: – Set the LED high – Disable Hi interrupt (Don’t wake up at each sample) – Enable Lo interrupt (Wakes up when it drops below threshold)

128

Lab 2B | Filling in the blanks – Main loop (cont’d)


• If Lo fired: – Set the LED low – Disable Lo interrupt (Don’t wake up at each sample) – Enable Hi interrupt (Wakes up when it drops below threshold)

129

Lab 2B | Filling in the blanks – Main loop (cont’d)


• If Lo fired: – Set the LED low – Disable Lo interrupt (Don’t wake up at each sample) – Enable Hi interrupt (Wakes up when it drops below threshold)

130

Lab 2B | ISR handling

• In the ISR – Note whether a Hi or Lo interrupt has occurred for our main loop to

reference – There isn’t a blank here, just note the ISR handling

131

Lab 2B | Measure Current

1. Once the code is working, take a current measurement.

a) Connect the jumper wire to GND (so LED is off – LED consumes a lot of current and would mask the MSP430 current consumption)

b) Make sure to terminate the debug session (debugger would affect the reading)

c) Remove jumper JP1 and hook-up a multimeter between these pins to measure the current

132

Lab 2B | Results

• The current measurement should be around ~75uA (compare to Part 1 current of ~230uA)

• What contributes to this difference? – With this configuration almost everything is done automatically in hardware:

triggering the conversions, deciding if the result is high or low. – When the input isn’t crossing the threshold (just sitting in one range), the

part is asleep in LPM0 the whole time! But we will still be responsive when the threshold crossing occurs.

– This is why the current consumption is closer to being mostly just the ADC current consumption.

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134

MSP430™ Memory Protection Unit (MPU) Overview & Hands-On Lab

135

MPU | Memory Protection

• FRAM is easy to write to… • Both code and non-volatile data need protection • MPU’s main job is Access Management

– protect against accidental writes/fetches – Does not secure the device!

• Features include: – Configuration of main memory in three variable sized segments – Independent access rights for each segment – MPU registers are password protected

136

MPU | Using It

• The MPU can be configured: – By the linker file, at compile-time – In application initialization code – Can be reconfigured at any time in application

• To use the linker file: – See the bottom of the MSP430FR5969.cmd file

– Uncomment this area that defines segment boundaries – Automatically adjusts to your needed sizes for code and data sections

137

MPU | Calculating Segment Boundaries

138

• Size of segment determined by setting the MPUSB register (Segment Borders)

• For lower 64kB, 12 bits are used to set the boundary • Granularity = 64 * 1024 / (2^12 ) = 16 bytes

MPU | Creating Segments in 4 Easy Steps

139

MPUSBx[4:0] Page_start Address

0x400 0x4000 ….. ….

0x600 0x6000 … ….

0x800 0x8000

Segment 1 = 0x4000 to 0x5FFF

Segment 2 = 0x6000 to 0x7FFF

Segment 3 = 0x8000 to 0xFFFF

Step 1: Decide segment boundaries

Step 2: Left shift boundary address by 4 bits

B1

B2

MPU | Creating Segments in 4 Easy Steps

140

Step 3: Write boundary values to MPUSEGB1, MPUSEGB2 register

Step 4: Assign rights and violation responses for each segment

MPU | Access Management

• Define segments as Read, Write, or Execute-only • Can also be any combination of these three • Choose what happens on a violation:

– Option 1 (default): NMI – Option 2: PUC

• When an access violation occurs, the illegal instruction is not executed. • MPULOCK bit – lock MPU settings until a BOR occurs

– Prevents accidental change of segment access rights

141

Lab 3 | Goals

• 3 segments are defined with different access rights – Segment 1: 0x4400 - 0x5FFF (Read/Write/Execute) – Segment 2: 0x6000 – 0x7FFF (Read-Only) – Segment 3: 0x8000 – 0x13FFF (Read/Write/Execute)

• Segment 2 (Read-only) causes an NMI on segment violation • Intentionally cause a violation by writing to 0x6002 • Toggle an LED whenever the NMI occurs

142

Lab 3 | Procedure

1. Fill in the blanks in Wolverine_Lab2_MPU_RunTime.c, using the comments as a guide.

a) Remember Ctrl+Spacebar for auto-complete b) Use the DriverLib documentation to help select the correct parameters

2. Once the code builds, if it is running properly the LED should toggle to show the access violations occurring

3. Use a breakpoint and the memory window to observe that the write to address 0x6002 does not occur (due to access rights).

143

Lab 3 | Filling in the blanks – Configure Segments

• Create three segments and set their access rights: – Segment 1: 0x4400 - 0x5FFF (Read/Write/Execute) – Segment 2: 0x6000 – 0x7FFF (Read-Only) – Segment 3: 0x8000 – 0x13FFF (Read/Write/Execute)

• Enter the two boundaries that will make these three segments • For each segment, enter the type of accesses allowed

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Lab 3 | Filling in the blanks – Configure Segments

• Create three segments and set their access rights: – Segment 1: 0x4400 - 0x5FFF (Read/Write/Execute) – Segment 2: 0x6000 – 0x7FFF (Read-Only) – Segment 3: 0x8000 – 0x13FFF (Read/Write/Execute)

• Enter the two boundaries that will make these three segments • For each segment, enter the type of accesses allowed

145

Lab 3 | Filling in the blanks – Violation configuration

• First, disable PUC on Segment 2 violation (so part doesn’t reset) • Then, enable MPU NMI interrupt • Finally, start MPU protection (so settings take effect)

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• First, disable PUC on Segment 2 violation (so part doesn’t reset) • Then, enable MPU NMI interrupt • Finally, start MPU protection (so settings take effect)

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• In the ISR, clear the interrupt flag for the segment 2 violation


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• In the ISR, clear the interrupt flag for the segment 2 violation

Thanks!

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