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Power MOSFETs with Enhanced Electrical Characteristics by Hao Wang A thesis submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy Department of Materials Science and Engineering University of Toronto © Copyright by Hao Wang 2009
Transcript of Power MOSFETs with Enhanced Electrical Characteristics · Power MOSFETs with Enhanced Electrical...
Power MOSFETs with Enhanced
Electrical Characteristics
by
Hao Wang
A thesis submitted in partial fulfillment
of the requirements for the degree of
Doctor of Philosophy
Department of Materials Science and Engineering
University of Toronto
© Copyright by Hao Wang 2009
ii
ABSTRACT
Power MOSFETs with Enhanced Electrical Characteristics
Hao Wang
Doctor of Philosophy
2009
Department of Materials Science and Engineering, University of Toronto
The integration of high voltage power transistors with control circuitry to form smart
Power Integrated Circuits (PIC) has numerous applications in the areas of industrial and
consumer electronics. These smart PICs must rely on the availability of high performance
power transistors. In this thesis, a vertical U-shaped gate MOSFET (UMOS) and a lateral
Extended Drain MOSFET (EDMOS) with enhanced electrical characteristics are
proposed, developed and verified via experimental fabrication. The proposed new process
and structure offers superior performance, such as low on-resistance, low gate charge and
optimized high breakdown voltage.
In the vertical power UMOS, a novel trenched Local Oxidation of Silicon (LOCOS)
process has been applied to the vertical gate structure to reduce the gate-to-source overlap
capacitance (Cgs). A 40% reduction in Cgs is achieved when compared to conventional
UMOS. A specific on-resistance Ron, sp = 60mΩ·mm2 is observed, which is 45% better
than that of the conventional UMOS. The improvement in the device’s Figure-of-Merit
(FOM = Ron × Qg) is about 58%.
A floating RESURF EDMOS (BV=55V, Ron,sp=36.5mΩ·mm2) with a 400%
improvement in the Safe Operating Area (SOA) when compared to the conventional
EDMOS structure is also presented. The proposed EDMOS employs both drain and
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source engineering to enhance SOA, not only via reducing the base resistance of the
parasitic bipolar transistor, but also suppressing the base current of the parasitic bipolar
transistor under high Vgs and high Vds conditions. A buried deep Nwell allows the device
to have better trade-off between breakdown voltage and on-resistance.
Finally, in order to achieve low gate charge in the EDMOS, a novel orthogonal gate
electrode is proposed to reduce the gate-to-drain overlap capacitance (Cgd). The
orthogonal gate has both horizontal and vertical sections for gate control. This device is
implemented in a 0.18µm 30V HV-CMOS process. Compared to a conventional EDMOS
with the same voltage and size, a 75% Cgd reduction is observed. The FOM is improved
by 53%.
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ACKNOWLEDGEMENTS
First of all, I want to extend my sincere gratitude to my supervisor, Prof. Wai Tung
Ng, for his time, advice, insight and guidance during my Ph.D studies.
I would like to thank Dr. Huaping Xu for his help with measurements, and advice in
planning the fabrication and in setting up simulation experiments.
I also would like to thank my other colleagues in the research group, including
Onishi-san from Fuji Electric, for his very helpful discussion and suggestions, Abraham
Yoo for his useful information about the semiconductor industry, and Quincy Fung for
his hands-on help with computer editing and CMOS process flow explanation.
My sincere gratitude also goes to Asahi Kasei EMD. Their financial and technical
support in the device fabrication has made the realization of this work possible. I would
also like to thank members involved in this collaborative research project, in particular,
Kenji Fukumoto, Ken Abe, Akira Ishikawa, Hisaya Imai, Kimio Sakai, and Kaoru
Takasuka for their technical assistance and generous accommodation in Tokyo, Japan.
Finally, I would like to thank my parents for their many years of support in all aspects
of my life. Without their moral and financial support, useful suggestions, and constant
encouragement, the completion of this work would not have been possible.
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Power MOSFETs with Enhanced Electrical Characteristics
Chapter 1 Introduction
1.1 HVICs and Smart PICs……………………………………………………………1
1.2 Advantages of Power MOSFET Devices……………………………..…………4
1.3 Implementation of Power Devices…………….………………………..………..5
1.4 Thesis Objectives and Organization ……………..………………………….....8
Chapter 2 Vertical Power MOSFET (UMOS)
2.1 Evolution of Low Voltage Vertical Power MOSFET………………………12
2.2 UMOS Design and Simulation……………...……………..……………………..15
2.2.1 Dependence of Epitaxial Thickness……….……………………………..15
2.2.2 Dependence of P-body Doping…………………………………………..18
2.3 Fabrication of a Conventional UMOSFET…………………………………...19
2.4 Trench LOCOS UMOS
2.4.1 Fabrication Process of Trench LOCOS UMOS……………….…….20
2.4.2 Experimental Data……………………………………….……………24
2.4.3 Gate Charge Test……………………………………….……………..26
2.4.4 Unclamped Inductive Switch (UIS) Test……………….…………....27
2.5 Summary of Trench LOCOS UMOS…………………………………………...29
Chapter 3 Lateral Power MOSFET (EDMOS)
3.1 Introduction……………………………..………………………………………31
3.2 EDMOS Enhanced Electrical Characteristics Analysis
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3.2.1 Turn-on and Turn-off Speed.…………………………………..…..…..33
3.2.2 dv/dt Capability…………………………….……………………………..34
3.2.3 REduced SURace Field (RESURF) Analysis ………….……………......36
3.2.4 Safe Operating Area Analysis...…………………...…..…………………39
3.3 Simulation Results
3.3.1 Simulation Results of 18V CMOS
3.3.1.1 Device Structure and Doping Profiles………….….……………..44
3.3.1.2 Breakdown Voltage………………………………………..……….47
3.3.1.3 NMOS Drift Dose Variation………………………………………49
3.3.1.4 PMOS Drift Dose Variation…………………….………………....50
3.3.1.5 Threshold Voltage and IV Curves...................................................51
3.3.2 Simulation Results of 30V CMOS
3.3.2.1 Device Structure and Doping Profiles……………….…..…….56
3.3.2.2 Breakdown Voltage…………………………………………...……58
3.3.2.3 Threshold Voltage and IV Curves……………………..….……59
3.3.2.4 NMOS Geometry Variation………………………..…….……..62
3.3.2.5 PMOS Geometry Variation……………………..……….……..64
3.4 A Floating RESURF EDMOS with Enhanced Safe Operating Area (SOA)
3.4.1 Methods to Improve SOA
3.4.1.1 Base Resistance Reduction…………………...…………….……..66
3.4.1.2 Base Current Reduction……………………...…………….……..67
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3.4.1.3 Floating RESURF……………………...…………….………...…..69
3.4.2 Simulation Results
3.4.2.1 Breakdown Characteristics………...…………….…………...…..70
3.4.2.2 IV Characteristics………...……………………….…………...…..71
3.4.2.3 Safe Operating Area Characteristics ………….…………...…..74
3.4.3 Summary………………..…………..………….………..……….……….75
3.5 Orthogonal Gate EDMOS
3.5.1 Device Concept and Structure……………….………..…….………..76
3.5.2 Simulation Results
3.5.2.1 Capacitance Characteristics…………………………....……...…..79
3.5.2.2 Gate Charge Test……………………………………......……...…..80
3.5.2.3 IV Characteristics……………………………………....……...…..81
3.5.2.4 Lateral Channel Length Variation…………….……....……...…..81
3.5.2.5 Switching Time Results…………..…………….……....……...…..83
3.5.2.6 dv/dt Capability…………………..…………….……....……...…..84
3.5.3 OG-EDMOS Fabrication……...…………………………………………85
3.5.4 Summary………………….………………………………………………89
Chapter 4 Experimental Results of EDMOS
4.1 Introduction……………………………………………………………..………92
4.2 Experimental Results of 18V CMOS
4.2.1 Device Structure and Key Ion Implantation…………….……………...92
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4.2.2 Threshold Voltage and IV Characteristics……………………………93
4.2.3 Breakdown Characteristics…………..……………………………….…96
4.3 Experimental Results of 30V CMOS
4.3.1 Device Structure and Key Ion Implantation.……….…………………..97
4.3.2 Threshold Voltage and IV Characteristics...……………………………98
4.3.3 Breakdown Characteristics……………….…………………………….100
4.3.4 Geometry Variation
4.3.4.1 NMOS Breakdown Voltage vs. Geometry……………………….103
4.3.4.2 PMOS On-resistance vs. Geometry………………………………105
4.4 Experimental Results of EDMOS with Enhanced SOA
4.4.1 Snapback Characteristics Comparison………………………………107
4.5 Experimental Results of Orthogonal Gate EDMOS (OG-EDMOS)
4.5.1 Threshold Voltage and IV Characteristics…………………………….110
4.5.2 Breakdown Characteristics…………………………………………….112
4.5.3 Capacitance Characteristics…………………………………………....114
Chapter 5 Conclusions and Future Work
5.1 Conclusions…………………………………………………………………….118
5.2 Future Work…………………………...……………………………………….120
Appendix I UMOS Design and Process Flow…………….…………………….122
Appendix II EDMOS Process Flow………………………………………………132
Appendix III General EDMOS Design Considerations………………………….145
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Appendix IV Technology Computer Aided Design (TCAD)…………………….161
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List of Figures Chapter 1
Figure 1.1 Applications for power devices with respect to their voltage and current
ratings………………...……………………………………………………3
Figure 1.2 Ron,sp vs. BV from most recently published results………………………..7
Chapter 2
Figure 2.1 Structure of a typical VMOS…………………………………………….12
Figure 2.2 Structure of a typical VDMOS………………..…………………………13
Figure 2.3 Structure of a standard UMOS………...…………………………………13
Figure 2.4(a) Conventional UMOS…………………………………………………….15
Figure 2.4(b) Breakdown dependence vs. Epi-thickness……………………………….15
Figure 2.5 Threshold voltage vs. Epi-thickness…………..…………………………16
Figure 2.6 UMOS Capacitance…………...…………………………………………17
Figure 2.7 Breakdown voltage vs. p-body dose……..………………………………18
Figure 2.8(a) Conventional UMOS…………………………………………………….20
Figure 2.8(b) Trench LOCOS UMOS…………..………………………………………20
Figure 2.8(c) Potential comparisons..…………..………………………………………21
Figure 2.9 Schematic of the trench LOCOS process to form thick oxide layers at
trench bottom and shoulders…………………………………………......22
Figure 2.10 Schematic of p+(2) boron implantation and deep body source contact
formation…………………………………………………………………23
Figure 2.11 Measured breakdown IV curve of trenched LOCOS UMOS with and
without p+(2) boron implantation………………………………………23
Figure 2.12 Measured characteristics of trenched LOCOS UMOS…………………24
Figure 2.13 A SEM cross-sectional indicating boron segregation reduces the effective
channel length……………………………..……………………..………24
Figure 2.14 The circuit used for gate charge test……………………………………26
Figure 2.15 Measured gate charge characteristics of trenched LOCOS UMOS and
conventional UMOS…………………………………………………….27
Figure 2.16 The circuit used for UIS test……………..………………………………28
Figure 2.17 UIS test results of UMOS devices fabricated by conventional and trenched
LOCOS process………………………………………………………….29
Chapter 3
Figure 3.1(a) Standard NMOS……………………………………………………..…...31
Figure 3.1(b) 18V N-type EDMOS……………………………………………………..31
Figure 3.1(c) 30V N-type EDMOS……………………………………………………..31
Figure 3.2 Power MOSFET turn-on and turn-off waveform………………………34
Figure 3.3 Equivalent circuit of power MOSFET………………...…………………35
Figure 3.4 Parasitic npn BJT of EDMOS……………………………………………39
Figure 3.5 Snapback phenomenon of EDMOS…………...…………………………42
Figure 3.6 Phosphorus penetration of gate………………..…………………………44
Figure 3.7 Device structure of 18V EDMOS……………..…………………………45
Figure 3.8(a) Doping concentration across the Ndrift region…………………………46
Figure 3.8(b) Doping concentration across the Pdrift region…………………………46
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Figure 3.9(a) N-type EDMOS simulated device breakdown potential characteristics…47
Figure 3.9(b) P-type EDMOS simulated device breakdown potential characteristics....46
Figure 3.10(a) N-type EDMOS breakdown IV characteristics…………………………..48
Figure 3.10(b) P-type EDMOS breakdown IV characteristics…………………………..48
Figure 3.11 Breakdown dependence with Ndrift dose………………………………49
Figure 3.12 Specific on-resistance dependence with Ndrift dose…………………….50
Figure 3.13 Breakdown dependence with Pdrift dose………………………………50
Figure 3.14 Specific on-resistance dependence with Pdrift dose…………………….51
Figure 3.15 Threshold voltage of N-type EDMOS…………………...………………51
Figure 3.16 Threshold voltage of P-type EDMOS…………………...………………52
Figure 3.17 IV characteristics of N-type EDMOS……………………………………52
Figure 3.18 IV characteristics of P-type EDMOS………...…………………………..53
Figure 3.19(a) N-type EDMOS structure..........................................................................56
Figure 3.19(b) P-type EDMOS structure……………...…………………………………56
Figure 3.20(a) Doping concentration across N-type EDMOS drain region……………..57
Figure 3.20(b) Doping concentration across P-type EDMOS drain region……………..57
Figure 3.21(a) N-type EDMOS breakdown IV characteristics……..……………………58
Figure 3.21(b) P-type EDMOS breakdown IV characteristics……..……………………58
Figure 3.22 Threshold voltage of N-type EDMOS………...…………………………59
Figure 3.23 IV characteristics of N-type EDMOS……………………………………59
Figure 3.24 Threshold voltage of P-type EDMOS……………………………………60
Figure 3.25 IV characteristics of P-type EDMOS…………………………………….60
Figure 3.26(a) N-type EDMOS dimensions………………..……………………………62
Figure 3.26(b) Specific on-resistance dependence with A parameter…………...………62
Figure 3.26(c) Specific on-resistance dependence with B parameter…………...………63
Figure 3.27(a) P-type EDMOS dimensions………………...……………………………64
Figure 3.27(b) Specific on-resistance dependence with A parameter…………...………64
Figure 3.27(c) Specific on-resistance dependence with B parameter…………...………65
Figure 3.28 Device structure of a conventional EDMOS transistor showing the
parasitic NPN and the base resistance…………………………………66
Figure 3.29 EDMOS transistor with p-buried layer to suppress the turn-on of the
emitter-base junction……………………………………………………..67
Figure 3.30 Phosphorus implantation is used in the drain region to suppress hole
current…………………...……………………………………………….67
Figure 3.31(a) Hole current vectors in conventional EDMOS…………………………68
Figure 3.31(b) Hole current vectors in proposed EDMOS…………………………….68
Figure 3.32 Potential contours comparison between (a) the conventional EDMOS and
(b) the proposed EDMOS………………………………………………..69
Figure 3.33 Comparison of the breakdown voltages between the conventional and the
proposed EDMOS transistors……………………………………………70
Figure 3.34 Comparison of the IV characteristics between the proposed EDMOS
transistor with p-buried layer and the conventional EDMOS transistor....71
Figure 3.35 Doping profile at the drain region for the proposed EDMOS transistor
with extra phosphorus implant, and the conventional EDMOS structure.72
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Figure 3.36 Comparison of IV characteristics EDMOS structures with p-buried layer,
p-buried layer and phosphorus implant at the drain, and conventional
structure…………………………………………………………………..72
Figure 3.37 Snapback characteristics of the proposed EDMOS………...……………73
Figure 3.38 Snapback characteristics of the conventional EDMOS………………….73
Figure 3.39 Comparison of the SOA between the conventional EDMOS transistor and
the proposed EDMOS transistor…………………………………………74
Figure 3.40 Device structure for (a) conventional EDMOS, and (b) OG-EDMOS
transistors……………………………………………………………….76
Figure 3.41 Potential contours at 3V/line for (a) conventional EDMOS, (b) orthogonal
gate EDMOS transistors, (c) conventional EDMOS without field
plate.……………………………….……………………………………..77
Figure 3.42 Comparison of Cgd, Cgs, and Cds between orthogonal gate and
conventional EDMOS transistors……….……………………………….79
Figure 3.43 Gate charge characteristics………………………………………………80
Figure 3.44 IV characteristics of the N-type OG-EDMOS transistors………………..81
Figure 3.45 Simulated specific on-resistance variation vs. lateral channel length……82
Figure 3.46(a) Switching time test circuit……………………………………………….83
Figure 3.46(b) Switching time waveforms…..…………………………………………..83
Figure 3.47 dv/dt capability comparisons between orthogonal gate and conventional
gate EDMOS transistors…………………………………………………84
Figure 3.48 Standard CMOS process flow with additional steps for the orthogonal gate
EDMOS implementation……………...…………………………………86
Figure 3.49 Orthogonal gate fabrication process flow………………………………..87
Figure 3.50 Breakdown dependence vs. STI depth…………………………………88
Figure 3.51 Cgd dependence with vertical gate width………………………………..88
Chapter 4
Figure 4.1(a) N-type EDMOS…………………………………………………………92
Figure 4.1(b) P-type EDMOS…………………………………………………………93
Figure 4.2(a) Threshold voltage of N-type EDMOS……………….…………………..94
Figure 4.2(b) Threshold voltage of P-type EDMOS……………………………………94
Figure 4.3(a) IV characteristics of N-type EDMOS……………………………………95
Figure 4.3(b) IV characteristics of P-type EDMOS…………………………………….95
Figure 4.4 Breakdown voltage of EDMOS………………………………………….96
Figure 4.5(a) N-type EDMOS…………………………………………………………97
Figure 4.5(b) P-type EDMOS…………………………………………………………97
Figure 4.6(a) Threshold voltage of N-type EDMOS……………….…………………..98
Figure 4.6(b) Threshold voltage of P-type EDMOS……………………………………99
Figure 4.7(a) IV characteristics of N-type EDMOS……………………………………99
Figure 4.7(b) IV characteristics of P-type EDMOS…………………………………100
Figure 4.8(a) Breakdown voltage of N-type EDMOS………………………………100
Figure 4.8(b) Breakdown voltage of P-type EDMOS…………………………………101
Figure 4.9 NMOS geometry………………………………………………………103
Figure 4.10 BV vs. A dimension…………………………………………………….103
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Figure 4.11 BV vs. B dimension…………………………………………………….104
Figure 4.12 PMOS geometry………………………………………………………105
Figure 4.13(a) Specific on-resistance vs. A dimension……..………………………….105
Figure 4.13(b) Specific on-resistance vs. B dimension…..…………………………….106
Figure 4.14(a) Snapback of conventional EDMOS……………………………………107
Figure 4.14(b) Snapback of proposed EDMOS………………………………………107
Figure 4.15 OG-EDMOS……………………………………………………………109
Figure 4.16(a) Threshold voltage of N-type OG-EDMOS……………………………..110
Figure 4.16(b) Threshold voltage of N-type OG-EDMOS……………………………..110
Figure 4.17(a) IV characteristics of N-type OG-EDMOS……………………………111
Figure 4.17(b) IV characteristics of P-type OG-EDMOS……………………………111
Figure 4.18(a) Breakdown characteristics of N-type OG-EDMOS….…………………112
Figure 4.18(b) Breakdown characteristics of P-type OG-EDMOS…………………….112
Figure 4.19 Comparison of Ron,sp vs. BV of the OG-EDMOS and previously published
results……………………………………...……………………………113
Chapter 5
Figure 5.1 Comparison of Ron,sp Vs. BV of power MOSFETs with previously
published results …………………………………………………..……119
Figure 5.2 Novel UMOS structure…………………………………………………120
Figure 5.3 Orthogonal Gate (OG) floating RESURF EDMOS structure…………121
Appendix I
Figure A1.1 UMOS structure ………………………………………………………..122
Figure A1.2 UMOS process flow chart…………………………………………...125
Figure A1.3 UMOS layout…………………………………………………………126
Figure A1.4 UMOS masks…………………………………………………………127
Figure A1.5 UMOS process flow…………………………………………………….128
Appendix II
Figure A2.1 EDMOS process flow chart………………………………………….133
Figure A2.2 NMOS die photo……………………………………………………134
Figure A2.3 EDMOS masks……………………………………………………….135
Figure A2.4 EDMOS process flow…………………………………………………137
Appendix III
Figure A3.1 Effect of channel hot carriers…………………………………………147
Figure A3.2 Planar diffused junction with field plate at the edge……………………149
Figure A3.3 Depletion junctions with field plate formed by the gate extension……150
Figure A3.4 N-type MOSFET with parasitic bipolar transistor……………………151
Figure A3.5 IV characteristics of snap back breakdown…………………………….152
Figure A3.6 Punch through breakdown……………………………………………153
Figure A3.7 Resistive components of EDMOS……………………………………154
Figure A3.8 Schematic of RESURF concept………………………………………158
Figure A3.9 Surface breakdown……………………………………………………..158
Figure A3.10 Bulk breakdown………………………………………………………158
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Appendix IV
Figure A4.1 TS4 simulation of oxidation….…………………………………………162
Figure A4.2 TS4 simulation of implantation………………………………………163
Figure A4.3 TS4 simulation of etch………………………………………….………164
Figure A4.4 TS4 simulation of deposition……………………………………...……165
Figure A4.5 TS4 simulation of trench LOCOS………………………………………166
Figure A4.6(a) TS4 simulation of metallization ………………………………………167
Figure A4.6(b)TS4 simulation of doping profile…...…………………………………167
Figure A4.7 Boron SIMS and simulation data before and after calibration………168
Figure A4.8 UMOS input structure form TS4……………………………….………170
Figure A4.9 Medici simulation of gate characteristics…………….………………171
Figure A4.10 Medici simulation of drain characteristics…………….………………172
Figure A4.11 Medici simulation of current flow lines…………….……………..……172
Figure A4.12 Medici simulation of gate characteristics…………….………………173
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List of Tables
Table 2.1 Electrical characteristics of conventional UMOS and trenched LOCOS
UMOS……………………………………………………………………25
Table 3.1 RESURF condition Nd and junction depth………………………………38
Table 3.2(a) 18V NMOS key ion implantation conditions……………………………43
Table 3.2(b) 18V PMOS key ion implantation conditions…………………………….43
Table 3.3 Summarized design parameters for EDMOS transistors………...………43
Table 3.4 Simulated results of 18V EDMOS……………………………………….53
Table 3.5(a) 30V NMOS key ion implantation conditions…………...……………….54
Table 3.5(b) 30V PMOS key ion implantation conditions…………………………….55
Table 3.6 Summarized design parameters for EDMOS transistors………………...55
Table 3.7 Summarized simulated results……………………...……………………61
Table 3.8 Electrical characteristics comparison between the conventional and
orthogonal gate structure EDMOS……………………………………….85
Table 4.1(a) 18V NMOS key ion implantation conditions……………………………93
Table 4.1(b) 18V PMOS key ion implantation conditions……………………………93
Table 4.2(a) 30V NMOS key ion implantation conditions……………………………98
Table 4.2(b) 30V PMOS key ion implantation conditions……………………………98
Table 4.3 Summarized simulation and measured results………………………101
Table 4.4 Capacitance comparison between OG-EDMOS and conventional
EDMOS………………………………………………………………...114
Table 4.5 Summarized measured and simulation results………………………….115
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List of Symbols and Abbreviations Symbols:
BV Breakdown Voltage (V)
Ron,sp Specific on-resistance (mΩ-mm2)
Vth Gate threshold voltage (V)
Vgs Gate-to-source voltage (V)
Vds Drain-to-source voltage (V)
Id Continuous drain current (A)
Gm Transconductance (S)
dv/dt Peak diode recovery rate (V/ns)
Cgd Gate-to-Drain Capacitance (F)
Cgs Gate-to-Source Capacitance (F)
Cds Drain-to-Source Capacitance (F)
Ciss Input capacitance (F), Ciss=Cgs+Cgd, Cds shorted.
Crss Reverse transfer capacitance (F), Crss=Cgd
Coss Output Capacitance (F), Coss=Cds+Cgd
ft Cutoff frequency (Hz)
fmax Maximum oscillation frequency (Hz)
Qg Total gate charge (C)
Qgs Gate-to-source charge (C)
Qgd Gate-to-drain charge (C)
Pd Power dissipation (W)
T Temperature (K)
q Electron charge 1.6×10-19
(C)
Xj Junction depth (µm)
Abbreviations:
AC Alternating Current
AKM Asahi Kasei Microsystems Co., Ltd.
BJT Bipolar Junction Transistor
CMOS Complementary MOSFET
CMP Chemical Mechanical Polishing
DC Direct Current
DTI Deep Trench Isolation
EDMOS Extended Drain MOSFET
FOM Figure-of-Merit
HV High Voltage
IC Integrated Circuit
I/I Ion Implantation
LOCOS Local Oxidation of Silicon
OG-EDMOS Orthogonal Gate Extended Drain MOSFET
MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
S/D Source/Drain
SEM Scanning Electron Microscopy
SIMS Secondary Ion Mass Spectrometry
xvii
SoC System-on-Chip
SOA Safe Operating Area
STI Shallow Trench Isolation
TCAD Technology Computer Aided Design
RTA Rapid Thermal Annealing
UMOS U-shaped gate MOSFET
UIS Unclamped Inductive Switch
1
Chapter 1 Introduction
Power semiconductor devices appeared in 1952 with the introduction of the power
diode by R.N. Hall [1]. They were made of germanium and had a voltage blocking
capability of 200 volts and a current rating of 35 amperes. The thyristors appeared in
1957 [1]. They are able to withstand very high reverse breakdown voltage and are also
capable of carrying high current. One disadvantage of the thyristor is that once it is turned
on, it cannot be turned off by external control. Power must be disconnected from the
device in order for it to be turned off. This is a major disadvantage for switching circuits.
Although bipolar transistors were invented in 1948, the first devices with substantial
power handling capabilities were not introduced until the 1960s [1]. These components
overcome the limitations of the thyristors, as they can be turned on or off by controlling
the base terminal.
With the improvements of the Metal Oxide Semiconductor (MOS) technology
(initially developed to produce integrated circuits), power MOSFETs became available in
the late 1970s. International Rectifier introduced a 25A, 400V power MOSFET in 1978
[1]. These devices allow operation at higher frequency than bipolar transistors, but are
limited to the low voltage applications.
The Insulated Gate Bipolar Transistor (IGBT) became widely available in the 1990s.
This component has the power handling capability of the bipolar transistor, with the
advantages of the isolated gate drive of the power MOSFET. It has since almost
completely replaced the bipolar transistor in power applications.
2
1.1 HVICs and Smart PICs
The continuing drive for higher integration density, circuit complexity and lower
power dissipation in modern Very Large Scale Integration (VLSI) chips has led to the
aggressive down scaling of both the device dimensions and power supply voltages in
advanced Complementary Metal Oxide Semiconductor (CMOS) technologies. However,
in many electronic applications, both decision making (data processing) and actuation
(power electronics for motor drives, solenoids, displays, etc.) are required [1, 2, 3].
Therefore, it is often necessary to perform level shifting of the digital control signals to
higher voltage levels that are required to drive the gate terminal of the output power
devices. In these situations, conventional VLSIs, with only low voltage CMOS logic
circuits cannot be used. Many existing circuit board level implementations use low
voltage CMOS chips for data processing and discrete components for level shifting. In
this case, off-chip components and interconnections between chips need to be added. This
leads to an increase in the system weight, size, cost, and electromagnetic interference
(EMI) and makes it less reliable. [4]
To solve this problem, it is necessary to develop techniques that allow the integration
of high voltage device structures with low voltage circuitry on a single silicon chip. This
technology is classified either as High Voltage Integrated Circuits (HVIC) or Power
Integrated Circuits (PIC), depending on the level of power dissipation (normally, PIC
would supply currents of more than several amperes). This has created the opportunity
for a rapid penetration of power electronics in aerospace, industrial and consumer
products. The applications for power semiconductor technology stretch over a very large
3
range of power levels. The voltage and current handling needs for various applications
are shown in Figure 1.1.
Figure 1.1 Applications for power devices with respect to their voltage and current
ratings.
There is a group of power electronic systems that involve switching at a high voltage
range but with low to medium current level. These systems have applications, including
Device Blocking Voltage Rating (V)10 100 1000 10000
0.01
0.1
1
10
100
1000
DisplayDrives
Telecom.Circuits
LampBallasts
MotorControl
FactoryAutomat.
HVDC
4
drivers for flat panel display and small DC motor control and DC/DC converters [5]. For
these applications, it is usually preferable to perform most of the signal processing at low
voltage, while the resulting output control signal is shifted to the appropriate voltage level.
Therefore, it is convenient to implement these systems with ICs that contain both power
devices and low voltage standard components such as bipolar transistors or MOSFETs.
Power devices in HVIC are usually required to perform switching functions. There
are a few types of power devices that can be integrated with standard components. These
devices include power MOSFET and power bipolar transistors, and thyristors. Among
these devices, the Extended Drain MOS [6] (EDMOS) is the most commonly used in
HVIC due to the advantages that it offers when compared to bipolar transistors. These
advantages are summarized in the next section.
1.2 Advantages of Power MOSFET Devices
Power devices are important elements in handling high voltage and current
applications. Before the development of power MOSFETs in the 1970s, power bipolar
transistors were the only devices available for high-speed power applications. Despite
their low production cost, bipolar transistors have become less desirable due to their low
current gain at typical current operating levels. Being a current-controlled device, a large
base drive current is required to maintain it in the on-state. There are a few important
advantages of MOS technology:
1. It has an excellent low on-state voltage drop due to the low resistance of the drift
region that supports these modest voltages.
2. The power MOSFET has very high input impedance in the steady-state due to its
metal-oxide-semiconductor (MOS) gate structure. It is classified as a voltage
5
controlled device. It is also suitable for large scale integration because of the small
gate currents that are required to charge and discharge the input gate capacitance.
When the operating frequency becomes high (> 100 kHz), this capacitive current
can become significant but it is still possible to integrate the control circuit due to
the low gate bias voltages (typically 5 to 15 V) required to drive the device.
3. In comparison with bipolar transistors, the MOSFET has a very fast inherent
switching speed due to the absence of the minority carrier injection. The switching
time for the MOSFET is dictated by the ability to charge and discharge the input
capacitance rapidly.
4. The MOSFET has superior secondary breakdown immunity and a forward biased
Safe Operating Area (SOA) when compared with bipolar transistors. This allows
the elimination of snubber circuits for protection of the switch during operation in
typical hard-switching PWM circuits used for motor control.
1.3 Implementation of Power Devices
Power devices can also be categorized into either vertical or lateral devices. The
vertical structure has a current path that flows from the top to the bottom via the substrate.
The lateral structure has a current path that enters and leaves the chip through the upper
surface of the chip. This feature allows different types and multiple numbers of lateral
devices to be implemented on the same substrate with the appropriate electrical isolation.
There are two approaches to implement power devices in HVIC. The first one is to
use a dedicated technology. The power devices fabricated with this technology usually
have a better current handling capability and a minimized device area at a given
breakdown voltage. One example of this technology is the Bipolar/CMOS/DMOS
6
process (BCD) [7]. Despite the fact that these dedicated technologies can provide good
performance of the power devices, the fabrication process is very complex and expensive.
As the BCD process is very expensive, all the available features must be put into use in
order to justify the cost.
The second approach to implementing power devices in HVIC is to start with a
standard low voltage CMOS process where the supplementary masks and processing
steps necessary to implement the HV features are added. The CMOS compatible
approach is significantly more cost effective since most existing processes are already
fine-tuned and are running at high volume. Computer Aided Design (CAD) tools for the
low voltage circuit design can remain unchanged. Special layout rules and models can be
added to facilitate the design of the high voltage circuits. One of the examples using this
approach is an advanced HV technology, e.g. Intelligent Interface Technology (I2T) [8],
based on a standard low voltage 0.7µm CMOS process produced by Alcatel Mietec. It
uses 5 additional masks and extra processing steps to implement LV and HV bipolar
transistors.
In general, the figure of merit that measures the performance of a power device is the
product of specific on-resistance (Ron,sp) and gate charge at a given breakdown voltage.
The specific on-resistance is defined as the product of the on-resistance and the area of
the device (Ron ×Area). The silicon limit [9] as specified in Equation 1.1 is the theoretical
performance envelope for power MOSFETs.
Ron-sp=5.9×10-9
×VB2.5
(Ω·cm2) (1.1)
7
The silicon limit implies that as breakdown voltage (BV) increases, the specific on-
resistance also increases. Therefore, there is always a trade-off between the breakdown
voltage and the specific on-resistance. A comparison of Ron,sp vs. BV from most recently
published results is shown in Figure 1.2.
Figure 1.2 Ron,sp vs. BV from most recently published results.
0.01
0.1
1
10
100
10 100
Breakdown voltage (V)
Specific on-resistance (mΩcm2)
EDMOS
UMOS
Si-limit
[10]
[11]
[10]
[18][12]
[13]
[14]
[15]
[16]
[17]
[13]
8
1.4 Thesis Objectives and Organization
As illustrated in Figure 1.1, quite a few applications fall in the range below 100V
with low to medium current level. Applications such as DC/DC converters require
optimized power devices with low specific on-resistance to reduce power dissipation.
Other applications such as a flat panel driver may require bi-directional switches with
high gate driving voltage. In order to satisfy a wide range of applications, it is necessary
to provide device structures with these features in the HVIC. A dedicated process can be
used to implement the HVIC. However it will be very expensive.
The objective of this thesis is to develop a CMOS compatible process with high
voltage n-type and p-type vertical MOSFET (UMOS) and lateral MOSFET, such as
Extended Drain MOSFET (EDMOS) optimized for applications below the 100V range.
The device development is based on 0.18 µm CMOS process for EDMOS with minimum
additional process steps to minimize the cost and complexity of the fabrication process.
The electrical characteristics of the standard CMOS transistors should remain unchanged
for low voltage operation.
The base CMOS process is an existing CMOS production technology from Asahi
Kasei Microsystem (AKM) [19], Japan. AKM is a leading supplier of mixed signal
integrated circuits for audio, video, networking and wireless communications. The
fabrication of the actual devices is carried out by AKM.
This thesis is organized as follows: Chapter 2 discusses the vertical power MOSFET
(UMOS). Conventional UMOS has been designed and fabricated. This is followed by the
description of a novel trenched LOCOS UMOS. An electrical characteristics comparison
is also presented. Chapter 3 introduces the lateral Extended Drain power MOSFET
9
(EDMOS). A novel EDMOS structure with an enhanced Safe Operating Area (SOA) and
an orthogonal gate EDMOS are also proposed. Chapter 4 describes the experimental
measurement results for the EDMOS transistors, and presents the measured electrical
characteristics. Chapter 5 concludes the thesis and provides suggestions for future work.
Appendix I contains a detailed process flow for the UMOS fabrication and an analysis of
specific on-resistance. Append II provides the EDMOS process flow. Appendix III
includes general EDMOS design considerations. Appendix IV presents TCAD simulation
illustrations of the UMOS.
10
REFERENCES
[1] B.J Baliga, Power Semiconductor Devices, ISBN 0-534-94098-6.
[2] B.J Baliga, An overview of Smart Power Technology, IEEE Trans. Electron
Devices, Vol. 38, pp.1568-1575, 1991.
[3] B.Murari, Smart Power Technology and the evolution from Protective Umbrella to
Complete System, IEDM Tech. Dig., pp. 9-15, 1995.
[4] D.A. Grant, J.Gowon, Power MOSFET Theory and Applications, John Wiley
Interscience, 1989.
[5] Hussein Ballan, Michel Declercq, High Voltage Devices and Circuits in Standard
CMOS Technologies, Kluwer Academic Publishers, 1999.
[6] Peter C Mei, Katsumi Fujikura, Takaaki Kawano,Satwinder Malhi, A High
Performance 30V Extended Drain RESURF CMOS Device for VLSI Intelligent
Power Applications, Symposium on VLSI Technology Digest of Technical Papers,
pp.81-82,1994.
[7] C.Contiero, P.Galbiati, M.Palmieri, L.Vecchi, LDMOS implementation by large tilt
implant in 0.6µm BCD5 process, flash memory compatible, Power Semiconductor
Devices and ICs, 1996. ISPSD ’96 Proceedings, pp.75-78, May 1996.
[8] Alcatel Mietec I2T Design and layout manual 1997.
[9] Chengming Hu, Optimum doping profile for minimum ohmic resistance and high-
breakdown voltage, IEEE Trans. on Electron Devices, Vol. ED-26, No. 3, pp. 243-
245, March 1979.
[10] S Pendharkar, R Pan, T Tamura, B Todd, T Efland, 7 to30V state-of-art power
device implementation in 0.25/spl mu/m LBC7 BiCMOS-DMOS process
technology, Power Semiconductor Devices and ICs, 2004. ISPSD ’04 Proceedings,
pp. 419-422, May 2004.
[11] In’t Zandt, M.A.A; Hijzen, E.A; Hueting, R.J.E; Koops, G. E.J, Record low
specific on-resistance for low-voltage trench MOSFETs, IEE Proceeding: Circuits,
Devices and System, v 151, n 3, pp. 269-272, June 2004.
11
[12] Jongdae Kim, Tae Moon Roh; Sang-Gi Kim; II-Yong Park; A novel process for
fabricating high density trench MOSFETs for DC-DC converters, ETRI Journal, v
24 n 5, Oct. 2002.
[13] V. Khemka, V. Parthasarathy, R. Zhu, A. Bose, T. Roggenbauer, Floating
RESURF(FRESURF) LDMOSFET devices with breakthrough BVdess-Rdson (for
example:47V-0.28mΩ·cm2
or 93V-0.82mΩ·cm2), Power Semiconductor Devices
and ICs, 2004. ISPSD ’04 Proceedings, pp. 415-418, May 2004.
[14] R. Zhu, V. Khemka, A.Bose, T. Roggenhauer, Stepped-Drift LDMOS: A Novel
Drift Region Engineered Device for Advanced Smart Power Technologies, Power
Semiconductor Devices and ICs, ISPSD ’06 Proceedings, pp. 1-4, June 2006.
[15] H. Takaya, K. Miyagi, K.Hamada, Floating island and thick bottom oxide trench
gate MOSFET(FITMOS)- A 60V ultra low on-resistance novel MOSFET with
superior internal body diode, Power Semiconductor Devices and ICs, ISPSD ’05
Proceedings ,pp.43-46, 2005.
[16] Y. Miura, H. Ninomiya, K. Kobayashi, High performance superjunction
UMOSFETs with split p-columns fabricated by multi-ion-implantations, Power
Semiconductor Devices and ICs, ISPSD ’05 Proceedings, pp.39-42, 2005.
[17] H. Ninomiya, Y. Miura, K. Kobayashi, Ultra-low on-resistance 60-100V
superjunction UMOSFETs fabricated by multiple ion-implantation, Power
Semiconductor Devices and ICs, ISPSD ’04 Proceedings, pp. 177-180, 2004.
[18] W. Nehrer, L. Anderson, T. Debolske, Power BICMOS process with high voltage
device implementation for 20V mixed signal circuit application, Power
Semiconductor Devices and ICs, ISPSD ’01 Proceedings, pp. 263-266, 2001.
[19] Asahi Kasei Microsystems., http://www.akm.com/
12
Chapter 2 Vertical Power MOSFET (UMOS)
The design and implementation of trench MOSFET are presented in this chapter. The
UMOS devices are designed to be implemented by a standard 0.35µm CMOS technology
from AK EMD Japan. The fabricated prototype discrete devices are suitable for
automotive applications. They can also be incorporated into integrated circuits.
2.1 Evolution of Low Voltage Vertical Power MOSFET
The first power MOSFETs were developed in the 1970’s based upon the VMOS [1]
structure shown in Figure 2.1. The V-groove in the structure was created by using
preferential etching with potassium hydroxide (KOH)-based solutions. But this led to
instabilities in the threshold voltage. In addition, the sharp tip at the bottom of the V-
groove created a high electric field which degraded its breakdown voltage.
Figure 2.1 Structure of a typical VMOS.
Consequently, the VMOS structure was displaced by the DMOS [2] structure shown
in Figure 2.2 which was based upon the diffusion of the p-base and n+ source regions
n+ n+
p-base p-base
n-epi (n-drift)
Source Gate
Drain
Source
n+ substrate
p+ p+
13
using the edge of the poly-silicon as a masking boundary. This process is called double-
diffusion because both implantations are done through the same window as defined by
the poly-silicon gate. The advantage of employing this double-diffusion technique is that
even without using advanced photolithography, a short channel length can be obtained.
Since the channel length is defined by the different diffusion rate of the body and source
dopants, the channel length can be accurately controlled. The butting contact at the
source with the p+ region ties the p-body to the same potential.
Figure 2.2 Structure of a typical VDMOS.
n+ n+
p-base p-base
n-epi (n-drift)
Source Gate
Drain
Source
n+ substrate
p+ p+
n+ n+
p-body p-body
n-epi (n-drift)
Source Gate
Drain
Source
n+ substrate
p+ p+
Figure 2.3 Structure of a standard UMOS.
14
This process enabled fabrication of sub-micron channel lengths without resorting to
high resolution lithography by utilizing the difference in the junction depth of the two
diffusion steps.
For a silicon MOSFET with 70V blocking capability, the ideal specific on-resistance
can be calculated to be 0.25 mΩ·cm2. There is considerable opportunity to improve the
performance of silicon power MOSFETs beyond the capability achieved with the DMOS
structure. An effective method for achieving this is the UMOS structure shown in Figure
2.3. The UMOS gate region can be fabricated by using trench etching processes
originally developed for memory cells in DRAMs. With this process, the UMOS cell size
can be made relatively small (2 µm). This results in an increase in the channel density
(channel width per sq. cm. of device area) and an elimination of the JFET component of
the resistance inherent within the DMOS cell.
Even greater reduction in the specific on-resistance has been achieved by utilizing
deep trench structures where the trench extends all the way down to the n+ substrate. In
this structure, the resistance contribution from the drift region is reduced by the parallel
current flow path created by the formation of an accumulation layer on the sidewalls of
the trench. It is theoretically possible to obtain a specific on-resistance even lower than
the ideal limit for silicon with this structure if the cell pitch is reduced to below 2 µm [3].
However, it must be noted that the blocking voltage of this structure is limited to 30 V by
the high electric field created in the gate oxide by the extension of the trench into the n-
epi drift region.
15
2.2 UMOS Design and Simulation
A 70V rated UMOS for automotive application has been proposed and simulated in
this section. The device structures and doping profiles are simulated and optimized using
the process simulator, TSUPREM4. The electrical characteristics such as the breakdown
voltage, resistance and threshold voltage are optimized with the aid of the 2D device
simulator MEDICI.
2.2.1 Dependence of Epitaxial Thickness
The breakdown voltage of UMOS is mainly determined by the thickness of the
epitaxial layer. The breakdown voltage for 6 µm, 7 µm, and 8 µm thickness has been
simulated. A doping value of a 5×1015 cm-3 epitaxial layer is chosen as the requirement
by the AKM foundry. The trench width is set for 1 µm and the depth is set for 2 µm, and
therefore, the aspect ratio of the trench is set to 2, which is a reliable and mature trench
fabrication technology for AKM to implement this prototype device.
Figure 2.4 (a) Conventional UMOS (b) Breakdown dependence vs. Epi-thickness
Epi-thickness
BV vs. Epi-thickness
50
60
70
80
90
5 6 7 8 9
Epi-thickness (µm)
Bre
akd
ow
n V
olt
ag
e (
V)
0
20
40
60
80
100
120
Ro
n,s
p(m
Oh
m-m
m2)
16
From Figure 2.4(b), an epi-thickness of 7 µm is chosen in order to obtain a 70V rating
for the UMOS. The UMOS threshold voltages of 6µm, 7µm, and 8µm epi-thickness are
simulated as shown in Figure 2.5.The threshold voltages are constant at 3.5V in these
three cases.
Figure 2.5 Threshold voltage vs. Epi-thickness
The power MOSFET is capable of operation at high frequencies due to the absence of
minority carrier transport. However, the power MOSFET has a large input capacitance
due to the large active area required to carry substantial drain currents. Consequently, the
frequency response is usually limited by the charging and discharging of the input
capacitance.
The total input capacitance is:
iss gs gdC C C= + (2.1)
The frequency response limited by the RC charging time constant of the input gate
circuit is given by: 1
2input
iss G
fC Rπ
= (2.2)
UMOS: Ids vs Vgs at Vds=0.1V
0E+0
1E-6
2E-6
3E-6
4E-6
5E-6
6E-6
7E-6
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Vgs (V)
Ids(A
/µm
)
6µm 7µm
8µm
17
The capacitances of the UMOS are shown in Figure 2.6, and the Cgs are dominant in
UMOS. Therefore, it is necessary to minimize the gate-to-source capacitance. The trench
LOCOS process is proposed in a later section to address the method of reducing Cgs. It is
clear that a smaller Cgs will provide a lower switching loss and higher cut-off frequency.
Capacitance vs Epi-thickness
0.0E+00
2.0E-16
4.0E-16
6.0E-16
8.0E-16
1.0E-15
1.2E-15
1.4E-15
1.6E-15
1.8E-15
0 5 10 15 20 25 30 35
Vds(V)
Ca
pa
cita
nce
(F/µ
m)
Figure 2.6 UMOS Capacitance
Cgs
Vgs=0V
Cds Cgd
18
2.2.2 Dependence of P-body Doping
For constant epi doping of 5×1015 cm-3, the effect of the p-body dose variation versus
the breakdown voltage has been investigated.
72
73
74
75
2.0E+13 2.2E+13 2.4E+13 2.6E+13 2.8E+13 3.0E+13 3.2E+13 3.4E+13
P-body Dose (cm-2) @ 120keV
Bre
ak
do
wn
Vo
lta
ge
(V
)
87.5
88
88.5
89
89.5
90
90.5
91
Ro
n,s
p(m
Oh
m-m
m2
)
Figure 2.7 Breakdown voltage vs. p-body dose
From Figure 2.7, the breakdown voltage is found to increase with p-body dose until
the dose reaches 3×1013cm-2. At this point the charge balance condition is reached. The p-
body region and the epitaxial layer are depleted. The breakdown voltage will saturate at
74 V, therefore the p-body dose of 3×1013cm-2 is chosen for fabrication.
19
2.3 Fabrication of a Conventional UMOSFET
The device fabrication is based on a 7 µm n-type epitaxial layer with phosphorus
doping of 5×1015 cm-3 on top of a heavily As-doped n+ (100) substrate [4]. Boron
implantation of 3×1013 cm-2 at 120 KeV was used and driven in for 60 minutes at 1150°C
to produce the p-body. n+ ion implantation of 5×1015cm-3 Arsenic at 80 KeV is implanted
after the formation of the p-body. A 2µm deep and 1µm wide U-shaped trench was dry
etched. BF2 was used to adjust the threshold voltage after the growth of a thin layer of
sacrificial oxide. A 700Å gate oxide growth is carried out at 950°C for 15.5 minutes after
briefly annealing and removing the sacrificial oxide. Poly-silicon in-situ refill and
planarization were performed after the gate oxidation. A p+ ion implantation of
2.5×1015cm-3 BF2 at 60 KeV was carried out to form the ohmic contact between
semiconductor and metal. Finally, contact holes were opened for metal deposition.
The specific on-resistance was 110 mΩ·mm2 at Vgs=10V and the breakdown voltage
was 75V.
20
2.4 Trench LOCOS UMOS
2.4.1 Trench LOCOS UMOS Design and Fabrication
In order to further reduce switching loss and Ron, sp, we propose a novel trenched
LOCOS process for the gate oxidation. The oxidation conditions are chosen with
reference to a standard 0.35µm CMOS LOCOS isolation technology, but in the vertical
direction inside of the trench. A comparison of the device structures between the
proposed trenched LOCOS UMOS and the conventional UMOS is as shown in Figure 2.8.
The channel length L2 for the trench LOCOS UMOS is shorter than that for the
conventional UMOS, L1, and the current path width A2 is wider than that for the
conventional UMOS, A1. Using the trenched LOCOS technique, the oxide at the
shoulder of the UMOS is much thicker than that in the conventional UMOS. The circle
indicates the difference between conventional UMOS and trenched LOCOS UMOS. The
trenched LOCOS produced bird’s beaks at the trench shoulders.
Figure 2.8 (a) Conventional UMOS (b) Trench LOCOS UMOS
poly-Si
Source
L2
A2
Drain
poly-Si
Thick oxide
L1
A1
Source Thin oxide
Drain
poly-Si
21
The reduction in on-resistance is due to both a reduction in channel length and an
increase in the width of the current path near the bottom of the gate trench. This is due to
the fact the channel length is reduced from L1 = 1.5µm to L2 =0 .9µm, and width of the
current path is increased from A1 = 1µm to A2 = 1.4µm, respectively, as Figure 2.8(a) (b).
As a further proof of the reason why channel length is not the only deciding factor, a
comparison of the potential distributions between the conventional UMOS and LOCOS
UMOS is presented in Figure 2.8 (c). As can be seen, the potential contours are quite
dense in the p-body near the bottom of the trench for the conventional UMOS. However,
the LOCOS UMOS exhibits much more spacing between potential contours in the same
location. This indicates both the channel length reduction and current path increase
contribute to a significant on-resistance reduction.
Vgs=10V Vds=3V 0.3V/line
Potential lines are dense, indicating high channel resistance
Figure 2.8 (c) Potential comparisons
Potential lines are more spaced out, indicating low channel resistance
Vgs=10V Vds=3V 0.3V/line
22
A LOCOS process was carried out to form a thick oxide layer at the trench sidewall.
The Si3N4 deposition and etch back leaves open areas to form LOCOS at the trench
bottom, and at the trench shoulders (see Figure 2.9). This process is carried out at 950°C
for 100 minutes in oxygen and hydrogen ambient. This is simpler and easier to control
when compared to the approach of oxide deposition and etch back introduced by Takaya et
al. [5].The effect of stress on oxidation becomes reduced due to the relief of stress by
appearance of viscous flow of SiO2 at temperature greater than 950 ºC [6].
After nitride removal and a brief sidewall oxide cleaning, gate oxidation at 950 oC
was performed to form a 700 Å gate oxide on the trench wall. As visualized in simulation,
this relatively high temperature oxidation causes some segregation of boron and
phosphorus at the oxide and epitaxial layer interface, which reduces the effective channel
length. This also helps to reduce the device Ron,sp. On the other hand, the sidewall gate
oxide thickness is increased at the top part of the UMOS due to the trenched LOCOS
process. This thick oxide at the n+ source decreases Cgs significantly.
Figure 2.9 Schematic of the trenched LOCOS process to form thick oxide layers at trench bottom and shoulders.
n + s ub ( 1 0 0 )
n e p i
p p S i
3 N
4
n + s u b ( 1 0 0 )
n e pi
p p
n + s u b ( 1 0 0 )
n e p i
p p
L o c o s
23
In order to force the breakdown location to be at the bottom of the p-body, a second
high energy boron ion implantation through the body contact hole is carried out, as
shown in Figure 2.10. This implant is in the body region and we did not observe channel
length change with and without the second boron implantation. The breakdown location
is verified by Medici simulation.
Finally, a deep body source contact [7] was formed by shallow trenched Si etch and
p+ boron implantation. This can greatly reduce contact resistance, as indicated in Figure
2.10. Figure 2.11 clearly indicates that UMOS with high energy boron ion implantation
does not degrade on breakdown voltage.
Figure 2.10 Schematic of p+ (2) boron implantation and deep body source contact formation.
n+ sub
n epi
p-body
n+ n+
p-body
p+
p+(2)
n+ n+
p+(2) p+(2)
0.5um2.0um
1.0um
n+ sub
n epi
p-body
n+ n+
p-body
p+
p+(2)
n+ n+
p+(2) p+(2)
0.5um2.0um
1.0um
0 20 40 60 80
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
I ds(A
)
Vds
(V)
w/o 2nd boron
implantation
with 2nd boron
implantation
Figure 2.11 Measured breakdown I-V curve of trenched LOCOS UMOS with and without p+ (2) boron implantation.
24
2.4.2 Experimental Data
The measured I-V characteristics are as shown in Figure 2.12. The LOCOS UMOS
achieved a breakdown voltage of 60 V and Ron, sp = 85 mΩ·mm2 at Vgs = 3.5 V. At Vgs =
10 V, Ron, sp = 60 mΩ·mm2.
A comparison of the measured electrical characteristics between conventional UMOS
and trenched LOCOS UMOS are presented in Table 2.1.
The SEM photos in Figure 2.13 clearly indicate the increased oxide thickness in shoulder
and bottom regions in trench LOCOS UMOS, and boron segregation effect. The gate
oxide uneven thickness is due to the SEM sample preparation.
1 µm
N+N+ N+
N+ N+ N+P+
P+
P-body
P-body
Po
ly
Poly
LO
CO
S
N-epi
W
W
Conventional LOCOS
1 µm
N+N+ N+
N+ N+ N+P+
P+
P-body
P-body
Po
ly
Poly
LO
CO
S
N-epi
W
W
Conventional LOCOS
Figure 2.13 A SEM cross-sectional indicating boron segregation reduces the
effective channel length.
Figure 2.12 Measured characteristics of trenched LOCOS UMOS.
25
Table 2.1 Electrical characteristics of conventional UMOS and trenched LOCOS
UMOS.
The comparisons of electrical characteristics are listed in Table 2.1. A significant
reduction in Cgs, from 722 pF to 432 pF for the conventional LOCOS and trenched
LOCOS UMOS was observed. The 40% reduction in Cgs is contributed by two factors:
30% Cgs reduction is due to the reduction in channel length. The other 10% Cgs reduction
is due to the increase in the gate oxide thickness at the n+ source. By measuring the
channel length from TSUPREM4 process simulation:
Conventional UMOS gate overlap = L1 + Lsource = 1.5+0.5=2µm,
Trenched LOCOS UMOS gate overlap = L2 + Lsource = 0.9+0.5=1.4µm,
∆Loverlap = 2 −1.4=0.6µm, ∆Cgs = 0.6/2 = 30%.
This phenomenon is due to the high temperature trenched LOCOS process that
caused boron segregation at the oxide and silicon interface. During the high temperature
LOCOS process at 950°C for 100 minutes, Si atoms react with oxygen atoms at the Si-
SiO2 interface. At the same time, the impurities at the interface move easily through the
Device
( Area: 1 mm2 )
Conven-tional UMOS
LOCOS
UMOS
BVdss at Ids=1uA, V 75 73
Vth at Ids=250uA, V 3.4 3.8
Ron, sp at Vgs=10V, Ids=100mA, mΩ·mm2 110 60
Cgs at Vds=0V, pF 722 432
Cgd at Vds=0V, pF 58 69
Cds at Vds=0V, pF 229 278
Qg at Vgs=10V, nC 14.9 11.4
FOM (Ron × Qg), nC·mΩ 1639 684
26
interface, causing boron redistribution and eventually achieving equal chemical potentials
on both sides of the interface [8].
2.4.3 Gate Charge Test
A gate charge test has also been carried out to quantitatively determine the charge
reduction in the trenched LOCOS UMOS. The circuit used for the gate charge test is as
shown in Figure 2.14.
The upper power MOSFET is a commercially available device, used as a current
regulator to set the drain current. The gate source (Vgs) is 10V, and the Vdd is set at 40V.
Phase 1 in Figure 2.15 represents a linear increase in Vgs with gate charge. Qgs defines the
charge needed during turn on. In phase 2, Vgs remains relatively constant, and the drive
current starts to charge the Miller capacitance, Cgd . During phase 3, the gate capacitance
Figure 2.14 The circuit used for gate charge test.
Ig=0.0273mA
27
is the summation of Cgs and Cgd, and the total charge is Qg = Qgs+ Qgd, which is required
to charge the gate to Vgs = 10V.
Under these conditions, the Qgs is 23% lower for the trenched LOCOS UMOS.
Overall, the FOM (Ron × Qg) has been improved by 58% without compromising the
breakdown voltage.
%581639
6841639=
−=
−
alConvention
LOCOSalConvention
FOM
FOMFOM
2.4.4 Unclamped Inductive Switch (UIS) Test
High speed switching would induce a lot of stress on the device which might lead to
device damage. This occurs especially when switching with an inductive load. The rapid
0 2 4 6 8 10 12 14 16
0
2
4
6
8
10
12
14
16
Conventional
LOCOS
∆Qgate
Calibration: 14.8nF
Igs
=C*dV/dt=0.0273mA
Vdd
=40V Ids
=10A Vgs
=10V
Vg
s (V
)
Gate charge (nC)
Figure 2.15 Measured gate charge characteristics of trenched LOCOS UMOS and conventional UMOS.
Phase 1 Phase 2 Phase 3
28
turn off of an inductive load can cause avalanche breakdown of the drain to source diode,
resulting from Vds transients [9]. In order to determine the ruggedness of the new device,
an Unclamped Inductive Switch (UIS) test was carried out for the trenched LOCOS
UMOS.
When the gate voltage is switched off, the inductor current continues to flow through
the circuit due to the collapsing inductive field. This current forces the body diode of the
MOSFET into avalanche breakdown. If the current is too large for the device to handle,
the device will be permanently destroyed. The inductor used for the UIS test in Figure
2.16 is 1mH. From the UIS test results (Figure 2.17), the trenched LOCOS UMOS
process demonstrates ruggedness comparable to conventional UMOS. This is because the
overall process does not involve any doping profile change within the p-body or n-epi
junction. The parasitic BJT inherent in the UMOS remains the same.
Figure 2.16 The circuit used for UIS test.
29
2.5 Summary of Trench LOCOS UMOS
A novel trenched LOCOS UMOS technique has been proposed and experimentally
verified. This technique is simple to carry out and the new device exhibits a 40%
reduction in Cgs, a 45% reduction in Ron,sp, and a 58% improvement in FOM when
compared to the conventional device. The new device shows ruggedness comparable to
the conventional devices without compromising the breakdown voltage.
In order to integrate power MOSFETs with the controller circuits, lateral power
MOSFETs are necessary, which will be discussed in the next chapter.
0 100 200 300 400 500
0
2
4
6
8
10
12
14
LOCOS
Conventional
DUT "ON"
I ds (A
)
Time (µSec)
0
20
40
60
80
100
120
Vds (V
)
Figure 2.17 UIS test results of UMOS devices fabricated by conventional and
trenched LOCOS process.
30
REFERENCES
[1] V. A. K. Temple and P. V. Gray, Theoretical comparison of DMOS and VMOS
structures for voltage and on-resistance, IEEE Int. Electron Device Meeting Digest,
pp.88-92, Abstract. 4.5, 1979.
[2] S.C. Sun and J.D. Plummer, Modeling the on-resistance of LDMOS, VDMOS, and
VMOS power transistors, IEEE Trans, Electron Devices, Vol. ED-27, pp. 356-367,
1980.
[3] T. Syau, P. Venkatraman, and B.J. Baliga, Comparison of ultra-low specific on-
resistance UMOSFET structures: The ACCUFET, EXTFET, INVFET, and
conventional UMOSFET’s, IEEE Trans. Electron Devices, Vol. ED-41, pp. 800-
808,1994.
[4] E. S. Ammar and T.J. Rogers, UMOS Transistors on (110) Silicon, IEEE Trans. On
Electron Devices, Vol. ED-27, no. 5, pp. 907-914, 1980.
[5] H.Takaya, K. Miyaki, and A. Kurayanagi, et. al., Floating Island and Thick Bottom
Oxide Trench Gate MOSFET (FITMOS) – A 60V Ultra low On-resistance Novel
MOSFET with Superior Internal Body Diode, Proc. ISPSD, pp. 1-5, 2005.
[6] R.B. Marcus and T.T.Sheng, The Oxidation of Shaped Silicon Surfaces,
J.Electrochem. Soc., Vol.129, No.6, pp. 1278-1282, 1982.
[7] S. S. Kim, J. K. Oh and M. K. Han, A New Trenched Source Power MOSFET
Improving Avalanche Energy, Jpn. J. Appl. Phys., Vol. 42, pp. 2156-2158, 2003.
[8] Hao Wang, H.P.E Xu, Wai Tung Ng, K. Fukumoto, A. Ishikawa, Y. Furukawa, H
Imai, T. Naito, N. Sato, K. Sakai, S. Tamura, K. Takasuka, Observation and
Utilization of Boron Segregation in Trench MOS to Improve Figure-of-Merit (FOM)
IEEE Electron Device Letters, v 29, n 11, pp. 1239-1241, Nov. 2008.
[9] J.P.Phipps and K. Gauen, New Insights Affect Power MOSFET Ruggedness,
Conference Porceeding of Applied Power Electronics Conference and Exposition, pp.
290-298, 1988.
31
Chapter 3 Lateral Power MOSFET
Integrated devices are necessary for applications such as LCD drivers, which require
low specific on-resistance in order to minimize power loss and with the ability to support
high breakdown voltages [1][2]. The target voltages for the devices designed in this thesis
are 18V and 30V, which can be used for medium and large-size LCD drivers,
respectively. The gates of these devices are usually driven directly by logic level inputs.
3.1 Introduction
The extended drain MOS transistor (EDMOS) is one of the most popular high-
voltage structures used to implement smart PIC at this voltage range. The EDMOS
structure is adopted in this work because it is fully compatible with the standard CMOS
process and it can be integrated with other circuits, such as controller circuits.
p+ n+
HV Pwell
P substrate
Deep Nwell
STI n+STI
Ndrift
DrainSource
Gate
STI
parasitic npn
p+ n+
HV Pwell
P substrate
Deep Nwell
STI n+STI
Ndrift
DrainSource
Gate
STIp+ n+
HV Pwell
P substrate
Deep Nwell
STI n+STI
Ndrift
DrainSource
Gate
STI
parasitic npn
p+ n+
HV Pwell
P substrate
Deep Nwell
STI n+STI
Ndrift
DrainSource
Gate
STI
(c) 30V N-type EDMOS
Figure 3.1(a) Standard NMOS, (b) with shallow Ndrift to support medium
breakdown voltage, (c) with field plate, STI, and deep Ndrift to support high
breakdown voltage.
p+ n+
P substrate
Deep Nwell
Source
Gate
p+ n+
Pwell
Deep Nwell
DrainSource
n+p+ n+
P substrate
Deep Nwell
Source
Gate
p+ n+
Pwell
Deep Nwell
DrainSource
n+
p+ n+
P substrate
Deep Nwell
STI n+
Source
Gate
p+ n+
HV Pwell
P substrate
Deep Nwell
n+Ndrift
DrainSource
p+ n+
P substrate
Deep Nwell
STI n+
Source
Gate
p+ n+
HV Pwell
P substrate
Deep Nwell
n+Ndrift
DrainSource
(a) Standard NMOS (b) 18V N-type EDMOS
Xj
Drift Length
32
For the 18V EDMOS, the Ndrift region can be implemented as a lightly-doped drain
(LDD) without an extra mask (Ndrift mask), see Figure 3.1 (b), by properly controlling
the drift length and junction depth (Xj). The desired breakdown voltage and on-resistance
can be achieved.
The high voltage (>20V) EDMOS device does not use the same mask opening for the
implantation of both the well and source/drain regions. Therefore, the self-aligned MOS
channel is not available and fine lithography is required to define the channel length. By
incorporating the Ndrift region underneath the Shallow Trench Isolation (STI), deeper
junction depth can be achieved, see Figure 3.1 (c). RESURF [3] conditions are utilized to
ensure the trade-off between breakdown voltage and on-resistance. Although standard
CMOS and EDMOS have different fabrication methods, the fundamental operation
principle is the same. The evolution of EDMOS from the standard CMOS is presented in
Figure 3.1 and the details of the process flow are presented in Appendix II.
3.2 EDMOS Enhanced Electrical Characteristics Analysis
The design of a modern EDMOS transistor is intricate, as breakdown voltage and
specific on-resistance have to be satisfied to meet the stringent circuit requirements, the
general design concerns are presented in Appendix III. The advanced electrical
characteristics, such as dv/dt capability and safe operating areas, are discussed in this
section.
33
3.2.1 Turn-on and Turn-off Speed
Turn-on time, ton, is the time taken to charge the input gate capacitance of the device
before the drain current can conduct. Similarly, turn-off time, toff, is the time taken to
discharge the gate capacitance before the device can be switched off.
on d ri fvt t t t= + + (3.1)
( ) ln GHd G gs gd
GH th
Vt R C C
V V= +
− (3.2)
( ) ln( )
m GHri G gs gd
m gs th D
g Vt R C C
g V V I= +
− − (3.3)
( )
( / )
DM on G gd
fv
GH th D m
V V R Ct
V V I g
−=
− + (3.4)
dt is the turn-on delay, rit is the rise time, and fvt is the turn-on interval;
The turn-off time,
off s rv fit t t t= + + , (3.5)
( ) ln m GHs G gs gd
m th D
g Vt R C C
g V I= +
+ (3.6)
( )DM on m G gd
rv
D m th
V V g R Ct
I g V
−=
+ (3.7)
( ) ln D m thfi G gs gd
m th
I g Vt R C C
g V
+= + (3.8)
st is the turn-off delay, rvt is the fall time, and
fit is the turn-off interval, it is clear that
small Cgd will result in fast turn-on and turn-off time. All the parameters are referred to
Figure 3.2.
34
MOS turn-on waveform MOS turn-off waveform
Figure 3.2 Power MOSFET turn-on and turn-off waveform
3.2.2 dv/dt Capability
Peak diode recovery is defined as the maximum rate of rise in the drain-source
voltage (Vds) allowed, i.e., dv/dt capability. If this rate is exceeded, the voltage across the
gate-source terminals may become higher than the threshold voltage of the device,
forcing the device into current conduction mode. Under certain conditions a catastrophic
failure may occur. One mechanism of dv/dt induced turn-on through the feedback action
of the gate-drain capacitance, Cgd, can be explained in Figure 3.3.
VGH
VGS
VGH +ID/gfs
VGS(th)
t0
0
t
t0
ID
VDS
td tri tfv
VGH
VGS
VGH +ID/gfs
VGS(th)
t0
0t
ID
t0
VDS ts trv tfi
35
Figure 3.3 Equivalent circuit of power MOSFET
When a voltage ramp appears across the drain and the source terminal of the device, a
current I1 flows through the gate resistance, RG, via the gate-drain capacitance; Cgd. RG is
the total resistance in the circuit and the voltage drop across it is given by:
Vgs = I1RG = RGCgddv
dt (3.9)
If the gate voltage Vgs exceeds the threshold voltage of the device Vth, the device is forced
into conduction.
The dv/dt capability for this mechanism is thus set by:
dv
dt= th
G gd
V
R C (3.10)
It is clear that smaller Cgd will result in higher dv/dt capability, making the power
MOSFET more reliable. This allows the power transistors to be used in a harsh
environment without resulting in the self turning-on phenomenon.
I1
36
3.2.3 REduced SURace Field (RESURF) Analysis
In 1978 Appels and Vaes suggested the reduced surface field (RESURF) concept [3].
The RESURF concept allows a good trade-off between the breakdown voltage and the
on-resistance of lateral devices. It has been shown that a lateral diode with a thin n-type
epitaxial layer on a lightly doped p-substrate can achieve a higher breakdown voltage
than a conventional lateral diode for the same area. The RESURF conditions are
discussed in general in Appendix III. In this section we will discuss the detail equations
regarding the RESURF conditions to quantify the analysis. The basic properties of
RESURF structures are determined by three parameters: the well doping concentration
(Pwell), the N-drift doping concentration (Ndrift), and the N-drift layer thickness (Xj), see
Figure 3.1(b). For the N-drift layer integrated charge Qn = Ndrift×Xj, the vertical space
charge width in the N-drift region extends and interacts with the lateral junction space
charge region, allowing the lateral depletion width to effectively span a larger distance
compared to the case without the presence of the P-well. As a result, the lateral electric
field at the lateral P+/N-drift junction is much reduced when compared to the one-
dimensional diode case. Therefore, higher voltages can be applied [3]-[6]. To achieve
high breakdown voltages in such RESURF structures, it is required that the N-drift region
be fully depleted before the lateral electric field reaches the critical value. Since the
vertical depletion of the N-drift region is supported by a single junction, namely the P-
well /N-drift junction, such a device structure is typically referred to as a single-RESURF.
In such structures, the breakdown voltage performance is critically dependent on the
integrated charge of the N-drift region Qn.
37
At any applied reverse voltage Vapp, the lateral diode (P+/N-drift) breakdown voltage
BV and the vertical junction (P-well/N-drift) depletion extension dN-drift into the N-drift,
are given as:
2
2
s c
drift
EBV
q N
ε ⋅=
⋅ ⋅ (3.11)
2( )
( )
s app well
N drift app
drift well drift
V Pd V
q N P N
ε−
⋅ ⋅ ⋅=
⋅ ⋅ + (3.12)
sε is the dielectric constant of silicon, cE is the silicon critical field ( ≅ 3×105V/cm), and
q is the electronic charge. For such a structure, and as a requirement to achieve the
benefit from RESURF, the vertical full depletion of the N-drift region has to take place
before the lateral diode breaks down. Therefore, to ensure full vertical depletion of the N-
drift, it is required that:
( )N drift jd BV X−
≥ (3.13)
Where ( )N driftd BV−
is the vertical depletion extension into the N-drift at BV. As a result,
in single-RESURF devices, the optimal N-drift integrated charge Q = Ndrift×Xj, is given
by:
122 10 well
well drift
PQ
P N< ×
+ (3.14)
When processing and forming doped regions in IC technologies, and in order to have
reasonable control over the thickness and doping concentrations of these regions, it is
essential that the doping concentration of the N-drift region be higher than that of the P-
well. An upper theoretical bound for Q can be obtained by setting Ndrift = Pwell, and is
38
given by Qmax = 1.4×1012
atoms/cm2. Possible Ndrift and Xj ranges are presented in Table
3.1 while satisfying the RESURF conditions.
The on-resistance of the EDMOS is dominated by the drift region resistance given by
drift
n
n
LR
q Qwµ= (3.15)
where driftL is the drift region length, nµ is the electron mobility, w is the channel width,
and Q is the drift region charge [7]. The drift region charge, integrated vertically down
from the surface, is approximately 1.4×1012 atoms/cm2. Typical sheet resistance is about
3.5kΩ/sq for n-type EDMOS. One unique property of the lateral EDMOS is that the drift
region charge remains almost constant as the breakdown voltage is increased. Therefore,
as the breakdown voltage of the device is increased, the on-resistance varies
approximately as a function of the drift region length.
2
,on sp sh driftR R L= ⋅ (3.16)
Meanwhile, the desired breakdown voltage can then be determined from device layout
through the proper choice of the lateral drift distance driftL (see Fig. 3.1),
lat driftBV E L= ⋅ (3.17)
latE =10 to15V/µm [6], driftL is the length of the drift region.
Table 3.1 RESURF condition Nd and junction depth
RESURF condition Q=1.4×1012
(cm-2
)
Drift Doping(cm-3
) Junction Depth(µm)
Nd=1×1018
Xj=0.014
Nd=1×1017
Xj=0.14
Nd=1×1016
Xj=1.4
39
The following steps are taken in order to design 70V EDMOS, assume latE =12V/µm
for instance:
Step1: the drift length = 70V/ 12V/µm = 5.8 µm.
Step2: if the N-drift region doping is 5×1016cm-3, the drift layer thickness Xj = Q/Nd =
1.4×1012
/5×1016
= 0.28µm.
Step3: for the P-well doping with 5×1015
cm-3
and Vds = 70V, the maximum
depletion length dN-drift(Vapp) can be calculated using equation (3.12), which
equals 0.41µm. Therefore, the channel length should be larger than 0.41µm,
Lchannel>0.41µm, (set 0.45 µm).
Therefore, the drift length is 5.8 µm, the drift thickness is 0.28 µm, and the channel
length is 0.45 µm.
3.2.4 Safe Operating Area Analysis
The safe operating area defines the limits of operation for the device. It is well known
that the maximum current at low drain voltages is limited by the power dissipation,
assuming that the metal interconnects are sufficiently rated to prevent fusing. Under the
simultaneous application of high current and voltage, the device may be susceptible to
destructive failure even if the duration of the transient is small enough to prevent
excessive power dissipation. This failure mode has been referred to as secondary
breakdown.
p+ n+
HV Pwell
P substrate
Deep Nwell
STI n+STI
Ndrift
DrainSource
Gate
STI
parasitic npn
p+ n+
HV Pwell
P substrate
Deep Nwell
STI n+STI
Ndrift
DrainSource
Gate
STI
parasitic npn
P-base
Figure 3.4 Parasitic npn BJT of EDMOS
40
The term secondary breakdown refers to a sudden reduction in the blocking voltage
capability when the drain current increases. This phenomenon has been observed in
power MOSFETs. It originates from the presence of the parasitic bipolar transistor in the
device structure, as shown in Figure 3.4. When the drain voltage is increased to near the
avalanche breakdown voltage, current flows into the P-base region, in addition to the
normal current flow within the channel inversion layer. The avalanche current collected
within the P-base region flows laterally along the P-base region to its contact. The
voltage drop along the P-base region forward biases the edge of the region. When the
forward bias on the emitter closes to 0.7V, it begins to inject carriers. The parasitic
bipolar transistor is no longer capable of supporting the P-base/Ndrift layer breakdown
voltage (BVCBO). Its breakdown voltage is instead reduced to BVCEO, which is typically
60 percent of BVCBO.
During the secondary breakdown, the parasitic npn BJT is turned on, and the collector
current becomes
c E T EI MIγ α= (3.18)
where Eγ is the injection efficiency, Tα is the base transport factor and M is the
avalanche multiplication factor. The first two parameters can be assumed to be equal to
unity for a typical power MOSFET structure, because we assume the emitter doping
concentration is much higher than the base and the base width is small compared with the
minority diffusion length . The emitter current is:
exp( / )E BI I qV kTο= (3.19)
41
Iο is the reverse saturation current, and BV is the forward bias caused by the lateral base
current BI . The voltage drop due to the lateral base current flow is determined by the
base resistance, BR ,
B B BV R I= .
Combining these equations gives:
exp[ ( 1) ]BE E
qRI I M I
kTο
= − (3.20)
Using the Taylor series expansion and taking the first two terms, we obtain
1 ( 1)E
B
II
qRM I
kT
ο
ο
=
± −
(3.21)
Measurements of carrier multiplication M in junctions near breakdown lead to an
empirical relation:
1
1 ( / )n
br
MV V
=−
(3.22)
where n depends on the material and the doping concentration, usually for Si n is 4. As
the drain voltage increases, the emitter current and the source current can rise
catastrophically (Figure 3.5) in accordance with Equation (3.21). The snapback voltage at
which this will occur can be obtained from the above equations:
1/(1 / )
brSB n
B
VV
qR I kTο
=+
(3.23)
An increase of the safe operating area is possible with the reduction of base resistance
BR and base current BI . It is very important that the transistor be operated in a range such
that IV does not exceed the maximum power rating of the device. In devices designed for
high power capability, the transistor is mounted on an efficient heat sink, so that thermal
energy can be extracted from the junction.
42
Figure 3.5 Snapback phenomenon of EDMOS
negative resistance
Vds (V)
Ids (A)
43
3.3 Simulation Results
In this section, the simulated performance of 18V and 30V EDMOS are presented.
The impacts of the major processing parameters on the device performances are
simulated and optimization conditions are also discussed. The key ion implantation
conditions are illustrated in Table 3.2(a) and (b), respectively.
Table 3.2(a) 18V NMOS key ion implantation conditions
Process Mask Dopant Dose(/cm2) Energy(keV)
Deep Nwell Deep Nwell Phos. 1.00E+13 2300
HVPW HVPW Boron 1.30E+13 500
ND(Vth adjust) ND BF2 1.00E+12 60
Ndrift1(HNM1) Open Phos. 5.00E+12 40
Ndrift2 (HNM2) Open Phos. 3.50E+12 150
Table 3.2(b) 18V PMOS key ion implantation conditions
Process Mask Dopant Dose(/cm2) Energy(keV)
HVNW HVNW Phos. 2.00E+12 700
PD(Vth adjust) PD Phos. 2.00E+12 40
Pdrift1(HPM1) Open BF2 3.00E+12 20
Pdrift2(HPM2) Open Boron 5.00E+12 40
The design parameters of 18V N-type and P-type EDMOS are summarized in Table
3.3.
Table 3.3 Summarized design parameters for EDMOS transistors.
EDMOS Drift Length(µm) Channel Length(µm) Gox(Å)
N-type 0.7 0.5 125
P-type 0.7 0.6 125
The performance of the power device in this work is shown to be comparable to the
previously published results which used a more complex fabrication process. All
44
processes involved have been fully developed based on a 0.18µm CMOS process, which
can be cost-effective and feasible for mass production.
3.3.1 Simulation Results of 18V EDMOS
For a small panel LCD driver, 18V EDMOS is required. In order to minimize the cost,
the drift region mask is eliminated by using the poly gate as the mask. Therefore, the
source and drain will be self-aligned with the gate. But without the Ndrift mask, the
maximum Ndrift junction depth that can be reached is 0.2µm. For high energy Ndrift ion
implantation, phosphorus can penetrate the gate results in punch-through breakdown, as
shown in Figure 3.6. Therefore, in the 18V EDMOS, the junction depth is limited to
0.2µm.
p+ n+
P substrate
Deep Nwell
STI n+
Source
Gate
p+ n+
HV Pwell
P substrate
Deep Nwell
n+Ndrift
DrainSource
p+ n+
P substrate
Deep Nwell
STI n+
Source
Gate
p+ n+
HV Pwell
P substrate
Deep Nwell
n+Ndrift
DrainSource
Figure 3.6 Phosphorus penetration of gate
HNM1
HNM2
45
3.3.1.1 Device Structure and Doping Profiles
The device structures are generated using TSUPREM4 and then imported to MEDICI
for electrical simulation. The 2D device structures of 18V n-type and p-type EDMOS
devices are illustrated in Figure 3.7 (a) and (b), respectively.
The resulting doping profile is illustrated in Figures 3.8(a) and 3.8(b). The Ndrift has
a surface phosphorus concentration of 2×1017
cm-3, and the Pdrift has a surface boron
concentration of 5×1017
cm-3. These doping concentrations are based on numerous
computer simulations, optimized to achieve best trade-off between on-resistance and
breakdown voltage.
(b)P-type EDMOS.
Figure 3.7 Device structures of 18V EDMOS.
Source Gate
Drain
Ndrift
p body
N sub
Source Gate Drain
n body
Pdrift
P sub
(a)N-type EDMOS
46
Figure 3.8(a) Doping concentration across the Ndrift region for the n-type EDMOS.
Figure 3.8(b) Doping concentration across the Pdrift region for the p-type EDMOS.
1E+12
1E+13
1E+14
1E+15
1E+16
1E+17
1E+18
0 1 2 3 4 5 6
Distance (µm)
Dopin
g C
once
ntr
atio
n (
/cm
3)
Phos
Boron
1E+12
1E+13
1E+14
1E+15
1E+16
1E+17
1E+18
0 1 2 3 4
Distance (µm)
Dopin
g C
once
ntr
atio
n (
/cm
3)
Boron
Phos
Phos
Boron
Phos
Boron
47
3.3.1.2 Breakdown Voltage
The breakdown voltage of the devices is simulated using MEDICI. With the gate
turned off, the drain voltage is ramped up until breakdown occurs. Figure 3.9(a) and
Figure 3.9(b) show the potential contours of the n-type and the p-type EDMOS devices
under breakdown conditions, respectively.
(a)
(b)
(a) N-type EDMOS. (b) P-type EDMOS.
Figure 3.9 Simulated device breakdown potential characteristics.
As illustrated in Figure 3.9, the drift regions of the devices are totally depleted.
Therefore, the drift regions are fully utilized to support the breakdown voltage. The
breakdown of the complementary EDMOS occurs at the bottom of the drift region
Vg=Vs=0V
Vds=30V
Vsub=0
1V/line
Source Gate Drain
Source Gate
Drain
Vg=Vs=0V
Vds= −30V
Vsub= −30V
1V/line
48
instead of at the surface, as indicated in Figure 3.9. Also, punch through of the channel
does not occur in this design. The breakdown characteristics are as plotted in Figure 3.10,
BV = 26V for n-type EDMOS, and −25V for p-type EDMOS with limit current set at
1µA.
(a) N-type EDMOS.
(b) P-type EDMOS.
Figure 3.10 Breakdown IV characteristics.
0.0E+0
5.0E-6
1.0E-5
1.5E-5
2.0E-5
2.5E-5
0 5 10 15 20 25 30
Vds (V)
Ids (
A/u
m)
-1.4E-6
-1.2E-6
-1.0E-6
-8.0E-7
-6.0E-7
-4.0E-7
-2.0E-7
0.0E+0
-30 -25 -20 -15 -10 -5 0
Vds (V)
Ids (
A/u
m)
49
3.3.1.3 NMOS Drift Dose Variation
The Ndrift dose is one of the key parameters that control the breakdown of the
EDMOS. In order to investigate this effect, process and device simulations were carried
out for different Ndrift doses. It was found that the second ion implantation, HNM2, used
to form the Ndrift region influenced the breakdown voltage as well as the breakdown
location.
Figure 3.11 Breakdown dependence with Ndrift dose
If the HNM2 dose is lower than 3.5×1012
cm-2, charge balance between Ndrift region and
Pbody is not achieved, and breakdown voltage is lower than the ideal case. If the HNM2
dose is higher than 3.5×1012
cm-2, too much phosphorus will be distributed at the surface
and the electrical field crowing at the surface will occur. This will degrade the breakdown
voltage. However, on-resistance will decrease monotonically with an increasing HNM2
dose, as high doping concentration in the drift region will reduce on-resistance. In order
Breakdown Characteristics
21
22
23
24
25
26
0 1E+12 2E+12 3E+12 4E+12 5E+12 6E+12
HNM 2 Dose (cm-2) @ 150 Kev
Bre
akd
ow
n V
olt
age (
V)
50
to achieve the best trade-off between breakdown voltage and on-resistance, HNM2 =
3.5×1012
cm-2 is selected.
Figure 3.12 Specific on-resistance dependence with Ndrift dose.
3.3.1.4 PMOS Drift Dose Variation
Similar to n-type EDMOS, too much boron ion implantation at the Pdrift region,
namely HPM2, will decrease the breakdown voltage. The best choice for the HPM2 dose
is 5×1012
cm-2.
Figure 3.13 Breakdown dependence with Pdrift dose.
Breakdown Characteristics
19
19.5
20
20.5
21
21.5
22
22.5
23
23.5
2E+12 3E+12 4E+12 5E+12 6E+12 7E+12 8E+12
HPM2 Dose (cm-2
) @ 40 kev
Bre
akd
ow
n V
olt
ag
e (
V)
0
2
4
6
8
10
12
14
16
18
20
0 1E+12 2E+12 3E+12 4E+12 5E+12 6E+12
HNM 2 Dose (cm -2) @ 150 KeV
Ro
n (
mO
hm
, m
m2)
51
3.3.1.5 Threshold Voltage and IV Curves
The threshold voltage is extracted by setting the drain voltage to 0.1V and then the
gate voltage is ramped up until a conduction current is observed. The threshold voltage is
taken as the x-intercept on the Ids-Vgs graph. Figure 3.15 shows the threshold voltage for
the n-type EDMOS device Vth=1.6V and Figure 3.16 shows the threshold voltage for the
p-type EDMOS device, Vth= −1.7V.
Figure 3.14 Specific on-resistance with Pdrift dose.
Figure 3.15 Threshold voltage of N-type EDMOS
0.0E+00
2.0E-06
4.0E-06
6.0E-06
8.0E-06
1.0E-05
1.2E-05
1.4E-05
1.6E-05
0 1 2 3 4 5 6
Vgs(V)
Id(A
/um
)
0
5
10
15
20
25
30
2E+12 3E+12 4E+12 5E+12 6E+12 7E+12 8E+12
HPM2 Dose (cm-2
) @ 40 kev
Ro
n,
sp
(m
Oh
m,
mm
2)
52
The IV curves of the n-type and p-type EDMOS devices were simulated with
different gate voltages and are illustrated in Figure 3.17 and Figure 3.18, respectively.
The on-resistance can be extracted from the IV curve. The usual gate drive voltage of the
device is 10V. The on-resistance is the inverse of the slope of the IV curves in the triode
region with Vgs=10V. The corresponding specific on-resistance is 11 mΩ·mm2 for the
n-type device and 22 mΩ·mm2 for the p-type device.
Figure 3.16 Threshold voltage of P-type EDMOS
-7E-06
-6E-06
-5E-06
-4E-06
-3E-06
-2E-06
-1E-06
0E+00
-6 -5 -4 -3 -2 -1 0
Vgs(V)
Id(A
/um
)
0E+00
1E-04
2E-04
3E-04
4E-04
5E-04
6E-04
0 2 4 6 8 10Vds (V)
Ids (
A/u
m)
Figure 3.17 IV characteristics of N-type EDMOS.
Vgs=2V
Vgs=4V
Vgs=8V
Vgs=10V Vgs=12V
Vgs=6V
53
The simulated results of 30V devices are summarized in Table 3.4.
Table 3.4 Simulated results of 18V EDMOS
Simulation 18V NMOS 18V PMOS
BV (V) 26 -25
Ron,sp (mΩ-mm2) 11 22
Vth (V) 1.6 -1.7
-4E-04
-3E-04
-3E-04
-2E-04
-2E-04
-1E-04
-5E-05
0E+00
-12 -10 -8 -6 -4 -2 0
Vds (V)
Ids (
A/u
m)
Figure 3.18 IV characteristics of P-type EDMOS.
Vgs=−2V
Vgs=−4V
Vgs=−6V
Vgs=−8V
Vgs=−10V
Vgs=−12V
54
3.3.2 Simulation Results of 30V EMOS
For a medium-sized LCD driver, 30V rating EDMOS is necessary. In order to relax
the electrical field close to the gate region and improve breakdown voltage, a field plate
is necessary. With the addition of a drift region mask, the gate can make an overlap with
the drift region to be served as the field plate.
The key ion implantation conditions are illustrated in Tables 3.5(a) and (b),
respectively.
Table 3.5(a) 30V NMOS key ion implantation conditions
Process Mask Dopant Dose(/cm2) Energy(keV)
Deep Nwell Deep Nwell Phos 1.00E+13 2300
P-Buffer Boron 1.50E+13 1150
HVPW HVPW Boron 5.80E+12 200
Nsink1 Phos 1.00E+13 1550
Nsink2 Phos 1.00E+13 800
Nsink Nsink Phos 1.00E+12 300
ND(Vth adjust) ND BF2 1.65E+12 60
N-drift1 Phos 3.50E+12 680
N-drift2 Phos 2.50E+12 400
N-drift3 Phos 2.00E+12 250
N-drift4 Phos 2.50E+12 120
N-drift5 N-drift Phos 3.00E+12 60
55
Table 3.5(b) 30V PMOS key ion implantation conditions
Process Mask Dopant Dose(/cm2) Energy(keV)
Deep Nwell Deep Nwell Phos 1.00E+13 2300
P-Buffer Boron 1.50E+13 1150
HVPW HVPW Boron 5.80E+12 200
NW Phos 2.00E+13 360
BN NW Phos 1.50E+12 100
PD(Vth adjust) PD Phos 8.70E+11 40
P-drift1 Boron 1.50E+12 200
P-drift2 Boron 3.00E+12 120
P-drift3 P-drift BF2 5.00E+12 60
The design parameters of 30V N-type and P-type EDMOS are summarized in Table
3.6.
Table 3.6 Summarized design parameters for EDMOS transistors.
EDMOS Drift Length(µm) Channel Length(µm) Gox(Å)
N-type 2 0.9 125
P-type 1.9 0.4 125
56
3.3.2.1 Device Structure and Doping Profiles
The 2D device structures of 30V n-type and p-type EDMOS devices are illustrated in
Figure 3.19 (a) and (b), respectively.
(a) N-type EDMOS (b) P-type EDMOS
Figure 3.19 Device structures of 30V EDMOS.
The resulting doping profile is illustrated in Figure 3.20(a) and 3.20(b). The Ndrift
has a phosphorus concentration of 1×1017
cm-3, and Pdrift has a boron concentration of
Gate
STI Pdrift
Drain Source
NISO
HV NWell
P sub
Gate
57
5×1017
cm-3. These doping concentrations are based on numerous computer simulation
optimizations to achieve best trade-off between on-resistance and breakdown voltage.
Figure 3.20 (a) Doping concentration across N-type EDMOS drain region.
1E+12
1E+13
1E+14
1E+15
1E+16
1E+17
1E+18
1E+19
1E+20
1E+21
0 1 2 3 4 5 6 7 8
Distance (µm)
Do
pin
g C
on
cen
tra
tion
(/c
m3
)
Boron
Phos
As
Phos
Boron
As
Figure 3.20 (b) Doping concentration across P-type EDMOS drain region.
1E+12
1E+13
1E+14
1E+15
1E+16
1E+17
1E+18
1E+19
1E+20
1E+21
0 1 2 3 4 5 6 7 8
Distance (µm)
Do
pin
g C
on
cen
tra
tion
(/c
m3)
Boron
Phos
Phos
Boron
58
3.3.2.2 Breakdown Voltage
The breakdown voltage of n-type EDMOS, and p-type EDMOS are simulated. The
current limit is set to 1µA. As shown in Figure 3.21, the breakdown voltage is 35V for
n-type EDMOS, and -35V for p-type EDMOS, respectively.
(a) N-type EDMOS
(b) P-type EDMOS
0E+00
2E-13
4E-13
6E-13
8E-13
1E-12
1E-12
0 5 10 15 20 25 30 35 40
Vds (V)
Ids (
A/u
m)
-2.5E-13
-2.0E-13
-1.5E-13
-1.0E-13
-5.0E-14
0.0E+00
-40 -35 -30 -25 -20 -15 -10 -5 0
Vds (V)
Ids (
A/u
m)
Figure 3.21 Breakdown IV characteristics.
59
3.3.2.3 Threshold Voltage and IV curves
The threshold voltage is 0.7V for n-type, and −1.2V for p-type EDMOS as
extrapolated from Figure 3.22 and 3.24, respectively.
0.0E+00
5.0E-05
1.0E-04
1.5E-04
2.0E-04
2.5E-04
3.0E-04
3.5E-04
4.0E-04
0 2 4 6 8 10 12 14 16
Vds(V)
Id(A
/um
)
Vgs=3V
Vgs=4V
Vgs=5V
Vgs=10V
Figure 3.23 IV characteristics of N-type EDMOS.
0E+00
1E-06
2E-06
3E-06
4E-06
5E-06
6E-06
7E-06
8E-06
0 0.5 1 1.5 2 2.5 3 3.5
Vgs(V)
Id(A
/um
)
Figure 3.22 Threshold voltage of N-type EDMOS
60
The pecific on-resistance is 42mΩ-mm2 for a n-type EDMOS, and 52mΩ-mm
2 for a
p-type EDMOS at Vgs=10V, respectively. The current increment from Vg=5V to 10V is
smaller than the current increment from Vg=3V to 4V. This is because the drift region
resistance is dominant. The increase in gate voltage cannot further increase the drain
current.
-4.5E-04
-4.0E-04
-3.5E-04
-3.0E-04
-2.5E-04
-2.0E-04
-1.5E-04
-1.0E-04
-5.0E-05
0.0E+00
-35 -30 -25 -20 -15 -10 -5 0Vds(V)
Id(A
/um
)
Vgs=−3V
Vgs=−4V
Vgs=−5V
Vgs=−10V
Figure 3.24 Threshold voltage of P-type EDMOS
Figure 3.25 IV characteristics of P-type EDMOS
-5.0E-06
-4.5E-06
-4.0E-06
-3.5E-06
-3.0E-06
-2.5E-06
-2.0E-06
-1.5E-06
-1.0E-06
-5.0E-07
0.0E+00
-5.5 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0Vgs(V)
Id(A
/um
)
61
The simulated results of 30V devices are summarized in Table 3.7.
Table 3.7 Summarized simulated results
Simulation 30V NMOS 30V PMOS
BV (V) 35 -35
Ron,sp (mΩ-mm2) 42 52
Vth (V) 0.7 -1.2
62
3.3.2.4 NMOS Geometry Variation
In order to minimize the on-resistance, the optimization of the device parameters A, B,
C and D are carried out, as shown in Figure 3.26.
Figure 3.26 (a) N-type EDMOS dimensions.
20
25
30
35
40
45
50
1 1.1 1.2 1.3 1.4 1.5 1.6
A(µm)
Ro
n,s
p(m
Oh
m,m
m2)
Vgs=10V
Figure 3.26 (b) Specific on-resistance dependence with parameter A (B=0.4µm)
P+ N+
PWell
Psub
Deep Nwell (NISO)
STI STI STI N+
NW
Nsink
N+ STI
Ndrift
A
B C
D
63
Figure 3.26(c) Specific on-resistance dependence with parameter B (A=1.3µm)
Increasing dimension A will increase the channel length such that the specific
on-resistance will increase, as shown in Figure 3.26(b). Dimension B determines the
current path width. A large B dimension will reduce the specific on-resistance, as shown
in Figure 3.26(c), but a large B dimension will also increase the risk of punch-through
breakdown. These geometries are optimized via computer simulations. A = 1.3µm,
B=0.4µm are eventually chosen.
0
10
20
30
40
50
60
0.3 0.4 0.5 0.6 0.7 0.8 0.9
B(µm)
Ro
n,s
p(m
Oh
m,m
m2
)
Vgs=10V
64
3.3.2.5 PMOS Geometry Variation
Similar to n-type EDMOS, in order to minimize the on-resistance, the optimization of
the device parameters A, B, C and D are carried out, as shown in Figure 3.27.
Figure 3.27 (a) P-type EDMOS dimensions
N+ P+ P+ STI STI STI STI
Pdrift
P+
D
B C
A
0
10
20
30
40
50
60
70
80
0.5 0.6 0.7 0.8 0.9 1 1.1
A(µm)
Ro
n,s
p(m
Oh
m,m
m2)
Figure 3.27 (b) Specific on-resistance dependence with parameter A (B=0.3µm)
Vgs= −10V
PW
Deep Nwell (NISO)
NW
Psub
65
Similar to n-type EDMOS analysis, A = 0.7µm and B = 0.3µm are chosen for p-type
EDMOS.
0
10
20
30
40
50
60
70
0.2 0.3 0.4 0.5 0.6 0.7
B(µm)
Ro
n, sp
(mO
hm
, m
m2)
Figure 3.27(c) Specific on-resistance dependence with parameter B (A = 0.7µm)
Vgs= −10V
66
3.4 A Floating RESURF EDMOS with Enhanced Safe Operating Area
Besides breakdown voltage and specific on-resistance, high voltage and high current
stress often occur in these switching circuits. Therefore, it is necessary to improve the
device’s safe operating area (SOA) [8].
3.4.1 Methods to Improve SOA
In order to suppress the parasitic NPN bipolar transistor inside of the EDMOS and
improve the safe operating area, three methods are introduced.
3.4.1.1 Base Resistance Reduction
Due to the parasitic bipolar transistor inherent in the EDMOS, the “snapback”
phenomenon will occur if the device is operating under high Vgs and high Vds conditions.
This is often referred to as the onset of the secondary breakdown in EDMOS. In this case,
the EDMOS will exhibit negative resistance and low impedance with no gate control.
Figure 3.28 Device structure of a conventional EDMOS transistor showing the
parasitic NPN and the base resistance.
In order to suppress the parasitic NPN bipolar transistor from turning on, a p-buried
p+ n+
HV Pwell
P substrate
Deep Nwell
STI n+STI
Ndrift
DrainSource
Gate
STI
parasitic npn
p+ n+
HV Pwell
P substrate
Deep Nwell
STI n+STI
Ndrift
DrainSource
Gate
STI
parasitic npn
67
layer underneath the source is necessary to reduce the base resistance [9]. Figure 3.28 and
3.29 illustrate the structural difference between a conventional EDMOS and an EDMOS
with a p-buried layer.
Figure 3.29 EDMOS transistor with p-buried layer to suppress the turn-on of the
emitter-base junction.
3.4.1.2 Base Current Reduction
Under high Vds conditions, electron impact ionization could generate a large amount
of hole current, which could become the base current. This base current increases
exponentially with Vgs. If the voltage drops across the HV Pwell and the n+ source region
exceeds 0.7V, the parasitic BJT will turn on and a snapback in the IV characteristics will
occur.
p+ n+
HV Pwell
P substrate
Deep Nwell
STI n+STI
Ndrift
DrainSource
P buried layer
Gate
STIp+ n+
HV Pwell
P substrate
Deep Nwell
STI n+STI
Ndrift
DrainSource
P buried layer
Gate
STI
p+ n+
HV Pwell
P substrate
Deep Nwell
STI n+STI
Ndrift
DrainSource
P buried layer
Gate
STI
holes
Phosphorus Implant
p+ n+
HV Pwell
P substrate
Deep Nwell
STI n+STI
Ndrift
DrainSource
P buried layer
Gate
STI
holes
Phosphorus Implant
Base current
Figure 3.30 Phosphorus implantation is used in the drain region to suppress hole current.
68
In order to improve the SOA, it is necessary to suppress this hole current [10]. By
introducing a proper amount of n-type dopants near the drain region, see Figure 3.30, the
hole current can be significantly reduced. Figures 3.31(a) and 3.31(b) are the comparison
of the hole current between conventional EDMOS and the proposed EDMOS. By using
TCAD simulations, we could estimate that the hole current inside of the proposed EDMOS
is suppressed by approximately 100 times. In conventional EDMOS, the holes are
generated near the drain region as shown inside the circle. These holes will be collected by
the source and cause a base voltage drop in the parasitic NPN transistor. In the proposed
EDMOS, with the extra phosphorus implantation, the hole-induced base voltage drop in
the parasitic NPN transistor is significantly reduced, as shown in Figures 3.31(a) and (b).
Figure 3.31 (a) Hole current vectors in
conventional EDMOS
Figure 3.31 (b) Hole current vectors in
Proposed EDMOS
Vgs=5V
Vds=18V
69
3.4.1.3 Floating RESURF
In conventional EDMOS structures, breakdown normally occurs at the Ndrift and HV
Pwell junction. However, by adjusting the HV Pwell, the deep Nwell dose and the
implantation energy, the HV Pwell underneath the Ndrift region can be designed to be
totally depleted as well. Since the deep NWell is floating, this technique is referred to as
floating RESURF [11]. In this case, the expanded depletion region will be able to support a
larger breakdown voltage. The potential contours are illustrated in Figure 3.32.
(b)
(a) (b)
VG=VS=0V VDS=50V
Vsub=0V
Deep NWell
Source Gate Drain
5V/line
P substrate
HV
Pwell
VG=VS=0V VDS=30V
Vsub=0V 5V/line
P substrate
Source Gate Drain
Deep NWell
HV Pwell
P buried layer
Figure 3.32 Potential contours comparison between (a) the conventional EDMOS and
(b) the proposed EDMOS.
70
3.4.2 Simulation Results
The operation of the proposed floating RESURE EDMOS were discussed in the
previous section. The simulated results for the floating RESURF EDMOS are presented
in this section.
3.4.2.1 Breakdown Characteristics
A plot of the simulated breakdown characteristics for the conventional EDMOS and
the proposed EDMOS are presented in Figure 3.33. With the Ndrift and HV Pwell regions
completely depleted, the potential drop is spreaded over a larger area and into the deep
Nwell. This significantly reduces the peak electrical field strength at the Ndrift/HV Pwell
junction, allowing the proposed EDMOS to achieve much higher breakdown voltage when
compared to the conventional EDMOS. The proposed EDMOS has a breakdown voltage of
62V with Ron,sp = 36.5mΩ·mm2, and these electrical characteristics are comparable to one
of the best reported results in high-side devices [11].
1E-14
1E-12
1E-10
1E-8
1E-6
1E-4
0 10 20 30 40 50 60 70
Vds (V)
Ids (
A/µ
m)
Conventional
EDMOS
Proposed
EDMOS
Figure 3.33 Comparison of the breakdown voltages between the
conventional and the proposed EDMOS transistors.
71
3.4.2.2 IV Characteristics
The Ids versus Vds characteristics of the EDMOS transistors with and without a p-buried
layer are as plotted in Figure 3.34. By incorporating the p-buried layer in the source region
of the EDMOS structure, the base resistance is reduced and helps to suppress the turn-on of
the parasitic NPN transistor, the snapback voltage increases from 22V to 48V, and the
snapback current increases from 5×10−4
A/µm to 1×10−3
A/µm.
At low Vds, impact ionization is weak and the hole concentration is insignificant. As
Vds increases, impact ionization becomes apparent near the drain region and results in a
large amount of hole current. Normally, this hole current will flow through the source,
causing a voltage drop across the HV Pwell/n+ source region, thus turning on the parasitic
NPN bipolar transistor.
0E+0
1E-3
2E-3
3E-3
0 10 20 30 40 50 60
Vds (V)
Ids
(A
/µm
)
Conventional
EDMOS
VGS = 5V
EDMOS with
p-buried layer
Figure 3.34 Comparison of the IV characteristics between the proposed EDMOS transistor
with p-buried layer and the conventional EDMOS transistor.
72
In order to suppress hole current and avoid voltage drop across the emitter-base
junction (HV Pwell/n+) of the parasitic NPN transistor, extra phosphorus implantation is
introduced to the drain region to cancel the hole current. The amount of phosphorus
introduced can be observed in the drain doping profiles as plotted in Figure 3.35. The
comparison of the IV characteristics between EDMOS transistors with a p-buried layer, a
p-buried layer and phosphorus implant at the drain, and a conventional structure is plotted
in Figure 3.36.
0E+0
1E-3
2E-3
3E-3
0 20 40 60
Vds (V)
Ids (
A/µ
m)
Conventional
EDMOS
with p-buried layer &
phosphorus implant
Vgs = 5V
EDMOS with
p-buried layer
Figure 3.36 Comparison of IV characteristics EDMOS structures with p-buried
layer, p-buried layer and phosphorus implant at the drain, and
conventional structure.
1E+14
1E+15
1E+16
1E+17
1E+18
1E+19
1E+20
0 1 2 3 4 5
Depth (µm)
Co
nc
en
tra
tio
n (
cm
-3)
n+ drain
Phos. 2×1012cm-2, 380KeV
Ndrift
Conventional
EDMOSProsposed
EDMOS
Figure 3.35 Doping profiles at the drain region for the proposed EDMOS transistor with extra
phosphorus implant, and the conventional EDMOS structure.
p+ n+
HV Pwell
P substrate
Deep Nwell
STI n+STI
Ndrift
DrainSource
Gate
STI
parasitic npn
p+ n+
HV Pwell
P substrate
Deep Nwell
STI n+STI
Ndrift
DrainSource
Gate
STIp+ n+
HV Pwell
P substrate
Deep Nwell
STI n+STI
Ndrift
DrainSource
Gate
STI
parasitic npn
p+ n+
HV Pwell
P substrate
Deep Nwell
STI n+STI
Ndrift
DrainSource
Gate
STI
73
The IV characteristics of the EDMOS with a p-buried layer and a phosphorus implant
at the drain for a wide range of Vgs are plotted in Figure 3.37. The IV curves can be
identified to have two regimes, the compression regime and the expansion regime [12]. By
introducing phosphorus implantation near the drain region, the proposed EDMOS
demonstrated a 15% larger SOA in the expansion regime, which is an improvement when
compared to that reported by Hower et al. [9].
0E+0
1E-3
2E-3
3E-3
0 20 40 60
Vds (V)
Ids (
A/µ
m)
Expansion
regime
Vgs from 10 to 3V
Compression
regime
Figure 3.37 Snapback characteristics of the proposed EDMOS.
0E+0
1E-3
2E-3
3E-3
0 20 40 60Vds (V)
Ids (
A/µ
m)
Vgs = 7 to 3V
curves overlap each
other for Vgs > 7V
Compression
regime
Figure 3.38 Snapback characteristics of conventional EDMOS.
74
In contrast with the conventional EDMOS transistor, the IV characteristics, as plotted
in Figure 3.38, show snapback voltages that are much lower when compared to those of the
proposed device (see Figure 3.37). In the conventional EDMOS, the expansion regime is
almost non-existent. This is due to the fact that there is no shunt resistance underneath the
source to reduce the base resistance. Therefore, the parasitic NPN bipolar transistor can be
turned on whenever a moderate amount of drain current is present.
3.4.2.3 Safe Operating Area Characteristics
Safe operating area is defined as the voltage and current conditions over which the
device can be expected to operate without self-damage. The dynamic SOA is for the
0.0E+0
5.0E-4
1.0E-3
1.5E-3
2.0E-3
2.5E-3
10 20 30 40 50 60
Vds(V)
Ids(A
/µm
)
SOA of the
Conventional EDMOS
SOA of the
Proposed EDMOS
Figure 3.39 Comparison of the DC SOA between the conventional EDMOS
transistor and the proposed EDMOS transistor.
75
device under pulsed current and voltage conditions without self-damage. Due to
equipment constrains, only DC SOA is investigated.
The DC SOA for both the conventional EDMOS transistor and the proposed EDMOS
are shown in Figure 3.39. The p-buried layer and the extra phosphorus drain implant were
found to be an effective means to suppress the turning-on of the parasitic transistor,
allowing a much higher snapback voltage. The estimated DC SOA of the proposed
EDMOS is approximately 400% larger when compared to conventional EDMOS.
3.4.3 Summary
An EDMOS transistor with improved breakdown voltage and enhanced SOA is
proposed. The base resistance of the parasitic NPN transistor is reduced and the hole
current that would normally be problematic at high Vgs and high Vds is suppressed. These
two enhancements suppress the turn-on mechanisms for the parasitic NPN transistor.
Therefore, the SOA can be greatly improved. A floating RESURF technique is utilized to
support high breakdown voltage and achieved low on-resistance. Finally, all the processing
steps introduced remain fully compatible with standard CMOS process.
76
3.5 Orthogonal Gate EDMOS
For modern power devices, focusing only on the breakdown and specific
on-resistance relationship is not enough. Since power MOSFETs are widely used as
on-off switches, the Miller capacitance of power MOSFETs determines the overall
switching performance. We propose an EDMOS transistor with a novel orthogonal gate
(OG) electrode designed to provide low Miller capacitance, fast switching speed, low
gate charge and reduced Ron,sp.
3.5.1 Device Concept and Structure
A comparison between a conventional gate EDMOS structure and an orthogonal gate
EDMOS structure is as shown in Figure 3.40. The orthogonal gate EDMOS has both
vertical and lateral control gate. The field plate (FP) extension is necessary in
conventional EDMOS transistors to alleviate the electrical field crowding in the drift
region for a given breakdown voltage.
(a) (b)
Figure 3.40 Device structure for (a) conventional EDMOS, and (b) OG-EDMOS.
p+ n+
HV Pwell
P substrate
Deep Nwell
STI STI STIn+
Ndrift
Gate DrainSourceBody
p+ n+
HV Pwell
P substrate
Deep Nwell
STI STI STIn+
Ndrift
Gate
p+ n+
HV Pwell
P substrate
Deep Nwell
STI STI STIn+
Ndrift
Gate DrainSourceBody
FP Overlap
Connection Region
A
p+ n+
HV Pwell
P substrate
Deep Nwell
STI STI STIn+
Ndrift
Gate
DrainSourceBody A
p+ n+
HV Pwell
P substrate
Deep Nwell
STI STI STIn+
Ndrift
Gate
DrainSourceBody A
p+ n+
HV Pwell
P substrate
Deep Nwell
STI STI STIn+
Ndrift
Gate
DrainSourceBody
0
.35µ
m
0.2µm
Lateral Gate
Vertical Gate
77
The potential distributions in all EDMOS just before breakdown are shown in Figure
3.41. The conventional EDMOS and OG-EDMOS have evenly distributed potential
lines, which illustrates gradually voltage drop along the drift region, and the drift region
is fully utilized to support breakdown voltage. The field plate is an essential part in the
conventional EDMOS, which cannot be eliminated to reduce Miller capacitance.
Vgs=0V
Vds=30V
3V/line
S Gate D
Vgs=0V
Vds=30V
3V/line
D Gate S
(a) (b)
Vgs=0V
Vds=14V
1.5V/line
D Gate S
(c)
Figure 3.41 Potential contours at 3V/line for (a) conventional EDMOS, (b)
orthogonal gate EDMOS transistors, (c) conventional EDMOS
without field plate.
78
Otherwise, the electrical potential lines concentrate at the gate edge and the breakdown
voltage reduces to 14V, as shown in Figure 3.41 (c). This breakdown voltage is
significantly lower when compared to the orthogonal gate EDMOS of the same device
size and Ndrift region design. The cause is due to the connection region in Figure 3.40 (a),
which needs the field plate at the edge of the planar junction to influence the depletion
layer curvature by altering the surface potential. This alleviates the electrical field and
maintains 30V breakdown voltage. Shrinking the connection region width can cause high
on-resistance, as shown in Figure 3.26(c) already. Therefore, it is inevitable to have a
field plate on top of the conventional EDMOS. This results in a large Miller capacitance,
Cgd.
The proposed orthogonal gate structure has a different connection path between the
source and drain as shown in Figure 3.40 (b). In this case, the drift region is in ideal
RESURF condition, which does not need a field plate to maintain the breakdown voltage.
And the vertical gate width is controlled by lithography resolution. For this prototype
OG-EDMOS, the opening is chosen to be 0.2µm in a standard 0.18µm CMOS technology
as shown in Figure 3.40 (b).
3.5.2 Simulation Results
The operation of the proposed orthogonal gate EDMOS was discussed in the previous
section. The simulated results for the orthogonal gate EDMOS are presented in this
section.
79
3.5.2.1 Capacitance Characteristics
The vertical gate significantly reduces the gate-to-drain overlap capacitance (Miller
capacitance), and a 75% reduction in Cgd is observed as illustrated in Figure 3.42. All
other capacitances are also simulated using MEDICI. The gate-to-source capacitance (Cgs)
is smaller than conventional EDMOS, and the drain-to-source capacitance (Cds) is
comparable to conventional EDMOS.
Figure 3.42 Comparison of Cgd, Cgs, and Cds between orthogonal gate and conventional
EDMOS transistors.
0
2E-16
4E-16
6E-16
8E-16
1E-15
1.2E-15
0 5 10 15 20 25 30
Vds (V)
Cg
s
Cap
acit
an
ce (
F/µ
m)
OG-EDMOS
Conventional gate EDMOS
0
3E-16
6E-16
9E-16
1.2E-15
1.5E-15
1.8E-15
0 5 10 15 20 25 30
Vds (V)
Cd
s C
ap
acit
an
ce (
F/µ
m)
Conventional gate
EDMOSOG-EDMOS
0
2E-16
4E-16
6E-16
8E-16
1E-15
1.2E-15
0 5 10 15 20 25 30
Vds (V)
Cg
d
Cap
acit
an
ce (
F/µ
m)
OG-EDMOS
Conventional gate
EDMOS
80
The input capacitance, Ciss = Cgs + Cgd, is the summation of gate-to-source and
gate-to-drain capacitance. Cgs and Cgd are the most relevant intrinsic capacitances which
are responsible for limiting the overall device performance in terms of device-switching
speed. The gate-to-substrate capacitance is much smaller in strong inversion cases [13].
The formation of an inversion layer in the channel region provides an electrostatic shield
between the gate and the substrate, such that total gate charge ceases to respond to the
changes of the substrate bias. Therefore, gate-to-substrate capacitance is often neglected.
By reducing the gate-to-drain (Miller) capacitance, the switching speed can be enhanced
while switching loss can be reduced.
3.5.2.2 Gate Charge Test
The comparison of gate charge (Qg) between the orthogonal gate and conventional
EDMOS transistors is presented in Figure 3.43. Qg specifies the amount of gate charge
required to drive the MOSFET gate-to-source voltage (Vgs) from zero to ten volts. It is
obtained by integrating the gate current as a function of time, Qg=∫Ig·dt. The OG-EDMOS
transistor demonstrates a 37.5% reduction in total Qg at Vgs = 10V. The figure-of-merit
(Ron × Qg) is improved by 53%.
0
5
10
15
0E+00 1E-14 2E-14 3E-14 4E-14 5E-14
Gate Charge (Coul/µm)
Vgate
(V
)
OG-EDMOS
Conventional gate
EDMOS
Figure 3.43 Gate charge characteristics.
81
3.5.2.3 IV Characteristics
IV characteristics of the orthogonal gate EDMOS are presented in Figure 3.44, the
orthogonal gate EDMOS achieved a breakdown voltage of 30V and Ron, sp = 32mΩ·mm2
at Vgs = 10V. At high gate voltage conditions, such as from Vgs=4V to Vgs=5V, the drain
current has smaller increments compared to Vgs=1V toVgs=2V, this is due to the drift
resistance is dominant in the OG-EDMOS. Further increase gate voltage cannot further
increase drain current.
3.5.2.4 Lateral Channel Length Variation
In Figure 3.45, the specific on-resistance for the orthogonal EDMOS transistor is
simulated for various lateral channel lengths, A (see Figure 3.40(b)), while keeping all
other parameters constant. The channel resistance contributed by A is 2mΩ·mm2 per
0.1µm. Since the lateral channel length A does not have a strong influence on the
0E+00
1E-04
2E-04
3E-04
4E-04
5E-04
0 5 10 15 20 25 30 35 40
Vds(V)
Ids
(A/u
m)
Vgs=0V Vgs=1V
Vgs=2V
Vgs=3V
Vgs=4V
Vgs=5V
Figure 3.44 IV characteristics of the N-type OG-EDMOS transistors.
82
breakdown voltage of the orthogonal gate EDMOS transistor, it can be shortened to
further reduce the channel resistance. The specific on-resistance is reduced by 24% due to
the reduction of lateral channel length A. The OG-EDMOS drift region is completely
underneath the STI, and this reduces the risk of punch-through between the drift region
and the source. The minimum lateral channel length A1 is 0.3µm in OG-EDMOS before
punch-through breakdown will occur. As a result, we can reduce the channel length from
A2 = 0.9µm to A1 = 0.3µm.
20
25
30
35
40
45
50
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Lateral channel length A (µm)
Ro
n-s
p (
mO
hm
-mm2
)
0
5
10
15
20
25
30
35
Bre
akdow
n v
olta
ge (
V)
Figure 3.45 Simulated specific on-resistance variation vs. lateral channel length.
Since the STI depth is 0.35µm, the total channel length is estimated to be 0.3 + 0.35 =
0.65µm for the OG-EDMOS. As the effective channel length is reduced, the total
on-resistance is also lowered for the OG-EDMOS. The orthogonal gate can be employed
for universal breakdown voltage. For higher than 30V breakdown voltage EDMOS, the
83
drift region length should be increased, but near the orthogonal gate region, the critical
electrical field is still kept the same as 10 to15V/µm. Therefore, the OG-EDMOS can
work for a wide range of breakdown voltages while keeping the Ron,sp low.
3.5.2.5 Switching Time Results
The simulated switching time results are presented in Figure 3.46. The test is to send a
pulse to the gate and to see how fast the MOSFET can be turned on and turned off.
OG-EDMOS demonstrates faster rising time and faster falling time when compared to
conventional EDMOS as shown in Figure 3.46(b).
0
5
10
15
20
0 10 20 30 40
Time (ns)
Voltage (V)
OG-EDMOS Vds
EDMOS Vds
OG-EDMOS Vgs
EDMOS Vgs
D.U.T
(b) Switching time waveforms
Figure 3.46 Switching time test results.
Vds Rd
Vdd
Rg
Vgs
(a)Switching time test
84
3.5.2.6 dv/dt Capability
From the dv/dt simulation comparison as shown in Figure 3.47, the OG-EDMOS
transistor demonstrates a 4 times higher dv/dt capability for transistors with threshold
voltage =1V. This indicates that the OG-EDMOS is more stable than the conventional
EDMOS.
All the simulated electrical characteristics are listed in Table 3.8, which shows the
OG-EDMOS has superior electrical characteristics over the conventional EDMOS.
Figure 3.47 dv/dt capability comparisons between orthogonal gate and
conventional gate EDMOS transistors.
0
1
2
3
4
5
0 0.5 1 1.5 2 2.5 3 3.5
Vg(V)
dv/d
t (V
/µs)
OG-EDMOS
EDMOS
85
n-type EDMOS EDMOS OG-EDMOS
Ron,sp(mΩ·mm2) 42.9 32
BV(V) 30 30
Cgd(F/µm)@Vds=0V 1.1×10-15
2.8×10-16
Cgs(F/µm)@Vds=0V 9×10-16
7×10-16
Cds(F/µm)@Vds=0V 1.5×10-15
1.5×10-15
Gate Charge(C/µm) 4×10-14
2.5×10-14
FOM(nC·mΩ) 1716 810
dv/dt(V/µs) 0.6 2.4
3.5.3 OG-EDMOS Fabrication
The orthogonal gate EDMOS fabrication process is based on a 0.18µm CMOS
technology developed by Asahi Kasei EMD. This technology accommodates both high
voltage devices (30V n and p-type EDMOS transistors) and standard CMOS on the same
substrate. The thermal budget allocated to the standard CMOS devices is designed to
remain the same as before, hence the electrical characteristics of the standard CMOS
devices are not altered.
The fabrication steps are compatible with the standard CMOS flow. Process modules
are designed to be optional steps that can be added or removed from the baseline CMOS
technology. Figure 3.48 is a condensed flow chart for the orthogonal gate EDMOS
process. The starting wafer is a <100> oriented p-type wafer with a doping concentration
of 1×1015
cm−3
. At the beginning of the fabrication process, field oxidation is carried out
to form a thick layer of oxide followed by active lithography and oxide etching to define
the device area. Prior to the formation of the STI, TEOS (Tetraethylorthosilicate)
Table 3.8: Electrical characteristics comparison between the conventional and
orthogonal gate EDMOS.
86
deposition and annealing, deep n-well and HV p-well ion implantations are performed.
All the implanted impurities can be activated together during the STI annealing. The
n-drift ion implantation is carried out after the STI annealing, because RESURF
conditions require careful control of the n-drift dose and junction depth. The choice of
this dose is based on experimental diffusion trials and extensive process and device
simulations. Gate lithography and etch, gate oxidation, poly-silicon deposition,
poly-silicon etch and doping annealing are then carried out to form the gate electrode.
Standard CMOS Process Additional Steps
The details of process flow to form the orthogonal gate are illustrated in Figure 3.49.
The vertical gate formation requires an extra mask (see Figure 3.49(b)) and an extra
P-type substrate
Field oxide and active region
lithography
STI annealing
Gate lithography
Gate oxidation
TEOS oxide deposition and
contact formation
HV p-well I/I
n-drift I/I
Vertical gate
formation
Figure 3.48 Standard CMOS process flow with additional steps for the
orthogonal gate EDMOS implementation.
87
etching step (see Figure 3.49(c)). The conventional gate mask is then used to define the
entire orthogonal gate electrode. Thereafter, a thick inter-level oxide deposition of TEOS
is followed by contact lithography and oxide etching to form the contact window. Finally,
metallization covers the chip surface and forms the contacts for the EDMOS.
(a) (b) (c)
(d) (e) (f)
Figure 3.49 Orthogonal gate fabrication process flow. (a) Starting structure, (b)
Vertical gate lithography, (c) Vertical gate etch, (d) Gate oxidation, and (e)
Poly-silicon deposition, (f) Orthogonal gate definition
The breakdown dependence on STI depth is simulated and as shown in Figure 3.50.
For STI depth shallower than 0.2µm, RESURF condition of the drift region is not
satisfied, and the breakdown voltage is reduced. For STI depth deeper than 0.2µm, the
breakdown voltage will be maintained as 30V. For standard 0.18µm CMOS process from
STI
Ndrift HV Pwell
STI
Ndrift HV Pwell
photoresist
Ndrift HV Pwell
STI
HV Pwell Ndrift
STI
HV Pwell Ndrift
STI
HV Pwell Ndrift
STI
88
BV dependence on STI depth
0
5
10
15
20
25
30
35
0 0.1 0.2 0.3 0.4 0.5 0.6
STI Depth (µm)
BV
(V
)
AKM, the STI depth is set as 0.35µm, therefore, the breakdown voltage can always be
kept as 30V.
The vertical gate width can further be shrunk in order to reduce Cgd, as shown in
Figure 3.51. The breakdown voltage will remain relatively unchanged. This is because of
the fact that uses the same RESURF structure to build the drift region. Therefore,
OG-EDMOS still has the potential to further reduce Cgd with the development of more
advanced lithography technology.
Cgd depenednce with vertical gate width
0
5E-17
1E-16
1.5E-16
2E-16
2.5E-16
3E-16
0 0.05 0.1 0.15 0.2 0.25
Vertical gate width (µm)
Cg
d (
F)
Figure 3.51 Cgd dependence with vertical gate width.
Figure 3.50 Breakdown dependence vs. STI depth.
89
3.5.4 Summary
A transistor with an orthogonal gate electrode is proposed to improve dv/dt capability,
to reduce the gate-to-drain overlap capacitance (Cgd) and to improve the Figure-of-Merit
(FOM). The orthogonal gate has both a horizontal section and a vertical section for the
MOS gate electrode. This 30V device is designed for a 0.18µm CMOS compatible process.
Compared to a conventional EDMOS transistor with the same voltage rating and device
size, a 75% reduction in Cgd, 4-times-higher dv/dt capability and a 53% improvement in
FOM are observed.
90
REFERENCES
[1] Application Review and Comparative Evaluation of Low-Side Gate Drivers,
AN-6069, Fairchild Semiconductor.
[2] Power MOSFET Basics, AN-1084, International Rectifier Application Notes.
[3] J. Appels, H.Vaes, and J. Verhoeven, High voltage thin layer devices (RESURF
DEVICES), in IEDM Tech. Dig., p.238, 1978.
[4] J. Appels, M. Collet, P.Hart, H. Vaes, and J. Verhoeven, Thin layer high voltage
devices (RESURF DEVICES), Philips J. Res., Vol. 35, p.1, 1980.
[5] H. Vaes and J. Appels, High voltage, high current lateral devices, IEDM Tech. Dig.,
p.87, 1980.
[6] Adraan W. Ludikhuize, A Review of RESURF Technology, International
Symposiumon Power Semiconductor Devices and ICs (ISPSD), pp. 11-18, 2000.
[7] Michael Amato and Vladimir Rumennik, Comparison of lateral and vertical DMOS
specific on-resistance, pp.736-739, IEDM-1985.
[8] Philip L Hower, Short and long-term safe operating area considerations in EDMOS
transistors, International Reliability Physics Symposium, IEEE, pp. 545-550, 2005.
[9] P. Hower, A Rugged EDMOS for LBC5 Technology, Proc. ISPSD, pp. 327-330,
2005.
[10] Ik-Seok Yang, An Improvement of SOA on n-channel SOI EDMOS Transistors,
Proc. ISPSD, pp. 379-382, 1998.
[11] Vishnu Khemka, A Floating RESURF LD-MOSFET Device Concept, Electron
Device Letters, IEEE, Vol. 24, No. 10, pp. 664-666, 2003.
[12] John Lin, Two Carrier Current Saturation in a Lateral DMOS, Proc. ISPSD, pp. 1-4,
2006.
91
[13] Yuanzheng Zhu, Yung C. Liang, Shuming Xu, Pang-Dow Foo, Johnny K. O. Sin,
Folded gate LDMOS with low on-resistance and high tranconductance, IEEE
Transactions on Electron Devices, VOL. 48, NO. 12, December 2001.
92
Chapter 4 Experimental Results of Lateral Power MOSFET (EDMOS)
4.1 Introduction
The operation of the proposed 18V and 30V EDMOS were verified by using process
and device simulation in Chapter 3. This chapter will provide the characterization of the
fabricated EDMOS using a 0.18µm CMOS compatible process.
4.2 Experimental Results of 18V EDMOS
The experimental results of 18V EDMOS are presented in this section. The electrical
characterization is carried out by measuring the on- and off-state characteristics of
experimental EDMOS devices. Device performance as a function of major design
parameters is also provided and the feasibility of changing the doping concentration and
reducing the specific on-resistance are discussed. Finally, a summary of the experimental
results is presented.
4.2.1 Device Structure and Key Ion Implantation
In high voltage CMOS fabrication, in order to suppress the parasitic MOS from
turning on, the guarding ring is incorporated in the unit device, as illustrated in Figures
4.1(a) and (b), respectively.
Figure 4.1(a) N-type EDMOS
N+ P+ N+ Ndrift1, 2
HVPW
Psub
Deep Nwell(NISO)
STI STI STI N+
HVNW
P+ STI
P+ guard ring
Gate
Drain Source
STI
93
Figure 4.1(b) P-type EDMOS
The key ion implantation conditions are illustrated in Tables 4.1(a) and (b), respectively.
Table 4.1(a) 18V NMOS key ion implantation conditions
Process Mask Dopant Dose(/cm2) Energy(keV)
Deep Nwell Deep Nwell Phos. 1.00E+13 2300
HVPW HVPW Boron 1.30E+13 500
ND(Vth adjust) ND BF2 1.00E+12 60
Ndrift1 N-drift Phos. 5.00E+12 40
Ndrift2 N-drift Phos. 3.50E+12 150
Table 4.1(b) 18V PMOS key ion implantation conditions
Process Mask Dopant Dose(/cm2) Energy(keV)
HVNW HVNW Phos. 2.00E+12 700
PD(Vth adjust) PD Phos. 2.00E+12 40
Pdrift1 P-drift BF2 3.00E+12 20
Pdrift2 P-drift Boron 5.00E+12 40
4.2.2 Threshold Voltage and IV Characteristics
The threshold voltage was extracted at a drain voltage of 0.1V. The measured
threshold voltage for the n-type EDMOS is 1.2V and the Ids-Vgs plot is as illustrated in
Figure 4.2(a). The measured threshold voltage for the p-type EDMOS is −1.6V and the
corresponding Ids-Vgs curve is as shown in Figure 4.2(b).
Drain Source
P+ N+ P+ Pdrift1, 2
Psub
STI P+ STI STI
HVPW HVNW
Gate
N+ STI
N+ guard ring
94
0E+00
1E-05
2E-05
3E-05
4E-05
5E-05
6E-05
7E-05
8E-05
0 1 2 3 4 5 6
Vgs(V)
Id(A)
Figure 4.2 (a) Threshold voltage of N-type EDMOS
-3.5E-5
-3.0E-5
-2.5E-5
-2.0E-5
-1.5E-5
-1.0E-5
-5.0E-6
0.0E+0
-6 -5 -4 -3 -2 -1 0
Vgs(V)
Id(A)
Figure 4.2 (b) Threshold voltage of P-type EDMOS
The specific on-resistance Ron,sp was obtained from the inverse of the slope of the Ids-Vds
plot with a gate voltage of Vgs=10V, and Vds=0.1V. As extracted from Figure 4.3(a), the
specific on-resistance of the n-type EDMOS device is 16.6mΩ·mm2. For the p-type
EDMOS device, the specific on-resistance as extracted from Figure 4.3(b) is 30mΩ·mm2.
95
0E+00
1E-03
2E-03
3E-03
4E-03
5E-03
6E-03
7E-03
0 2 4 6 8 10 12 14 16
Vds (V)
Id(A
)
Figure 4.3 (a) IV characteristics of N-type EDMOS
0.0E+00
5.0E-04
1.0E-03
1.5E-03
2.0E-03
2.5E-03
3.0E-03
3.5E-03
4.0E-03
-16-14-12-10-8-6-4-20
Vds (V)
|Id| (A
)
Figure 4.3 (b) IV characteristics of P-type EDMOS
Vgs=3V
Vgs=6V
Vgs=9V
Vgs=12V
Vgs=15V
Vgs=−3V
Vgs=−6V
Vgs=−9V
Vgs=−12V
Vgs=−15V
96
4.2.3 Breakdown Characteristics
The breakdown voltage of all the devices was measured with the gate, source and
body grounded. The current limit was set to 1µA. The measured breakdown voltage is
18.4V for n-type device and -21.8V for p-type device. The plots of the off state IV curves
for these measurements are illustrated in Figure 4.4(a) and Figure 4.4(b), respectively.
Figure 4.4(a) and (b) Breakdown characteristics of N-type EDMOS and P-type EDMOS.
1E-13
1E-12
1E-11
1E-10
1E-09
1E-08
1E-07
1E-06
1E-05
-25-20-15-10-50Vds (V)
|I d|
(A
)
(b)
1E-13
1E-12
1E-11
1E-10
1E-09
1E-08
1E-07
1E-06
1E-05
0 5 10 15 20
Vds (V)
Id
(A)
(a)
97
4.3 Experimental Results of 30V CMOS
The experimental results of 30V CMOS are presented in this section.
4.3.1 Device Structure and Key Ion Implantation
30V n-type and p-type EDMOS structures are illustrated in Figures 4.5(a) and 4.5(b),
respectively.
Figure 4.5(a) N-type EDMOS
Figure 4.5(b) P-type EDMOS
The key ion implantation conditions are listed in Tables 4.2(a) and (b), respectively.
N+ P+
HPE
BN
NW
Psub
Deep Nwell
STI STI STI P+ P+
Pdrift1, 2, 3
STI
HVPW
P-Buffer
A
B
L
Gate
Drain Source
P+ N+
HVPW
P-Buffer
Psub
Deep Nwell
STI STI STI N+ N+
Ndrift1,2,3,4,5
A
STI
Nsink1
Nsink2
Nsink3
L B
P+ STI
P+ guard ring Gate
Drain Source
98
Table 4.2(a) 30V NMOS key ion implantation conditions
Process Mask Dopant Dose(/cm2) Energy(keV)
Deep Nwell Deep Nwell Phos 1.00E+13 2300
P-Buffer Boron 1.50E+13 1150
HVPW HVPW Boron 5.80E+12 200
Nsink1 Phos 1.00E+13 1550
Nsink2 Phos 1.00E+13 800
Nsink Nsink Phos 1.00E+12 300
ND(Vth adjust) ND BF2 1.65E+12 60
N-drift1 Phos 4.50E+12 680
N-drift2 Phos 2.50E+12 400
N-drift3 Phos 2.00E+12 250
N-drift4 Phos 2.50E+12 120
N-drift5 N-drift Phos 3.00E+12 60
Table 4.2(b) 30V PMOS key ion implantation conditions
Process Mask Dopant Dose(/cm2) Energy(keV)
Deep Nwell Deep Nwell Phos 1.00E+13 2300
P-Buffer Boron 1.50E+13 1150
HVPW HVPW Boron 5.80E+12 200
NW Phos 2.00E+13 360
BN NW Phos 1.50E+12 100
PD(Vth adjust) PD Phos 8.70E+11 40
P-drift1 Boron 1.50E+12 200
P-drift2 Boron 3.00E+12 120
P-drift3 P-drift BF2 5.00E+12 60
4.3.2 Threshold Voltage and IV Characteristics
0.0E+0
2.0E-5
4.0E-5
6.0E-5
8.0E-5
1.0E-4
1.2E-4
0 1 2 3 4 5 6
Vgs(V)
Id(A)
Figure 4.6(a) Threshold voltage of N-type EDMOS.
99
-4.5E-5
-4.0E-5
-3.5E-5
-3.0E-5
-2.5E-5
-2.0E-5
-1.5E-5
-1.0E-5
-5.0E-6
0.0E+0
-6 -5 -4 -3 -2 -1 0
Vgs(V)
Id(A)
Figure 4.6(b) Threshold voltage of P-type EDMOS.
The specific on-resistance of the n-type EDMOS device is 45mΩ·mm2, and Vth=0.8V.
For the p-type EDMOS device, the specific on-resistance is 70mΩ·mm2, and Vth=−0.8V.
0E+0
1E-3
2E-3
3E-3
4E-3
5E-3
0 5 10 15 20 25 30
Vds (V)
Id (
A)
Figure 4.7 (a) IV characteristics of N-type EDMOS.
Vgs=1V
Vgs=2V
Vgs=3V
Vgs=4V
Vgs=5V
100
0.0E+0
5.0E-4
1.0E-3
1.5E-3
2.0E-3
2.5E-3
-30-25-20-15-10-50Vds (V)
|Id| (A
)
Figure 4.7 (b) IV characteristics of P-type EDMOS.
4.3.3 Breakdown Characteristics
The breakdown voltage is 35V for n-type EDMOS and −37V for p-type EDMOS,
respectively.
1E-13
1E-12
1E-11
1E-10
1E-9
1E-8
1E-7
1E-6
1E-5
0 10 20 30 40 50
Vds(V)
Id(A)
Vgs=−1V
Vgs=−2V
Vgs=−3V
Vgs=−4V
Vgs=−5V
Figure 4.8(a) Breakdown characteristics of N-type EDMOS.
101
1E-13
1E-12
1E-11
1E-10
1E-09
1E-08
1E-07
1E-06
1E-05
-45-40-35-30-25-20-15-10-50
Vds (V)
|Id|(A
)
Figure 4.8(b) Breakdown characteristics of P-type EDMOS.
Table 4.3 Summarized simulation and measured results
18V NMOS Simulation Measured
BV (V) 25.2 18.4
Ron,sp (mΩ-mm2) 11 16.6
Vth (V) 1.6 1.2
18V PMOS Simulation Measured
BV (V) -25 -21.8
Ron,sp (mΩ-mm2) 22 30
Vth (V) -1.7 -1.6
30V NMOS Simulation Measured
BV (V) 35 35
Ron,sp (mΩ-mm2) 42 45
Vth (V) 0.7 0.8
30V PMOS Simulation Measured
BV (V) -35 -37
Ron,sp (mΩ-mm2) 52 70
Vth (V) -1.2 -0.8
102
The measured and simulation results of all the devices are summarized in Table 4.3.
In general, simulation data are in reasonable agreement with experimental data. The
measured breakdown voltages of 18V devices are lower than the simulation data, which
can be caused by the fact that the junction depth of the drift regions is shallower than
expected, or not enough dopants are introduced in the drift region. SIMS calibration
should be carried out to check the real doping profile.
The discrepancy in the threshold voltage can be caused by the trapped charges that
exit at the oxide interface. Furthermore, process uncertainty fluctuates between different
lots or even on the same wafer. Threshold adjustment implantation can be implemented
in fabrication to fine tune the threshold voltage.
The specific on-resistances of simulation data are lower than the measured results for
all the fabricated devices. This is due to the fact that simulations are carried out in ideal
conditions, which does not consider contact resistances. Besides contact resistances, the
package resistance can also increase the overall resistance.
103
4.3.4 Geometry Variation
Geometry variation measurements are reported in this section to determine the
optimized device dimension. All the dimension parameters are as shown in Figure 4.9.
4.3.4.1 NMOS Breakdown Voltage vs. Geometry
Figure 4.9 NMOS geometry
A dimension dependence
0
5
10
15
20
25
30
35
40
0 0.5 1 1.5 2 2.5
A dimension (µm) @ B=0.4µm
BV
DSS
(@1µA
) (V
)
NDrift 1=4.5e12cm-2(#1)
NDrift 1=5.2e12cm-2(#6)
NDrift 1=6.5e12cm-2(#11)
Figure 4.10 BV vs. A dimension
P+ N+
HVPW
P-Buffer
Psub
Deep Nwell
STI STI STI N+ N+
Ndrift1,2,3,4,5
A
STI
Nsink1
Nsink2
Nsink3
C B
P+ STI
P+ guard ring Gate
Drain Source
D
104
Wafers number 1, 6 and 11 corresponds to 3 different drift doping concentrations.
Wafer 1 has the lowest doping concentration, wafer 6 has medium doping concentration
and wafer 11 has the highest doping concentration. It is obvious that the lowest drift
doping concentration has the highest breakdown voltage.
For dimension A (see Figure 4.9) smaller than 1.4µm, the drain and source will have
punch-through breakdown, so the breakdown voltage degrades significantly. In order to
keep the high breakdown voltage, dimension A is chosen as 1.4µm.
If dimension A is kept as 1.4µm while changing dimension B, the breakdown voltage
dependence experiments are also carried out to find out the relationship, as shown in
Figure 4.11. As dimension B is bigger than 0.4µm, the effective channel is shorter than
1µm, and the punch-through breakdown is the main cause of the breakdown degradation.
Thus, we can conclude that the effective channel length should be longer than 1µm in
order to keep the breakdown immune from the punch-through breakdown. Therefore,
B=0.4µm is chosen.
Figure 4.11 BV vs. B dimension
B dimension dependence
0
5
10
15
20
25
30
35
40
0 0.2 0.4 0.6 0.8 1
B dimension (µm) @ A=1.3µm
BV
DSS(@
1µA
) (V
)
NDrift 1=4.5e12cm-2(#1)
NDrift 1=5.2e12cm-2(#6)
NDrift 1=6.5e12cm-2(#11)
105
4.3.4.2 PMOS On-resistance vs. Geometry
Figure 4.12 PMOS geometry
N+ P+
HPE
BN
NW
Psub
Deep Nwell
STI STI STI P+ P+
Pdrift1, 2, 3
STI
HVPW
P-Buffer
A
B
Gate
Drain Source
D
C
0
20
40
60
80
100
120
140
160
180
200
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
A (µm) @ B=0.4µm
Ron,
sp(m
Ω-m
m2)
Figure 4.13(a) Specific on-resistance vs. A dimension
106
If A dimension is smaller than 0.5µm, there is a large leakage current, and punch-
through breakdown can occur. The B dimension determines the current pass width of the
EDMOS. A larger B dimension results in a wider current pass and a smaller specific on-
resistance, but at the same time, it increases the risk of punch-through breakdown. And
this causes a larger gate to drain overlap capacitance. Therefore, A = 0.7µm and B =
0.4µm are chosen for 30V p-type EDMOS.
0
20
40
60
80
100
120
140
160
180
200
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
B (µm) @ A=0.7µm
Ron,s
p(m
Ω-m
m2)
Figure 4.13(b) Specific on-resistance vs. B dimension
107
4.4 Experimental Results of EDMOS with Enhanced SOA
The experimental results of EDMOS with enhanced SOA are presented in this section.
4.4.1 Snapback Characteristics Comparison
The IV characteristics of the 30V EDMOS at high Vgs and high Vds are improved, the
bipolar behavior at high Vgs is suppressed by using the phosphorus ion implantation at the
drain. The comparison is shown in Figures 4.14(a) and 4.14(b), respectively.
Figure 4.14 (a) Snapback of conventional EDMOS
Figure 4.14 (b) Snapback of proposed EDMOS
0E+0
1E-3
2E-3
3E-3
4E-3
5E-3
6E-3
7E-3
8E-3
9E-3
1E-2
0 5 10 15 20 25 30 35 40
Vds (V)
Ids
(A)
Vgs=2V
Vgs=3V
Vgs=4V
Vgs=5V
Vgs=6V Curves overlap each
other for Vgs>7V
0E+0
1E-3
2E-3
3E-3
4E-3
5E-3
6E-3
7E-3
0 5 10 15 20 25 30 35 40
Vds (V)
Ids
(A)
Vgs=2V
Vgs=3V
Vgs=4V
Vgs=5V
Vgs=6V
Curves overlap each other for Vgs>7V
108
The conventional EDMOS exhibits the snapback characteristics at Vgs=10V and
Vds=22V. The negative resistance characteristics are clearly exhibited. The current
increases while the drain voltage decreases, which indicates that the internal parasitic
BJT is turned on, and the EDMOS is into snapback breakdown.
Compared to the conventional EDMOS, the novel EDMOS demonstrates stable
behavior for all Vgs conditions, which proves the validity of the BJT suppression methods.
We observe that the deep NWell junction depth is not as deep as expected, which
results in the breakdown voltage remaining at 32V rather than at 62V as in the simulation.
Further fabrication may fine tune the deep Nwell junction depth to match the simulation.
109
4.5 Experimental Results of Orthogonal Gate EDMOS
The OG-EDMOS electrical characteristics are presented in this section. The
orthogonal gate concept can be applied to both n-type EDMOS and p-type EDMOS, as
illustrated in SEM photos in Figure 4.15.The vertical gate width is 0.2µm, and it is
completely embedded in the Shallow Trench Isolation (STI). The overlap between the
gate and drain is only attributed to the thickness of the vertical gate; therefore, the overlap
capacitance of the gate and drain is only 0.2µm.
(a) N-type OG-EDMOS (b) P-type OG-EDMOS
Figure 4.15 (a) N-type and (b) P-type OG-EDMOS
110
4.5.1 Threshold Voltage and IV Characteristics
The threshold voltage is 0.6V for n-type OG-EDMOS, and −0.8V for p-type OG-
EDMOS.
0E+00
1E-05
2E-05
3E-05
4E-05
5E-05
6E-05
7E-05
8E-05
9E-05
1E-04
0 1 2 3 4 5 6
Vgs (V)
Id (A
)
-3E-05
-2E-05
-2E-05
-1E-05
-5E-06
0E+00
-6 -5 -4 -3 -2 -1 0
Vgs (V)
Id (A
)
Figure 4.16 (b) Threshold voltage of P-type OG-EDMOS
Since the lateral channel length is shortened, threshold voltage adjustment ion
implantations are necessary for both n-type OG-EDMOS and p-type OG-EDMOS.
Phosphorus ion implantations at 40KeV with 1.6e12cm-2 and BF2 ion implantation at
Figure 4.16 (a) Threshold voltage of N-type OG-EDMOS
111
60KeV with 1.65e12 cm-2
are implemented respectively. The Ron,sp=32.4mΩ·mm2 and
68mΩ·mm2 at Vgs=5V for n and p-type OG-EDMOS, are implemented respectively.
Figure 4.17(a) IV characteristics of N-type OG-EDMOS
0.0E+00
5.0E-04
1.0E-03
1.5E-03
2.0E-03
2.5E-03
3.0E-03
3.5E-03
4.0E-03
4.5E-03
0 5 10 15 20 25 Vds (V)
Vgs=5V
Vgs=4V
Vgs=3V
Vgs=2V
Vgs=1V
Id (
A)
0.0E+0
2.0E-4
4.0E-4
6.0E-4
8.0E-4
1.0E-3
1.2E-3
1.4E-3
1.6E-3
1.8E-3
2.0E-3
-25-20-15-10-50
Vds (V)
|Id| (A
)
Figure 4.17(b) IV Characteristics of P-type OG-EDMOS
Vgs=−1V
Vgs=−2V
Vgs=−3V
Vgs=−4V
Vgs=−5V
112
4.5.2 Breakdown Characteristics
The breakdown voltage is 35V for n-type OG-EDMOS and -39V for p-type OG-
EDMOS, respectively.
1E-12
1E-11
1E-10
1E-9
1E-8
1E-7
1E-6
1E-5
1E-4
1E-3
1E-2
1E-1
1E+0
0 10 20 30 40
Vds(V)
Id(A)
Figure 4.18(a) Breakdown characteristics of N-type OG-EDMOS
1E-15
1E-13
1E-11
1E-9
1E-7
1E-5
1E-3
1E-1
-50-40-30-20-100
Vds(V)
|Id|(A)
Figure 4.18(b) Breakdown characteristics of P-type OG-EDMOS
113
0.01
0.1
1
10
100
10 100
Breakdown voltage (V)
Specific
on
-re
sis
tance (
mΩ
cm
2)
LDMOS-EDMOS
Si-limit
OG-EDMOS
[1]
[2]
[3][4]
[5]
[2]
[6]
[2]
[7]
[8]
[9] [10]
[10]
Figure 4.19 Comparison of Ron,sp vs. BV of the OG-EDMOS and previously published
results.
For comparative purposes, the specific on-resistance, Ron,sp and the breakdown
voltage of this work are plotted along with other published results as illustrated in Figure
4.19. Most of the published works were implemented based on advanced BiCMOS
technology. The performance of the high voltage devices in this work is shown to be
comparable with those fabricated using more complex and expensive processes.
114
4.5.3 Capacitance Characteristics
The measured capacitances comparisons between OG-EDMOS and conventional
EDMOS are listed in Table 4.4. A 75% and 87% Cgd reduction are observed in n-type
and p-type EDMOS, respectively.
Table 4.4 Capacitance comparison between OG-EDMOS and conventional EDMOS
NMOS Cgs(pF) Cgd(pF) Cds(pF)
OG-EDMOS 6.631 3.025 10.392
Conventional EDMOS 8.524 12.098 10.411
PMOS Cgs(pF) Cgd(pF) Cds(pF)
OG-EDMOS 6.952 1.343 8.233
Conventional EDMOS 9.152 10.322 8.914
The device FOM is 810 nC·mΩ (BV = 35V, Ron = 32mΩ, Qg=25nC) which compares
favorably against commercially available power MOSFETs (e.g., Toshiba2SK2965,
FOM = 1450 nC·mΩ, (BV = 30V, Ron = 250mΩ, Qg = 5.8nC).
The total power loss is attributed to the on-state loss and switching loss, as presented
in equation 4.1.
With the Cgd significantly reduced, the switching loss will be tremendously low. The
enhanced performance of the OG-EDMOS will translate into better power conversion
efficiency when employed in switched-mode power supply applications.
Generally, the experimental results are in good agreement with simulation results, but
we observed a leakage current in the OG-EDMOS transistor. The leakage current is due
to the reduction of total channel length. Either a threshold voltage adjustment ion
implementation should be added or a lateral channel length should be increased in future
lots to suppress the leakage current.
2
( )( ) ( )gd
loss rms DS on DS
g
QP I R I V fc
I= × + × × × (4.1)
115
The measured and simulation results of OG-EDMOS are summarized in Table 4.5.
Table 4.5 Summarized measured and simulation results
30V P-type OG-MOS Simulation Measured
BV (V) -35 -39
Ron,sp (mΩ-mm2) 50 68
Vth (V) -1.2 -0.8
30V N-type OG-EDMOS Simulation Measured
BV (V) 30 35
Ron,sp (mΩ-mm2) 32 32.4
Vth (V) 0.7 0.6
116
REFERENCES
[1] Adriaan W. Ludikhuize, Lateral 10-15V DMOST with very low 6 mOhm·mm2 on-
resistance, Proc. ISPSD, pp. 301-304, 2002.
[2] W. Nehrer, L. Anderson, T. Debolske, T. Efland, P. Fleischmann, C. Haidinyak, W.
Leitz, M. McNutt, E. Mindricelu, S. Pendharkar, J. Smith, R. V. Taylor, Power
BICMOS process with high voltage device implementation for 20V mixed signal
circuit applications, Proc. ISPSD, pp. 263-266, 2001.
[3] Kozo Kinoshita, Yusuke Kawaguchi, Takeshi Sano, and Akio Nakagawa, 20V
LDMOS optimized for high drain current condition. Which is better, n-epi or p-epi?
Proc. ISPSD, pp.59-62, 1999.
[4] Adriaan W. Ludikhuize, Self-aligned and shielded-RESURF LDMOS for dense
20V power IC’s, Porc. ISPSD, pp. 81-84, 1999.
[5] Kazutoshi Nakamura, Yusuke Kawaguchi, Kumiko Karouji, Kiminori Watanabe,
Yoshihiro Yamaguchi and Akio Nakagawa, Complementary 25V LDMOS for
analog applications based on 0.6µm BiCMOS technology, Proc. BCTM, pp. 94-97,
2000.
[6] Peter C. Mei, Katsumi Fujikura, Takaaki Kawano, Satwinder Maihi, A high
performance 30V extended drain RESURF CMOS device for VLSI intelligent
power applications, VLSI Technology Digest, pp. 81-82, 1994.
[7] R. Zhu, V. Parthasarathy, V. Khemka, A. Bose and T. Roggenbauer,
Implementation of high-side, high-voltage RESURF LDMOS in a sub-half micron
smart power technology, Proc. ISPSD, pp.403-406, 2001.
117
[8] R. Zhu, V. Khemka, A. Bose, T. Roggenbauer, Stepped-drift LDMOSFET: a novel
drift region engineered device for advanced smart power technologies, Proc. ISPSD,
pp.1-4, 2006.
[9] T.H Kwon, Y. S Jeoung, S. K. Lee, Y. C. Choi, C.J. Kim, H. S. Kang and C.S.Song,
Newly designed isolated RESURF LDMOS transistor for 60V BCD process
provides 20V vertical NPN transistor, Device Research Conference, pp. 67-68,
2002.
[10] Taylor Efland, Satwinder Malhi, Wayne Bailey, Oh Kyong Kwon, Wai Tung Ng,
Manolo Torreno and Steve Keler, An optimized RESURF LDMOS powr device
module compatible with advanced logic processes, IEDM, pp. 237-240, 1992.
118
Chapter 5 Conclusions and Future Work
5.1 Conclusions
For modern power semiconductors, it is clear that conventional breakdown voltage
and on-resistance are no longer the primary performance indicators. Figure of merit,
capacitance, switching time, safe operating area, and dv/dt capability, etc., are essential
electrical characteristics that need to be considered and well-designed to satisfy the
current market needs. This thesis provided a detailed description of the design and
implementation of both vertical and lateral power MOSFETs with enhanced electrical
characteristics, which can have a variety of applications such as display drivers, power
supplies as well as automotive applications.
A trenched LOCOS process has been applied to an UMOS structure to reduce gate-
to-source overlap capacitance (Cgs), and it has been observed that not only a 40%
reduction in Cgs is achieved, but also a 45% reduction in specific on-resistance (Ron,sp).
Figure-of-Merit (FOM) is improved by 58%. TSUPREM4 doping profile simulation at
the silicon and oxide interface revealed the presence of boron segregation. On-resistance
reduction is attributed to the shortened vertical channel length due to boron segregation.
We proposed a floating RESURF EDMOS with a suppressed parasitic NPN transistor
to provide a large Safe Operating Area (SOA). Investigating the SOA of a floating
RESURF EDMOS, rather than a breakdown voltage and specific on-resistance
relationship, is a new aspect for power devices. The base resistance of the parasitic NPN
transistor is reduced and the hole current that would normally be problematic at high Vgs
and high Vds is suppressed. These two enhancements suppress the turn-on mechanisms
for the parasitic NPN transistor. The floating RESURF technique is utilized to support
119
high breakdown voltage and achieve low on-resistance. An estimated 400% enhanced
Safe Operating Area (SOA) has been observed as compared to that of the conventional
EDMOS structure. Finally, all the processing steps introduced remain fully compatible
with the standard CMOS process.
We also proposed a novel orthogonal gate structure in EDMOS, which needs only
one extra mask, and all proposed processes are fully compatible with the standard CMOS
process. By taking advantage of the Shallow Trench Isolation (STI) process, an
orthogonal gate structure can be formed. This gate structure has 75% reduction in the
gate-to-drain capacitance (Miller capacitance), so that the device has a fast switching
time and a low switching loss. Figure-of-Merit (Qg×Ron) is improved by 53%. The dv/dt
capability is four times higher than that of the conventional EDMOS.
0.01
0.1
1
10
100
10 100
Breakdown voltage (V)
Specific on-resistance (mΩcm2)
EDMOSUMOSSi-limitOG-EDMOSLOCOS UMOS18V EDMOS30V EDMOS
Figure 5.1 Comparison of Ron,sp Vs. BV of power MOSFETs with previously published results.
120
For illustrative purpose, the specific on-resistance, Ron,sp and the breakdown voltage
for devices developed in this thesis are plotted along with other published results as
illustrated in Figure 5.1. The performance of the proposed devices compares favorably
against commercially available power MOSFETs.
5.2 Future Work
Future work could investigate deep trench technology in UMOS and incorporate
floating p-type islands underneath the trench to increase the breakdown voltage, as shown
in Figure 5.2. In such a way, the breakdown voltage and specific on-resistance
relationship can be further improved. The deep portion of the trench can be filled with
poly-Si, which will have a smaller Miller capacitance.
Hot carrier effects should also be investigated in the OG-EDMOS to ensure long-
term reliability. Hot Carrier Injection (HCI) tests and Time-Dependent Dielectric
Breakdown (TDDB) tests should be carried out in future lots.
Since the OG-EDMOS has a smaller Cgd, RF characteristics, such as Ft and Fmax, this
can also be explored. Thermal simulation in a silicon lattice during the snapback process
could be a useful research area for power MOSFETs.
Drain
Figure 5.2 Novel UMOS structure
Floating p-type islands
Source
Gate
Poly-Si
121
The integration of OG-EDMOS with floating RESURF EDMOS might be another
interesting research project in the future, because such EDMOS could have all the
excellent features that were described in this thesis. Figure 5.3 shows the OG floating
RESURF EDMOS. The device is expected to have fast switching, high dv/dt capability
while maintain the large safe operating area.
Figure 5.3 Orthogonal Gate (OG) floating RESURF EDMOS structure
Finally, the optimization of a device package or thermal extraction methods to
achieve higher reliability could be another new aspect of power MOSFETs research.
S G
D
Vgs=0V
Vds=50V
5V/line
122
Appendix I UMOS Design and Process Flow
The breakdown voltage of UMOS is already analyzed in Chapter 2. The UMOS on-
resistance is analyzed in this appendix. The on-resistance of the UMOS transistor consists
mainly of channel resistance and the drift region resistance. In addition, the resistance of
the N+ source and N+ substrate can also be accounted. Figure A1.1 is the UMOS
structure used for analysis.
Figure A1.1 UMOS structure
For the UMOS structure, the channel resistance is
( )ch
ch
ox G T
LR
Z C V Vµ=
− (A1.1)
where Z is the width of the device, and the unit device area is ( )2 2m tW W
A Z= + ⋅ .
Therefore, the specific resistance (mΩ-mm2) is give by chR A⋅ ,
N+
P body
N drift
N+
Gate
Wt /2
LN+
LCH
t D
Z Wm /2
Source
Drain
P+
Current flow
123
,
( )
2 ( )ch m t
ch sp
ox G T
L W WR
C V Vµ+
=−
(A1.2)
The UMOS structure can be fabricated with narrow cell pitch because of the absence of
the JFET region. The cell pitch in the UMOS structure is determined by the process and
the lithographic design rules.
The drift region spreading resistance is:
, ( ) ln( ) ( )2 2
m t m t mD sp D D
t
W W W W WR t
Wρ
+ + = + −
(A1.3)
Dρ is the resistivity of the drift region, the detail derivation can be found in reference [1].
The N+ source specific resistance is
, ( )m tN sp N N
m
W WR t
Wρ+ + +
+= (A1.4)
Due to the high doping concentration and small thickness of the N+ source region, the
contribution from this resistance is usually negligible.
The N+ substrate specific resistance is
,SB sp SB SBR tρ= (A1.5)
where SBρ and SBt are the resistivity and thickness of the substrate.
It is important to reduce this value by thinning the substrate because this resistance is
comparable to the channel and drift region resistance for the UMOS structure.
It is beneficial to reduce the cell pitch as much as possible with respect to the
fabrication limits. As these dimensions become smaller, the channel resistance
contribution becomes smaller due to an increase in the channel density.
REFERENCE
[1] B. J. Baliga, Power Semiconductor Devices, PWS Publishing Company, 1996.
124
UMOS Process Flow
The device fabrication is based on a 7 µm n-type epitaxial layer with phosphorus
doping of 5×1015 cm-3 on top of a heavily As-doped n+ (100) substrate. Boron implantation
of 3×1013 cm-2 at 120 keV was used and driven in for 60 minutes at 1150°C to produce the
p-body. n+ ion implantation of 5×1015cm-3 Arsenic at 80 keV is implanted after the
formation of p-body. A 2µm deep and 1µm wide U-shaped trench was dry etched. BF2
was used to adjust the threshold voltage after the growth of a thin layer of sacrificial oxide.
A 700Å gate oxide growth is carried out at 950°C for 15.5 minutes after briefly annealing
and removing the sacrificial oxide. Poly-silicon in situ refill and planarization were
followed after the gate oxidation. A p+ ion implantation of 2.5×1015cm-3 BF2 at 60 keV
was carried out to form the ohmic contact between semiconductor and metal. Finally,
contact holes were opened for metal deposition. The process flow steps are shown from
page 128.
125
Figure A1.2 UMOS process flow chart
I/I: Ion Implantation
SOX: Superficial Oxidation
TEOS: Tetraethyl Orthosilicate
BPSG: Borophosphosilicate glass
Start N+ Si(100)
7µm N-epi (As-5e15 cm-3)
Field OX (6500Å), active litho, pad OX, P-body litho,
P-body drive in anneal
N+ litho, N+ I/I, drive in anneal
1000Å Oxide depo, trench litho, DTI etch and rounding
Optional: SOX, Vth I/I, SOX etch
Gate oxidation (700Å) In-situ poly-si depo and etch back
gate poly
Light OX , P+ litho, P+ I/I, drive in anneal
TEOS depo and BPSG anneal
Metal CNT litho, metallization
Passivation, test devices
126
Figure A1.3 UMOS layout
1µ
mG
ate
Sourc
e
127
Metal
N+ sub
N-epi
Fox
Poly Si
N+
Pbody
P+
P+
Active
P b
od
y
N+
TG
Ga
te
P+
Con
tact
Me
tal
Figure A1.4 UMOS m
asks
Metal
128
N+ sub
N-epi
Fox
N+ sub
N-epi
Fox
Pbody
N+ sub
N-epi
Fox
Pbody
N+
1st Oxidation(6500A)
Act Litho
Act W
et Eching
Act Dry Etching
Resist Rem
ove
2ndOxidation(300A)
PbodyLitho
PbodyI/I
Resist Rem
ove
PbodyAnneal
N+ Litho
N+ I/I
Resist Rem
ove
N+ Anneal
Ox:6500A
Ox:300A
7um
Fig
ure
A1.5
UM
OS
pro
cess f
low
129
N+ sub
N-epi
Pbody
N+
Fox
N+ sub
N-epi
Pbody
N+
Fox
N+ sub
N-epi
Fox
N+
Pbody
Pbody
Poly Si
TCAP Oxidation(1000A)
TG Litho
TCAP Etching
Resist Rem
ove
TG Etching (2um depth)
Gate Oxidation(700A)
Poly Si Deposition(7000A)
TCAP Ox:1000A
2um depth
Poly Si :7000A
1um width
0.6um width
The remainder of TcapOx : 500A
(after Poly Si Etch Back)
130
N+ sub
N-epi
Fox
Poly Si
N+
Pbody
Gate Litho
Poly Si Etch Back
Resist Rem
ove
HLD Deposition(150A)
TEOS Deposition(6300A)
N+ sub
N-epi
Fox
Poly Si
N+
Pbody
0.5um width
0.5um depth
P+
P+
6300A
N+ sub
N-epi
Fox
Poly Si
N+
Pbody
P+
P+
Light Oxidation(100A)
P+ Litho
P+ W
et Etching
P+(Si) Etching(0.5um)
P+ I/I
Resist Rem
ove
P+ Anneal
131
Cont Litho
Cont Etching
Resist Rem
ove
0.9um width
6300A
N+ sub
N-epi
Fox
Poly Si
N+
Pbody
P+
P+
Ti/TiN
Depo(700A/600A)
Al Depo(30000A)
AL Litho
AL Etching
Metal
N+ sub
N-epi
Fox
Poly Si
N+
Pbody
P+
P+
Devic
eT
erm
ination
132
Appendix II EDMOS Process Flow
The EDMOS fabrication process is based on a 0.18µm CMOS technology developed
by Asahi Kasei EMD. This technology accommodates both high voltage devices (30V n
and p-type EDMOS transistors) and standard CMOS devices on the same substrate. The
thermal budget allocated to the standard CMOS devices is designed to remain the same as
before, hence the electrical characteristics of the standard CMOS devices are not altered.
The fabrication steps are compatible with the standard CMOS flow. Process modules
are designed to be optional steps that can be added or removed from the baseline CMOS
technology. The starting wafer is a <100> oriented p-type wafer with a doping
concentration of 1×1015cm
−3. At the beginning of the fabrication process, field oxidation
is carried out to form a thick layer of oxide followed by active lithography and oxide
etching to define the device area.
Prior to the formation of the STI, TEOS (Tetraethylorthosilicate) deposition and
annealing, deep n-well and HV p-well ion implantations are performed. All the implanted
impurities can be activated together during the STI annealing process. The n-drift ion
implantation is carried out after the STI annealing, because RESURF conditions require
careful control of the n-drift dose and junction depth. The choice of this dose is based on
diffusion trials and extensive process and device simulations. Gate lithography and etch,
gate oxidation, poly-silicon deposition, poly-silicon etch and doping annealing are then
carried out to form the gate electrode.
Thereafter, a thick inter-level oxide deposition of TEOS is followed by contact
lithography and oxide etching to form the contact window. Finally, metallization covers
the chip surface and forms the contacts for the EDMOS.
133
Standard CMOS Process Option HV Steps
P-type substrate
Field oxidation & active
region lithography
STI annealing
Gate lithography
TEOS oxide deposition
and contact formation
Metallization
Backend process
HV Pwell, deep NWell
ion implantation
Ndrift I/I ion
implantation
p-type buried layer
and n-type drain ion
implantation
Standard CMOS Process Option HV Steps
P-type substrate
Field oxidation & active
region lithography
STI annealing
Gate lithography
TEOS oxide deposition
and contact formation
Metallization
Backend process
HV Pwell, deep NWell
ion implantation
Ndrift I/I ion
implantation
p-type buried layer
and n-type drain ion
implantation
Figure A2.1 EDMOS process flow chart
134
Fig
ure
A2
.2 N
MO
S d
ie p
ho
to
Dee
p N
wel
l
Dra
in
Gat
eS
ou
rce
85
µm
85
µm
135
Fig
ure
A2
.3 N
MO
S(3
0V
) m
ask
sN
ISO
NW
PWPD
PE
ND
NL
E
NE
NM
HN
M
HP
M
PM N+
P+
P-b
uff
er
Pw
el
Nsi
nk
Nd
rift
Pd
rift
P+
N+
PW
Psu
b
Dee
p N
wel
l(N
ISO
)
ST
IS
TI
ST
IN
+
NW
Nsi
nk
N+
ST
I
N-d
rift
DG
N
P-b
uff
er
HV CMOS mask
Standard CMOS mask
136
N+
P+
Psu
b
PW
Dee
p N
wel
l(N
ISO
)
NW
P+
ST
IS
TI
ST
IS
TI
P-d
rift
P+
PM
OS
(30
V)
mas
kN
ISO
NW
PWPD PE
ND
NL
E
NE
NM
HN
M
HP
M
PM N+
P+
DG
P
P-b
uff
er
Pw
el
Nsi
nk
Nd
rift
Pd
rift
Nsi
nk
HV CMOS mask
Standard CMOS mask
137
P sub
STI etch
Starting p substrate
P sub
Figure A2.4 EDMOS process flow
138
STI
STI
STI
STI
STI
Deep Nwell (NISO)
P sub
NISO Ion Implantation (I/I)
STI Chemical Mechanical
Polishing (CMP)
P sub
Deep Nwell (NISO)
139
STI
STI
STI
Deep Nwell (NISO)
P sub
STI
Ndrift
STI
Deep Nwell (NISO)
P sub
STI
STI
Ndrift
STI
N well
N well
STI
STI
N drift I/I for N-EDMOS, can add drain I/I to suppress hole current
N well I/I
140
Deep Nwell (NISO)
P sub
STI
STI
Ndrift
STI
N well
N well
STI
STI
Pdrift
Deep Nwell (NISO)
P sub
N well
N well
STI
Pdrift
STI
P well
STI
STI
Ndrift
P well
STI
P drift I/I for P-EDMOS
P well I/I
141
Deep Nwell (NISO)
P sub
N well
N well
STI
Pdrift
STI
P well
STI
STI
Ndrift
P well
STI
Deep Nwell (NISO)
P sub
N well
N well
STI
Pdrift
STI
P well
STI
STI
Ndrift
P well
STI
Gate oxidation
Poly-silicon gate deposition and litho
142
Deep Nwell (NISO)
P sub
N well
N well
STI
Pdrift
STI
P well
STI
STI
Ndrift
P well
STI
Deep Nwell (NISO)
P sub
N well
N well
STI
Pdrift
STI
P well
STI
STI
Ndrift
P well
STI
N-type lightly doped drain I/I
P-type lightly doped drain I/I
143
Deep Nwell (NISO)
P sub
N well
N well
STI
Pdrift
STI
P well
STI
STI
Ndrift
P well
STI
n+
n+
n+
n+
n+
Deep Nwell (NISO)
P sub
N well
N well
STI
Pdrift
STI
P well
STI
STI
Ndrift
P well
STI
n+
n+
n+
n+
n+
p+
p+
p+
p+
p+
N+ I/I
P+ I/I, can add p-bury layer underneath the source as shunt resistant
144
Deep Nwell (NISO)
P sub
N well
N well
STI
Pdrift
STI
P well
STI
STI
Ndrift
P well
STI
n+
n+
n+
n+
n+
p+
p+
p+
p+
p+
Metal CNT
N-MOS
P-MOS
N-EDMOS
P-EDMOS
145
Appendix III General EDMOS Design Considerations
A3.1 Introduction
The electrical characteristics of semiconductor devices can be solved by numerical
methods using MEDICI software. Without considering the carrier temperature effect and
lattice temperature effect, the Poisson’s equation and continuity equation are referred to
as the semiconductor’s fundamental equations. They constitute the core of all numerical
simulators.
2 s
s
Eρ ρ
φε
+∇ = − = −∇⋅ (A3.1)
Whereφ is the electric potential, E is the electric field , ρ is the sum of the electron and
hole concentrations, plus the concentrations of the ionized doping atoms, sρ is the
surface charge density that may be present due to fixed charge in insulating materials or
charged interface states, and sε is the permittivity of the semiconductor.
( )D Aq p n N Nρ + −= − + − , (A3.2)
The continuity equations for electrons and holes also govern the electrical behavior:
1n n
nJ U
t q
∂= ∇⋅ −
∂ (A3.3)
1p p
pJ U
t q
∂= − ∇ ⋅ −
∂ (A3.4)
nJ and pJ represent the electron current density and hole current density, respectively.
nU and pU are the net recombination rate for electrons and holes, respectively.
For a numerical method to solve the IV characteristics, these differential equations
are discretized in a simulation grid. The resulting set of algebraic equations is coupled
146
and nonlinear. Consequently the equations cannot be solved directly in one step. Instead,
starting from an initial guess, the equations must be solved by a nonlinear iteration
method. Each equation is integrated over a small volume enclosing each node, yielding
nonlinear algebraic equations for the unknown variables. The integration equates the flux
entering the volume with the sources and drains inside it, so that conservation of relevant
flux is built into the solution. The integrals involved are performed on an element-by-
element basis, leading to a simple and elegant way of handling general surfaces and
boundary conditions.
A3.2 Device Design and Simulation
All the device structures and doping profiles are simulated and optimized using the
process simulator, TSUPREM4 [1]. The electrical characteristics such as breakdown
voltage, resistance and threshold voltage are optimized with the aid of the 2D device
simulator MEDICI [2].
A3.2.1 Design Considerations for High Voltage Devices
Most power devices are used as switches operating between on and off states. During
the off-state, the maximum voltage applied to the terminal determines the range of
operating voltage. This voltage is often referred to as the breakdown voltage. The
mechanisms responsible for avalanche breakdown, surface breakdown, gate oxide
breakdown and punch-through breakdown are important design issues that need to be
considered.
During the on-state, the on-resistance of the device between the source and drain
terminals is the main consideration. The on-resistance determines both the on-state power
loss and to some extent the switching speed (due to RC delay at the output terminal) of
the device. In order to reduce cost, the area of the device should also be minimized. The
147
on-state performance of a high voltage device is commonly measured by the specific on
resistance, Ron,sp measured in mΩ·mm2.
A3.2.2 Breakdown Voltage
When the drain or gate bias voltages are pushed beyond their specific limit, device
degradation due to channel hot carrier effects arise. Channel hot carrier effects are
generated by carriers that drift across the channel region and enter the high field region of
the drain junction. These carriers acquire sufficient kinetic energy under the influence of
a large drain voltage and can cause impact ionization. Some of them can even overcome
the Si-SiO 2 interface barrier and tunnel into the gate oxide [3]. The effects of channel hot
carriers in and n-channel MOSFET are shown in Figure A3.1. The impact ionization
from the hot carriers can lead to the generation of the substrate and gate current.
Figure A3.1 Effect of channel hot carriers.
High Vd High Vg
gate
p substrate
n+ n+
p well
drift region
n+ n+
p well
Vsource=0V
148
Channel hot carrier effects not only cause long term reliability problems, but also lead to
destructive breakdown mechanisms such as avalanche breakdown, surface breakdown,
snapback breakdown and gate oxide breakdown. These breakdown mechanisms should
be avoided when designing high voltage devices.
Avalanche Breakdown
In a reverse biased pn junction, the high electric field in the depletion layer will
sweep any electron or hole out of this region. If the kinetic energy of an electron is high
enough (typically higher than 1.3eV in silicon), its collision with the semiconductor
crystal lattice can generate secondary electron-hole pairs. This effect is called impact
ionization. It can become an avalanche process since each incoming carrier can initiate
the creation of a large number of new carriers [4]. An avalanche breakdown is defined as
the condition under which the impact ionization rate becomes infinite. This usually
occurs when the peak electric field of the depletion layer reaches the critical electric field
of silicon. The peak electric field for an abrupt one-side junction is defined by Equation
A3.6,
02 ( )o s Rn d
D
V Vw w
qN
ε ε +≈ = (A3.5)
02 ( )
D BRcrit
o s
qN V VE
ε ε
+= (A3.6)
Where DN and nw are the doping concentration and the depletion width of the lightly
doped side of the junction, respectively. 0V is the contact potential. As noted in Equation
A3.6, the peak electric field inside the depletion layer increases with the increase in
doping concentration. Since breakdown occurs when the electric field reaches the critical
149
field, critE , the relationship between the electric field and the breakdown voltage can be
found by substituting Equation A3.6 into Equation A3.5. Equation A3.7 shows that the
breakdown voltage increases as the doping concentration decreases.
2( )
2
crit
D
EBV
qN
ε= (A3.7)
Surface Breakdown
The presence of surface charge has a strong influence on the shape of the depletion
layer. The presence of positive surface charge can cause the depletion layer at the surface
of the lightly doped side to extend further away from the junction as it compensates for
the charge of the depletion layer. This leads to a reduction of the electric field strength
and hence a higher breakdown voltage. The presence of negative surface charge will have
the opposite effect. In order to overcome the effect of the surface charge, which is
introduced during the thermal growth of SiO2 in the fabrication process, field plate
compensation can be used. Placing a metal field plate at the edge of the planar junction
will influence the depletion layer curvature by altering the surface potential.
Figure A3.2 Planar diffused junction with field plate at the edge.
p-body
n-epi
n+ substrate
- - - - - - - - - - - - - - - - - - -n+
DepletionRegionExtension
p-body
n-epi
n+ substrate
++++++++++++++++++++++++
n+
DepletionRegionRetardation
V<0V V>0V
(a) (b)
150
When the junction is reverse-biased as illustrated on the left-hand side in Figure A3.2(a),
an accumulation layer is formed at the surface of the substrate, forcing the depletion layer
to shrink. The result is an increase in the electric field strength in the “corner region” that
can decrease the breakdown voltage of the junction. When the field plate is positively
biased, a depletion layer is formed at the surface and the electric field spreads over the
substrate region as shown on the right in Figure A3.2(b). The breakdown voltage
increases in this case [5]. In the actual devices, it is impractical to provide a separate
electrode to bias the field plate. Therefore, it is preferable to create the field plate by
extending the junction metallization over the oxide, as shown in Figure A3.3. The
depletion layer of the junction termination extends beyond the field plate edge when the
forward bias voltage is applied. This results in a shift of the peak electric field from the
junction curvature at the surface to the bulk. The spreading of the electric field allows the
critical field to be reached at a higher applied voltage, and causes an increase in
breakdown voltage.
(a) Breakdown at the surface (b) Breakdown at the bulk
Figure A3.3 Depletion junctions with field plate formed by the gate extension.
gate
drift region
p substrate
n+
n+
p well
n+
p well
n+
p well
drift region
p substrate
n+
p well
n+
p well
n+ n+
p well
gate
151
Snapback Breakdown [6]
As shown in Figure A3.4, the presence of channel hot carriers can cause the
generation of the substrate current Isub, which in turn can lead to the generation of hole
current. This current can cause a voltage drop across the substrate resistance Rsub as
shown in Figure A3.4. This voltage drop raises the substrate potential near the source and
can forward bias the source/substrate junction. The source/substrate junction of the
MOSFET is also the emitter/base for the parasitic NPN transistor. Electrons are injected
into the substrate. The substrate current will then cause the source/substrate junction to
become even more forward biased. This triggers a positive feedback loop, causing the
current to rise exponentially. When this parasitic transistor switches on, snapback
behavior appears on the I-V characteristics of the transistor as shown in Figure A3.5. In
the case of short MOS channel, the electrons that are injected into the substrate can be
easily collected by the drain depletion layer. With both large drain and gate voltages, the
current can increase limitlessly in the parasitic bipolar transistor. Therefore, snapback
breakdown is triggered before an avalanche breakdown in this case. The effective
channel length and the bulk doping level have to be carefully chosen in order to suppress
this snapback breakdown.
Figure A3.4 N-type MOSFET with parasitic bipolar transistor.
n+ n+Gate
p substrate
P base
Source Drain
152
Figure A3.5 IV characteristics of snapback breakdown.
Gate Oxide Breakdown
When the gate bias is increased, a breakdown of the thin gate oxide may occur. Such
a bias condition can lead to channel hot carrier effects, as illustrated in Figure A3.1, due
to the high electric field across the oxide. Under the presence of hot carriers, the device
may still operate but with degradation of the device characteristics. However, if this
stress is further increased, the oxide integrity degradation may fail catastrophically [7]. In
modern CMOS technologies, these oxide films can withstand electric fields as high as
8MV/cm before breaking down. Such dielectric strength is only possible in SiO2 that is
defect free. Any contamination in the oxide may cause failure at lower electric fields. The
maximum voltage that the oxide can sustain is calculated from Equation A3.8, where oxT
and critE are the thickness and the electrical critical field of the oxide, respectively.
crit
ox
BVE
T= (A3.8)
negative resistance
Vds (V)
Ids (A)
153
Punch-Through Breakdown
Another breakdown mechanism that needs to be considered when designing high
voltage devices is punch-through breakdown. In a short channel device, the channel
doping concentration is always lower than the source and drain doping. When the drain
terminal is operating at a high voltage, it is possible that the channel region becomes
totally depleted. Carriers are then swept directly from the source to the drain region
resulting in a short between the two terminals. In order to avoid the punch-through
condition, the doping concentration of the channel must be carefully selected. Another
method is to use a relatively long channel length to achieve higher punch-through voltage
at the expense of an increase in channel resistance.
Figure A3.6 Punch-through breakdown.
A3.2.3 Specific On-resistance
Current flow in a high voltage device during forward conduction is limited by its on-
resistance Ron. The on-resistance is the total resistance between the source and drain
contacts when the device is turned on. Ron determines the DC conduction loss in the high
drift region
p substrate
n+ n+
p well
gate Vsource=0V High Vd
154
voltage device. It can be reduced by connecting many devices in parallel. However, the
chip area will accordingly be increased and hence result in higher cost. Therefore, in
order to have an accurate representation of the performance of high voltage devices
during the on-state, specific on-resistance is used.
In high voltage devices such as Extended Drain MOSFET (EDMOS), the on-
resistance consists of the sum of the contact resistance, channel resistance and the drift
region resistance. Figure A3.7 shows a typical EDNMOS device and all of its resistive
components.
Figure A3.7 Resistive components of EDMOS.
The contact resistance is usually much smaller than the channel and drift region
resistance. Therefore, it is usually neglected. The channel resistance Rch can be expressed
as Equation A3.9
( )
ch
n ox GS th
LR
W C V Vµ=
− (A3.9)
Where L is the channel length, W is the channel width, nµ is the surface electron
mobility, oxC is the gate oxide capacitance, oxox
ox
Ct
ε= and thV is the threshold voltage of
drift resistance Rn
n+ n+
channel resistance
gate
contact resistance contact resistance
p substrate
drift resistance Rn
n+ n+
channel resistance
gate
contact resistance contact resistance
p substrate
155
the device. From Equation A3.9, it is obvious that with a specific oxide thickness, the
channel resistance can only be reduced by minimizing the length of the channel. The
resistance in the drift region depends on the doping level and the length of the n drift
implant region. An increase in doping level or a decrease in drift region length can
minimize Rn. However, the electric field may not spread wide enough throughout the
drift region and breakdown voltage will be reduced. Therefore, it is important to optimize
the device such that the doping concentration and the length of the drift region can
achieve the lowest on-resistance for a given breakdown voltage.
A3.2.4 EDMOS Device Design
Applications such as DC/DC converters require MOSFETs with low specific on-
resistance in order to minimize the device power loss. The target voltage for the devices
designed in this thesis is 30V. The gate of these devices is usually driven directly by logic
level inputs. The extended drain MOS transistor (EDMOS) is one of the most popular
high voltage structures that is used to implement smart PIC at this voltage range.
EDMOS as shown in Figure A3.1 is adopted in this work. The EDMOS device does not
use the same mask opening for the implantation of both the well and source/drain regions.
Therefore, the self-aligned MOS channel is not available and fine lithography is required
to define the channel length. Although standard CMOS and EDMOS have different
fabrication methods, the fundamental operation principle is the same. The total drain to
source voltage drop Vds of the EDMOS device can be separated into two components as
shown in Equation A3.10.
Vds=Vdrift+Vch (A3.10)
156
The principle function of the drain drift region is to support the full reverse voltage
applied to the transistor. Avalanche breakdown of the drain junction can be improved
significantly by the use of a lightly doped drain (drift region). Since the lightly doped
drain extends laterally, the magnitude of the electric field is also important to determine
the high voltage capabilities of the device. A REduced SURface Field technique
(RESURF) [8] is usually employed to control the spreading of the depletion layer and the
magnitude of the surface electric field for higher breakdown voltage. By choosing an
appropriate drain drift region thickness and relative doping level between the channel
region and the drain drift region, the spread of the depletion layer can be controlled to
occur laterally along the drift region. The breakdown location can also be designed to
occur in the bulk region (bottom of the drift region).
A3.2.5 REduced SURace Field (RESURF) Technique
The RESURF fundamental principle can be explained with a reverse biased pn
junction diode. The diode consists of two junctions: a horizontal p-n junction and a
vertical p+n junction as shown in Figure A3.8. From Equation A3.7, lower background
doping concentration results in a higher breakdown voltage. In this case, the n epitaxial
layer has a higher doping concentration than the substrate, and hence the vertical pn
junction has a lower breakdown voltage than the horizontal junction.
With a thick epitaxial layer, the depletion region at the surface of the vertical p+n
junction is not influenced by the horizontal junction, hence breakdown voltage is
determined by the p+n junction. The electrical field strength along the surface is shown in
Figure A3.8a. When the layer becomes thinner, the depletion of the vertical p+n junction
is influenced by the horizontal junction. Consequently at the same applied voltage, the
157
depletion region stretches along the surface over a much longer distance as shown in
Figure A3.8b. The magnitude of the electric field at the surface in this case is far below
the critical field and therefore, a much higher voltage can be applied before breakdown
occurs. With further reduction in the thickness of the epitaxial layer, the surface field may
not reach the critical value even at high voltages, hence surface breakdown can be
eliminated. The breakdown of the diode is now determined by the horizontal junction and
thus the location of breakdown is shifted ideally to the bulk as shown in Figure A3.8c.
However, when the epitaxial layer becomes very thin, the electric field of the curvature at
the n+ contact strongly increases and becomes larger than the field in the bulk. The corner
breakdown occurs at a lower voltage than the ideal bulk breakdown.
n+p+
nspace charge region
p-
Esurface<Ecritical
Ebulk
n+p+
nspace charge region
p-
Esurface<Ecritical
Ebulk
(b)
n+p+ n
space charge region
p-
Esurface=Ecritical
Ebulk
n+p+ n
space charge region
p-
Esurface=Ecritical
Ebulk
(a)
158
Figure A3.8 Schematic of RESURF concept.
A minor change in the diode structure can lead to a high voltage EDMOS structure. A
conventional EDMOS device with a deep drift region usually has its breakdown occur at
the surface. The breakdown location is as shown in Figure A3.9. A RESURF EDMOS
device usually has a thinner drift region that can be totally depleted prior to breakdown
condition. The breakdown location is designed to occur in the bulk region as shown in
Figure A3.10. Detailed quantitative device design guidelines and RESURF analysis are
presented in Chapter 3.
Figure A3.9 Surface breakdown.
drift region
p substrate
n+ n+
p well
n+ n+
p well
gate n+ n+
p well
n+p+
nspace charge region
p-
Esurface<Ecritical
Ebulk
n+p+
nspace charge region
p-
Esurface<Ecritical
Ebulk
(c)
159
Figure A3.10 Bulk breakdown.
gate
drift region
p substrate
n+ n+
p well
n+ n+
p well
n+ n+
p well
160
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CMOS Technologies, Kluwer Academic Publishers, 1999.
[4] Ben G. Streetman. Solid State Electronic Devices, Prentice Hall, 1995.
[5] B. J. Baliga, High-voltage device termination techniques, IEE proceedings, Vol. 129,
no. 5, pp. 173-179, Oct. 1982.
[6] Harry A. Schafft, Second Breakdown – A Comprehensive Review, Proceedings of the
IEEE, Vol.55, No. 8, August 1967.
[7] Yong Yoong Hooi, Iskandar Idris Yaacob, Suhana Mohd Said, Richard Alan Keating,
Characterization of Tunneling Current and Breakdown Voltage of Advanced CMOS
Gate Oxide, International Conference on Semiconductor Electronics, ICSE 2004
IEEE, pp. 193-198, 2004.
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Devices and ICs, ISPSD IEEE, pp.11-18, 2000.
161
Appendix IV Technology Computer-Aided Design (TCAD)
Technology Computer-Aided Design (TCAD) refers to the use of computer
simulations to develop and optimize semiconductor processing technologies and devices.
Overview of TSUPREM4
Taurus TSUPREM4 is a 1D and 2D process simulator for developing semiconductor
process technologies and optimizing their performance. With a comprehensive set of
process models, Taurus TSUPREM4 can simulate the process steps used in fabricating
semiconductor devices, reducing the need for costly experiments using silicon. In
addition, Taurus TSUPREM4 has extensive modeling and analysis capabilities, allowing
concepts verification and devices optimization.
Advantages of TSUPREM4
The overall objective of TSUPREM4 is for designer to accurately simulate complete
fabrication sequences. The program input is a processing schedule specifying a sequence
of time, temperatures, ambient, depositions, implants, and other necessary process
specification conditions. There are a few important advantages of TSUPREM4.
1. Develop cost effective, leading-edge CMOS, bipolar, and power device
manufacturing processes.
2. Predict 1D and 2D device structure characteristics by accurately simulating ion
implantation, diffusion, oxidation, silicidation, epitaxy, etching and deposition
processing, reducing experimental runs and technology development time.
3. Analyze stress history in all layers as a result of thermal oxidation, silicidation,
thermal mismatch, etching, deposition and stress relaxation.
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4. Study impurity diffusion, including oxidation-enhanced diffusion (OED),
transient-enhanced diffusion (TED), interstitial clustering, dopant activation and
dose loss.
TSUPREM4 Simulation Examples
To see how the TSUPREM4 program works, some process steps for the fabrication of
a UMOS are presented.
Oxidation
This example illustrates the oxidation on silicon wafer. Oxidation occurs whenever a
diffusion statement specifies oxidizing ambient and exposed silicon is present in the
structure.
diffusion temp=750 t.final=1000 time=33.5 f.o2=0.15 f.n2=15
diffusion temp=1000 time=10 f.o2=0.15 f.n2=15
diffusion temp=1000 time=27 f.o2=4.5 f.n2=0 f.h2=8
diffusion temp=1000 time=5 f.n2=15
diffusion temp=1000 t.final=750 time=100 f.o2=0 f.n2=15
Figure A4.1 TS4 simulation of oxidation
Si Si
SiO2
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Implant
This example illustrates implantation of boron on silicon. The implant statement is
used to model the implantation of ionized impurities into the simulation structure.
implant boron dose=3e13 energy=120
Figure A4.2 TS4 simulation of implantation
Boron implant
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Etch
The etch command is used for etch away specific materials, the following command
etches a 2µm trench in UMOS and then etches all SiO2.
etch silicon thickness=2
etch sio2 all
Figure A4.3 TS4 simulation of etch
Si
Si
SiO2
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Deposition
The deposition statement specifies the deposition of a material on the exposed
surfaces of the existing structure. This example deposits Si3N4 films over the exposed
surfaces and then etches the top and bottom of Si3N4 films, leaving Si3N4 only on the
sidewalls.
deposition nitride thickness=0.05
etch nitride thickness=0.3
Figure A4.4 TS4 simulation of deposition
Si3N4
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Trench LOCOS Process
Trench local oxidation process can be simulated with the Si3N4 films on the sidewalls
of the trench. The process is carried out at 950 ºC for 100 minutes, vertical bird’s beak
can be formed after this process as shown in Figure A4.5.
diffusion temp=750 t.final=950 time=26.5 f.n2=15 f.o2=0.15
diffusion temp=950 time=10 f.n2=15 f.o2=0.15
diffusion temp=950 time=100 f.h2=5 f.o2=10
diffusion temp=950 time=1 f.o2=10
diffusion temp=950 time=5 f.n2=15
Figure A4.5 TS4 simulation of trench LOCOS
Si3N4
Thick SiO2, vertical
bird’s beak
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Metal Contact
Metallization for electrode contacts can also be simulated by deposition command in
TSUPREM4. The final UMOS structure after metallization is shown in Figure A4.6 (a),
the doping profile and the layer thickness can also be efficiently extracted after Tsuprem4
simulation as shown in Figure A4.6 (b).These examination features are unique
advantages of TSUPREM4 compared to conventional SIMS or TEM experimental
examinations.
deposition Al thickness=3
(a) (b)
Figure A4.6 TS4 simulation of metallization (a) and doping profile (b)
These examples are for demonstration purposes, the other commands and features of
TSUPREM4 can be found in the TSUPREM4 manual.
Metal contact
Drain
Gate Body
Source
Cut line
Polysilicon
SiO2
Silicon
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SIMS Calibration
After the initial TSUPREM4 simulation, it is necessary to calibrate the TCAD
simulation using experimental SIMS data. By adjusting the diffusion coefficient of boron
in TSUPREM4 simulation, we can perfectly fit the simulation doping profile to the
experimental SIMS data as shown from Figure 4.7(a) to 4.7(b). Other parameters, such as
impurity activation energy or transportation coefficient etc., can also be calibrated via
SIMS data. This can greatly improve the accuracy of process simulation.
Figure A4.7 Boron SIMS and simulation data before and after calibration
1.E+14
1.E+15
1.E+16
1.E+17
1.E+18
0 1 2 3 4 5 6 7 8
Distance (um)
Bo
ron
Co
ncen
trati
on
(cm
-3)
(a)
(b)
SIMS
Simulation
1E+14
1E+15
1E+16
1E+17
1E+18
0 1 2 3 4 5 6 7 8
Distance (um)
Bo
ron
co
ncen
trati
on
(cm
-3)
SIMS
Simulation
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Overview of Medici
TSUPREM4 can be used to perform the virtual fabrication of any semiconductor
device. The next step is to simulate the electrical behavior of the device. The linkage
between TSUPREM4 and the device simulator Taurus MEDICI is through the exchange
of both topographic information and arrays of data representing dopant distributions.
Taurus Medici is a 2D device simulator that simulates the electrical, thermal and
optical characteristics of semiconductor devices. A wide variety of devices including
MOSFETs, BJTs, HBTs, power devices, IGBTs, HEMTs, CCDs and photodetectors can
be simulated. Taurus Medici can be used to design and optimize devices to meet
performance goals, thereby reducing the need for costly experiments.
With the continued scaling of CMOS devices, device design and optimization become
more difficult. The vast array of advanced transport and quantum models available in
Taurus Medici allow users to perform accurate simulations of deeply scaled devices.
Advantages of Medici
For semiconductor devices, the devices characteristics are described by several cross-
coupled non-linear partial differential equations. The Possion’s equation describes the
interaction of charged particles due to electric fields, and the continuity equations
describe particle concentrations as they relate to particle fluxes, generation, and
recombination. Such device equations are cumbersome to work with by hand, making
computer-aided analysis a desirable alternative. There are a few important advantages of
Medici.
1. Analyze electrical, thermal and optical characteristics of devices through
simulation without having to manufacture the actual device.
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2. Determine static and transient terminal currents and voltages under all operating
conditions of interest.
3. Understand internal device operations through potential, electric field, carrier,
current density and recombination and generation rate distributions.
4. Investigate breakdown and failure mechanisms, such as leakage paths and hot-
carrier effects.
Medici Simulation Examples
In this section, the N-type UMOS structure in Figure A4.8 is used as an input
structure to simulate the electrical characteristics in Medici.
Figure A4.8 UMOS input structure from TS4
Since the UMOS is a majority carrier device, only the electrons fluxes are put into
calculation. The Newton’s method with Gaussian eliminate is used as the numerical
method to solve the non-linear partial differential equations.
Drain
Source
Gate
Source
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Figure A4.9 Medici simulation of gate characteristics
Comment Calculate UMOS Gate Characteristics
Symb Newton Carriers=1 Electrons
Solve V(Drain)=0.1
Solve V(Gate)=0 Elec=Gate Vstep=1 Nstep=14
Plot.1d Y.axis=I(Drain) X.axis=V(Gate)
Simulations are performed for a drain bias of 0.1V, and gate biases of 0V to 14V. The
gate electrical characteristics are shown in Figure A4.9.
UMOS: Ids vs Vgs at Vds=0.1V
0E+0
1E-6
2E-6
3E-6
4E-6
5E-6
6E-6
7E-6
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Vgs (V)
Ids(A
/µm
)
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For drain characteristics, simulations are performed with a gate bias of 3V and a drain
bias of 0V to 50V. The drain electrical characteristics are shown in Figure A4.10.
Comment Calculate Drain Characteristics
Symb Newton Carriers=1 Electrons
Solve V(Gate)=3
Solve V(Drain)=0 Elec=Drain Vstep=1 Nstep=50
Plot.1D Y.axis=I(Drain) X.axis=V(Drain)
Figure A4.10 Medici simulation of drain characteristics
Figure A4.11 Medici simulation of current flow lines
Plot.2D bound junc deplet fill scale
Contour flowline
0E+00
1E-06
2E-06
3E-06
4E-06
5E-06
6E-06
7E-06
8E-06
0 10 20 30 40 50
Vds (V)
Id (
A/u
m)
Vgs=3V
Depletion boundary
Current flow lines
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The depletion area and current flow lines can be plotted in Medici simulations as
shown in Figure A4.11. This can give researcher an intuitive insight of the device
working mechanisms which are not available from conventional electrical tests.
The 3D electrical field can also be plotted in Medici simulation as shown in Figure
A4.12.
Plot.3D E.field
The 3D simulation of UMOS can provide researcher the maximum electrical field and
the location. Therefore, researcher can optimize the device accordingly.
These examples are for demonstration purposes, the other commands and features of
Medici can be found in the Medici manual.
Figure A4.12 3D Medici simulation of electrical field
Vgs=10V
Vds=30V
