Domainers’ Top 10 Worst Practices * Bret Fausett * Eytan Elbaz * Mike Rodenbaugh * Jothan Frakes.
Part A Final Dor Obstbaum Kami Elbaz Advisor: Moshe Porian August 2012 FPGA S ETTING U SING F LASH.
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Part A Final Dor Obstbaum Kami Elbaz Advisor: Moshe Porian August 2012 FPGA SETTING USING FLASH
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Transcript of Part A Final Dor Obstbaum Kami Elbaz Advisor: Moshe Porian August 2012 FPGA S ETTING U SING F LASH.
Part A Final
Dor ObstbaumKami Elbaz
Advisor: Moshe Porian
August 2012
FPGA SETTING USING FLASH
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Content• Introduction• Top Architecture• Micro Architecture
• Testability
• GUI
• Conclusions
• Schedule• Demo in Lab
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Motivation
How can we make the connection?
Software
- Pre determined- Static
- Constantly updated- Dynamic
Hardware
Non Volatile memory
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Motivation• Hardware operates by configuration written
in the registers
registers
Hardware System
FPGA setting using FLASH system
Software HostFLASH memory
• Software writes up to date configuration in the FLASH memory
• FPGA setting using FLASH system does the connection
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
TOP Architecture
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Project Goals
• Creating Clients configured by registers that shall be updated using data stored in FLASH.
• Implementing a data structure that will be used for data storage in FLASH and for data transmission to clients.
• Setting an option for a host to read data from FLASH and write new data to it.
• Implementing strong debugging capabilities including a useful GUI
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Technical Demands
• Hardware is VHDL Implemented and burned on Altera Cyclone II FPGA on DE2 development board
• FLASH memory is spansion S29AL032D - 4MB also on DE2 development board
• FPGA – Host communication via UART protocol
• Internal communication via Wishbone protocol
• Software GUI is MATLAB implemented
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Message Pack Structure• Start Of Frame 0x3C – 1 byte• Type – Which Client – 1 byte• Length of data bytes – 1 byte• Address in FLASH memory or register
number – 3 bytes
• Data – min burst 1 byte- max burst 256 bytes
• Cyclic Redundancy Check (CRC)• End Of Frame 0xA5
Type
Length
Address
Data
Data
Data
EOF
SOF
CRC
Leng
th
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Write Transaction
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Read Transaction
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Micro Architecture
Quick Reminder:• RX path• TX path• Wishbone units• Wait Client• Leds Client• Clock and Reset
Detailed understanding:
• Display Client
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
RX path
Address
DataDataData
EOF
SOF
CRC
TypeLength
SOFType
LengthAddress
DataDataData
CRCEOF
Address
TypeLength
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
TX path
Type
Address
DataDataData
TypeLength
DataDataData
TypeAddress
Length
TypeAddress
Length
CRC
SOFEOF
DataDataData
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Wishbone communication
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Wishbone master and slave
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Wait Client
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
LEDS Client
Technical Demands:•Control 4 leds on DE2 board:
- on/off- Blinking frequency
•Operates on a 100 MHz clock•Inputs: Wishbone interface to configure registers•Outputs: 4 led_active signals
• Generics: - clk_freq_g - timer_freq_g- active_state_polarity_g
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
LEDS Client
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Clock and Reset
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Display client
Technical Demands:•VESA protocol •Operates on a 65 MHz clock•Produces 3 kinds of pictures: lines, columns, damka squares• control frame ROI and shape width and color•Supports any kind of Resolution and timing by Generics•Inputs: Wishbone interface to configure registers•Outputs: RGB, hsync, vsync, blank
1024
768
Our Configuration
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Display client
65 MHz100 MHz
Integrated from
RunLen project
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Display client
Integrated from
RunLen project
Enable Lines
Line ROILine width
RGB start val
Enable Lines
Line ROI
RGB start val
RGB
Line color diff
Line color diff
Line width
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Display client
We Want Our Frames like These:
And NOT like these:
How do we keep Synchronization when registersAre updated?
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Synthetic Data Provider
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Waveform
Wishbone transactions configures registers
Register Valid is ‘0’ while registers are updated
VESA generator requests data for a new frame
Valid Data is supplied after 1 cycle
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Testability
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Test Plan
• Write Transactions• Read Transactions• Correct Functionality of Clients• System boundaries• System Generics
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Test Environment
DUT
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Example: Generating the correct Frame-Generate a Text File with a write Transaction to Display Client- Run Simulation- Analyze the results
Wrong!
Correct
- Fix Bugs if necessary
-Run and Analyze again
DUT
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
GUIBuild the TransitionRegister
DescriptionPacket
WindowText files control
Change/Remove CRC, SOF, EOF
RX and TX debug window
Messages for user window
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
GUI and Simulations
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Synthesis Results
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Timing Results
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Debugging the hardwareProblem: First programming on FPGA…nothing happensSource: The reset button on the DE2 board is active low while our
generic for reset is active highSolution: Change the reset_activity_polarity_g generic to ‘0’.Conclusion: The ‘Programming indication led’ is found useful.
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Debugging the hardwareProblem: Writes effect only register address 0.Source: A FF was not implemented by synthesis because ‘clk’ signal
was not mentioned in a process sensitivity listSolution: Using signaltap found a bug at the address advancer
(inside clients registers)Conclusion: When a problem occurs at the hardware but not on
simulation, take a look at Quartus warnings and compilation report
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
Debugging the hardwareProblem: No DisplaySource: Forgot to allocate one pin in the pin allocation scriptSolution: Using signaltap found hardware is OK. Pin allocation script
was repairedConclusion: Double check the pin allocation script
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
What have we learned so far?• Planning and Specifying a Project• Writing reusable generic code• Protocols: UART, Wishbone, VESA• Integration of many components• Verify logic correctness using waveforms, text
files, BMP files and scripts• Testing our hardware using GUI and debug with
signaltap• Documentation of the work done• Code Review and running a project diary are
useful tools
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
ScheduleTo do… Due Date Num.
CCB specification done 1
Implement CCB 01.09 2
Test CCB in lab 10.09 3
FLASH control specification 17.09 4
Implement FLASH control 10.10 5
Full system simulation and debug 30.10 6
Extend GUI capabilities 20.11 7
Final debug in lab 10.12 8
Final Presentation 28.12 9
Introduction
Top Architecture
Micro Architecture
Testability
GUI
Conclusions
Schedule
Demo
