NEMS memory for low power application · 2014. 12. 16. · NEMS memory for low power application...
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NEMS memory for low power application Jin-Woo Han, Ph. D. [email protected] Center for Nanotechnology, NASA Ames Research Center 12/16/2014
Transcript of NEMS memory for low power application · 2014. 12. 16. · NEMS memory for low power application...
NEMS memory for low power application
Jin-Woo Han, Ph. D.
Center for Nanotechnology, NASA Ames Research Center
12/16/2014
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Moore’s (Hwang’s) Law
Moore’s Law (1965) Hwang’s Law (2002) Year Year
# of Tr.
in CPU
Memory
Capacity
Barrier Barrier
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Power Crisis in Scaling
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Gate Voltage (V)
Scaling VT, VDD
Stand-by power
KT/q doesn’t scale, lowing VT increases leakage.
Dra
in C
urr
en
t (A
)
Gate Length (um)
Passive power Gate leakage +
Subthreshold leakage
Active power
Po
wer
(W/c
m2)
Active power
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Gate Voltage (V)
Power Crisis & Steep Slope Transistor
Steep Slope FET
S < 60mV/dec
Steep Slope FETs
• I-MOS
• T-FET
• Ferroelectric FET
• NEM FET
(Nano-Electro-Mechanical)
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Steep slope device suppresses the stand-by leakage
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Nano-Electro-Mechanical Switches
Suspended-Gate Type Cantilever Type
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Our NEM Switch
G1 G2
G1 G2
Gate oxide removal and re-oxidation
Independent gate
FinFET
Fin Flip-Flop
FinFET
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IDG FinFET Nanogap DG FinFET
TEM/SEM Images
Gate-oxide removal and re-oxidation
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TEM/SEM Images
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Monolithic Integration with IDG FinFET
• (100) 8” SOI Wafer
• Channel IIP
• SiN dep. (50nm)
• Fin formation (30nm)
• SiO2 depo. (20nm)
• Poly-Si depo. (100nm)
• Poly-Si CMP
• Poly-Si patterning
• S/D IIP
• Activation
S/D Gate Fin Dielectric
• PR shelding
• SiO2 removal
Fin
SiN
BOX SiO2
Poly-Si (gate)
G1
G2
G1
G2 G1
G2 PR
* 0.18m CMOS foundry technology
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Monolithic Integration with IDG FinFET
• PR removal
• Reoxidation
• Forming gas annealing
Final device
G1
G2
G1
G2
CMOS
Functional device
IDG FinFET:
Peripheral Circuit
Nanogap DG FinFET:
Functional device
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-4 -3 -2 -1 0 1 2 3 410
-15
10-13
10-11
10-9
10-7
10-5
VG2
=0~2.5V
0.5V steps
DG mode
VG2
=0~-3V
-0.5V steps
NMOSPMOS
Dra
in c
urr
en
t, I
D (
A)
G1 voltage, VG1
(V)-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
0.0
0.2
0.4
0.6
0.8
1.0
1.2 VG1
=2~4V
0.5V steps
VG1
=-2~-4V
-0.5V steps
PMOS NMOS
Dra
in c
urr
en
t, I
D (
A)
Drain voltage, VD (V)
IV Characteristics of IDG FinFET
Back-gate factors of dVT/dVG2 ~ 0.66 at WFin = 30nm
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New NEM Switch – FinFACT*
(Fin Flip-flop Actuation Channel Transistor)
• Fin : lateral flip-flop
• G1 : driving electrode
• G2 : supportive electrode
-15 -10 -5 0 5 10 1510
-15
10-14
10-13
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
n-type
VD=0.05V
p-type
VD=0.05V
Dra
in c
urr
en
t, I
D (
A)
Gate1 voltage, VG1
(V)
S D
G1
G2
S D
G1
G2
S D
G1
G2
* J.-W. Han et al., IEEE Electron Device Letters, Jul. 2010
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Comparison with SG MOS: Off-current
S D
Gate
leakage
S D Gate
Off-state
On-state
Transfer
Curve
SG-MOSFET FinFACT
S D
G1
G2
S D
G1
G2 -3V
-3V
VG (V)
I D (
A)
VG (V) I D
(A
)
leakage Small
leakage
1V
1V
1V
1V
0V
1V
0V
1V
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Comparison with SG MOS: Pull-off
S D Gate
SG-MOSFET FinFACT
S D
G1
G2
Elastic force
of gate
Restore
(pull-off)
source
1) Elastic force of fin
2) Electrostatic force
Stiction immunity
Actuation Out-of-plane
(vertical)
In-plane
(lateral)
Spring factor Gate thickness
(single k*)
Fin width
(multiple k*)
On-state
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Comparison with Cantilever: Reliability
Cantilever FET FinFACT
S D
G1
G2
Actuation
In-use
stiction
S D Gate On-state
Free of arc &
Joule heating
Current flow
Arc welding
& Joule heating
Direction of actuation & current flow
Coupled Decoupled
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-5 0 5 10 15 2010
-15
10-13
10-11
10-9
10-7
10-5
10-3
Dra
in c
urr
en
t, I
D (
A)
G1 voltage, VG1
(V)
Ultra Low Power Nonvolatile Memory
Restoration : Elastic
Surface Adhesion
: Van Der Walls
If, fin is narrow enough,
adhesion force > Elastic force
3, 16 ( / )Spring Y Fin Fin FinF kx k E H W L
Retention of Mechanical State Hysteric I-V Curves
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Comparison of NEMS Memory
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