Multilevel Logic MinimizationMultilevel Logic Minimization-- Introduction-- Introduction

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OutlineOutline

Multi-level minimization: Multi-level minimization: technology independent technology independent local optimization.local optimization.

What to optimize: What to optimize: multi-level logic modeled as Boolean networksmulti-level logic modeled as Boolean networks

Optimization targets: Optimization targets: # of literals# of literals

What’s new: What’s new: Don’t caresDon’t cares Don’t cares in multi-level logicDon’t cares in multi-level logic

• Internal vs. externalInternal vs. external• Satisfiablity vs. observablity Satisfiablity vs. observablity

Using don’t cares for multi-level minimizationUsing don’t cares for multi-level minimization

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Boolean Network: Boolean Network: ExampleExample

A A Boolean networkBoolean network is an acyclic graph. is an acyclic graph. Each node of the graph is a gate (may not be basic).Each node of the graph is a gate (may not be basic). Each edge implies a connection between two gates.Each edge implies a connection between two gates.

Example:Example: Description of the network:Description of the network:

yy1 1 = x’= x’22 + x’ + x’33 (NAND)(NAND)

yy22 = x’ = x’44 + x’ + x’55 (NAND)(NAND)

yy33 = x’ = x’44y’y’11 (NOR)(NOR)

yy44 = x = x11 + y’ + y’33 yy55 = x = x66yy22 + x’ + x’66y’y’33

xx22xx11 xx33 xx44 xx55 xx66

yy22yy11

yy33

yy44 yy55

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Boolean Network: Boolean Network: DefinitionDefinition

A A Boolean networkBoolean network is an interconnection of Boolean is an interconnection of Boolean functions defined by a five-tuple:functions defined by a five-tuple: ff = (f = (f11,…,f,…,fnn)) n completely specified logic functions n completely specified logic functions

(gates);(gates); yy = (y = (y11,…,y,…,ynn)) n logic variables that are in one-to-one n logic variables that are in one-to-one

correspondence with f (signals of the network);correspondence with f (signals of the network); II = (I = (I11,…I,…Ipp)) p primary inputs;p primary inputs; OO = (O = (O11,…,O,…,Oqq)) q primary outputs;q primary outputs; ddXX = (d = (d11

XX,…,d,…,dqqXX)) completely specified logic functions completely specified logic functions

for the don’t care minterms on the outputs.for the don’t care minterms on the outputs.It is convenient to consider both I and O as functions. We denote It is convenient to consider both I and O as functions. We denote xx

= (x= (x11,…,x,…,xpp) = (y) = (y11,…,y,…,ypp) and ) and z z = (z= (z11,…,z,…,zqq) = (y) = (yn-q+1n-q+1,…,y,…,yn-1n-1,y,ynn) as the I-) as the I-component (primary inputs) and O-component (primary outputs) of component (primary inputs) and O-component (primary outputs) of vector y. vector y.

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Example: Example: Full AdderFull Adder

f: f: ff11 buffer,…, f buffer,…, f44 XOR, f XOR, f55 AND,…, f AND,…, f88 OR,…, f OR,…, f1010 buffer buffer

y: y: 1, 2, 3, 4, 5, 6, 7, 8, 9, 101, 2, 3, 4, 5, 6, 7, 8, 9, 10 I: I: 1,2,31,2,3 O: O: 9, 109, 10 ddXX::

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Boolean Network: Boolean Network: As a Digraph As a Digraph

G=(V,E): DAGG=(V,E): DAG V: each function is a node (node i V: each function is a node (node i ffii yyii).).

E: there is a directed edge from node i to node j if yE: there is a directed edge from node i to node j if y ii

supp(fsupp(fjj), denoted by (i,j) ), denoted by (i,j) E.E.

If (i,j) If (i,j) E, node i is a E, node i is a predecessor (input, fanin)predecessor (input, fanin) of node j, and of node j, and node j is a node j is a successor (output, fanout)successor (output, fanout) of node i; of node i;

If there is a path from node i to node j, node i is a If there is a path from node i to node j, node i is a transitivetransitive predecessor (transitive fanin) of node j, and node j is a transitive predecessor (transitive fanin) of node j, and node j is a transitive successor (transitive fanout) of node i. successor (transitive fanout) of node i.

PPii = {j = {jV | (j,i) V | (j,i) E}E} SSii = {j = {jV | (i,j) V | (i,j) E} E}

PPii** = {j = {jV | node j is a transitive fanin of node i}V | node j is a transitive fanin of node i}

SSii** = {j = {jV | node j is a transitive fanout of node i}V | node j is a transitive fanout of node i}

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Example: Example: Full AdderFull Adder

PP44={1,2},={1,2}, PP88={5,7},={5,7}, PP99={6},={6}, PP22==

SS44={6,7},={6,7}, SS88={10},={10}, SS99==,, SS22= {4,5}= {4,5}

PP44**={1,2},={1,2}, PP88

**={1-5,7},={1-5,7}, PP99**={1-4,6},={1-4,6}, PP22

**==

SS44**={6-10},={6-10}, SS88

**={10},={10}, SS99**==,, SS22

**= {4-10}= {4-10}

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Boolean Network: Boolean Network: Net and ConnectionNet and Connection

Each signal in the Boolean network represents Each signal in the Boolean network represents the voltage on a segment of interconnect/wire in the voltage on a segment of interconnect/wire in the circuit that implements the Boolean network. the circuit that implements the Boolean network. This wire segment is referred as a This wire segment is referred as a netnet. . The logic value on a net is determined by the The logic value on a net is determined by the source source

terminalterminal, a logical signal corresponding to a specific , a logical signal corresponding to a specific node ynode yii in the Boolean network. in the Boolean network.

Inputs to the nodes in the fanout SInputs to the nodes in the fanout Sii are are sink terminalssink terminals.. Source and sink terminals are called Source and sink terminals are called pinspins of the net. of the net.

Each edge (i,j) Each edge (i,j) E is also called a E is also called a connectionconnection, , denoted by cdenoted by cijij with a logic variable y with a logic variable y ijij.. PPijij = i, S = i, Sijij = j, P = j, Pijij

* * = P= Pii**{i}, S{i}, Sijij

** = S = Sjj**{j}{j}

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Example: Example: Full AdderFull Adder

XOR gate 6 produces logical signal yXOR gate 6 produces logical signal y66; its output ; its output is the source terminal of corresponding net; this is the source terminal of corresponding net; this net has a single sink terminal on the input of net has a single sink terminal on the input of buffer 9.buffer 9.

For the connection CFor the connection C6,96,9 from 6 to 9, we have: from 6 to 9, we have:PP6,96,9=6, S=6, S6,96,9=9, P=9, P6,96,9

**=P=P66* * {6}={1-4,6}, S{6}={1-4,6}, S6,96,9

** = S = S99**{9}=9{9}=9

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Boolean Network: Boolean Network: Global FunctionsGlobal Functions

FunctionsFunctions f fii(y)(y) are are local functionslocal functions in that they in that they

are specified by the neighbors of node i in the are specified by the neighbors of node i in the Boolean network.Boolean network.

The The global functionsglobal functions ffii*(x)=*(x)=(I,f(I,fii(y))(y)) are defined on are defined on

a subset of primary inputs, where the a subset of primary inputs, where the composition operator composition operator is defined recursively as: is defined recursively as:

ffii(((A,f(A,fPi(1)Pi(1)), ), (A,f(A,fPi(2)Pi(2)),…, ),…, (A,f(A,fPi(|Pi|)Pi(|Pi|))))) otherwiseotherwise

ffii if Pif PiiAA

yyii if iif iAA

(A,f(A,fii(y)) = (y)) =

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Example: Example: Full AdderFull Adder

ff33** = = (I,f(I,f33) = y) = y33

ff55** = = (I,f(I,f55) = f) = f55 = y = y11yy22

ff99** = = (I,f(I,f99) = ) = (I,f(I,f66) = XOR() = XOR((I,f(I,f44), ), (I,f(I,f33)) ))

=XOR(XOR(=XOR(XOR((I,f(I,f11),),(I,f(I,f22)),y)),y33) ) =XOR(XOR(y=XOR(XOR(y11,y,y22),y),y33) )

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Multilevel Logic MinimizationMultilevel Logic Minimization-- Don’t Care Conditions-- Don’t Care Conditions

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Don’t Cares: Don’t Cares: Satisfiability Don’t CareSatisfiability Don’t Care

Satisfiability don’t care (SDC)Satisfiability don’t care (SDC) occurs when occurs when certain input combination to a circuit can never certain input combination to a circuit can never occur.occur.

How it happens?How it happens? We may represent a node using both primary inputs We may represent a node using both primary inputs

and intermediate variables. (Band intermediate variables. (Bn+mn+m)) The intermediate variables depend on primary inputs.The intermediate variables depend on primary inputs. So, not all the minterms of BSo, not all the minterms of Bn+m n+m can occur.can occur.

Example:Example: y = a+b, then {y=0, a=1, b=-} will never occur (SDC).y = a+b, then {y=0, a=1, b=-} will never occur (SDC).

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Computing SDCsComputing SDCs

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where,)(:as defined is variableteintermedia theSuppose

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Example: Example: Minimization Using SDCsMinimization Using SDCs

Introduce intermediate variable Introduce intermediate variable gg at node 9. at node 9. Cannot do resubstitution since Cannot do resubstitution since F/g = 0F/g = 0.. What is the difference between What is the difference between bcdbcd and and bg (xor of the bg (xor of the

two)two)?? bcdg’bcdg’, , bc’g, bd’gbc’g, bd’g..

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G=a+cd

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Example: Example: Minimization Using SDCsMinimization Using SDCs

SDCSDC99=g=g(a+cd)=g’a+(a+cd)=g’a+g’cdg’cd++ga’c’ga’c’++ga’d’ga’d’ bcdg’ bcdg’ is covered by is covered by g’cdg’cd bc’gbc’g==abc’gabc’g+a’bc’g is covered by +a’bc’g is covered by aa + + ga’c’ga’c’ bd’gbd’g==abd’gabd’g+a’bd’g is covered by +a’bd’g is covered by aa + + ga’d’ga’d’

F = F = aa + bg + e + bg + e

? bcdg’,? bcdg’, bc’g, bd’g ?bc’g, bd’g ?

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Don’t Cares: Don’t Cares: Observability Don’t CareObservability Don’t Care

Observability don’t care (ODC)Observability don’t care (ODC) occurs when local occurs when local changes cannot be observed at the primary changes cannot be observed at the primary outputs.outputs.

How it happens?How it happens? Signals at pre-specified observation points (primary Signals at pre-specified observation points (primary

outputs) are outputs from some intermediate gates.outputs) are outputs from some intermediate gates. Change of some inputs to the intermediate gates may Change of some inputs to the intermediate gates may

not change the outputs.not change the outputs. So, these changes are not observable.So, these changes are not observable.

Example:Example: y = a+b, when a = 1, change on b is not observable.y = a+b, when a = 1, change on b is not observable.

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Computing ODCsComputing ODCs

Boolean differenceBoolean difference of function f w.r.t. a variable x of function f w.r.t. a variable x is defined as: is defined as: ff//x=fx=fxxffx’x’..

Example: Example: F(x,y,z) = x+yzF(x,y,z) = x+yz

FF//x = Fx = FxxFFx’x’= 1= 1yz = y’+z’yz = y’+z’

FF//y = Fy = FyyFFy’y’= (x+z)= (x+z)x = (x+z)x’+(x+z)’x = x’zx = (x+z)x’+(x+z)’x = x’z

If output F is sensitive to node y, I.e., FIf output F is sensitive to node y, I.e., FyyFFy’y’, then , then

FF//y=Fy=FyyFFy’y’=F=FyyFFy’y’’’+F+Fyy

’’FFy’y’=1=1..

Therefore, Therefore, ODCODCyy=(=(FF//y)’y)’=(F=(FyyFFy’y’)’=F)’=FyyFFy’y’+F+Fyy’’FFy’y’

’’..

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Example: Example: Minimization Using ODCsMinimization Using ODCs

yy11=a’b+ab’,=a’b+ab’, yy22=by=by11,, yy33=c’y=c’y22’’

ODCODCy1y1=(=(F/F/yy11)’=(()’=((yy33//yy22)()(yy22//yy11))’ ))’

=((0=((0c’)(bc’)(b0))’=(c’b)’=b’+c0))’=(c’b)’=b’+c K-map for yK-map for y11and and ODCODCy1y1

So ySo y11 = a’, XOR(a,b) = a’, XOR(a,b) NOT(a)NOT(a)

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0101 1111 1010

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Don’t Cares: Don’t Cares: Internal and External DCsInternal and External DCs

Internal Don’t CaresInternal Don’t Cares arise from the structure of arise from the structure of the network itself. the network itself. SDCSDC ODCODC

External Don’t CaresExternal Don’t Cares (XDCs) arise from the (XDCs) arise from the external environment in which the network is external environment in which the network is embedded.embedded. XSDCXSDC XODCXODCThese can be defined in the same way if we consider These can be defined in the same way if we consider

the larger network in which the Boolean network is the larger network in which the Boolean network is hierarchically embedded. hierarchically embedded.

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Don’t Cares: Don’t Cares: Complete Don’t CaresComplete Don’t Cares

The complete don’t cares (CDCs) of node i in a The complete don’t cares (CDCs) of node i in a Boolean network is given by: Boolean network is given by:

CDCCDCii=XSDC+XODC+SDC=XSDC+XODC+SDCii+ODC+ODCii