Memory Management 2 Tanenbaum Ch. 3 Silberschatz Ch. 8,9.

Memory Management 2

Tanenbaum Ch. 3

Silberschatz Ch. 8,9

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Paging implementation issues:

• The mapping from virtual address to physical address must be fast.

• If the virtual address space is large, the page table will be large.

Speeding Up Paging

Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639

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Translation look-aside Buffers (TLB)

• Also known as associative registers

• High speed cache used to store recent page accesses

• Supports parallel search algorithmpage # | frame #

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Figure 3-12. A TLB to speed up paging.

Translation Lookaside Buffers


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Paging Hardware with TLB

CPU

PhysicalMemory

PageTable

f

p{

p d

d

logical address

physical addressTLB

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CPU

PhysicalMemory

PageTable

f

p{

p d

df

logical address

physical addressTLB

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CPU

PhysicalMemory

PageTable

f

p{

p d

df

logical address

physical addressTLB

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TLB Performance

• Frequency with which address is found in TLB is known as hit ratio – Hit ratio depends on many things, including #

of TLBs– higher is better...

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TLB Performance

• Frequency with which address is found in TLB is known as hit ratio – Hit ratio depends on many things, including #

of TLBs– higher is better...

• Example:– Hit ratio = 80%, TLB access time = 2 ns,

memory access = 20 ns.

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TLB Performance

• Frequency with which address is found in TLB is known as hit ratio – Hit ratio depends on many things, including # of

TLBs– higher is better...

• Example:– Hit ratio = 80%, TLB access time = 2 ns, memory

access = 20 ns.

80% * 22 ns + 20% * 42 ns = 26 ns effective access time

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TLB Performance• Frequency with which address is found in TLB is

known as hit ratio – Hit ratio depends on many things, including # of TLBs– higher is better...

• Example:– Hit ratio = 80%, TLB access time = 2 ns, memory access =

20 ns.– 80% * 22 ns + 20% * 42 ns = 26 ns effective access time– Hit ratio = 98%, TLB access time = 2 ns, memory access =

20 ns.– 98% * 22 ns + 2% * 42 ns = 22.4 ns effective access time

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Memory Protection with Paging

• Every process has its own paging table

• Each paging table entry has a protection bit– valid-invalid bit– Page is valid if process is allowed to access

the associated page.– Invalid if not.

• Might also include bits for write and execute

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Memory Protection with Paging

• Every process has its own paging table• Each paging table entry has a protection bit

– valid-invalid bit– Page is valid if process is allowed to access the

associated page.– Invalid if not.

• Might also include bits for write and execute

• Problem: Paging tables can become very large

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Multi-level Paging

• Break the page number into two parts

• First paging number (p1) accesses outer table• Second paging number (p2) identifies inner table• (d) identifies the displacement within the page

P1 P2 d

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Multi-level Paging

• Break the page number into two parts

• First paging number (p1) accesses outer table• Second paging number (p2) identifies inner table• (d) identifies the displacement within the page

p1 p2 douter-page table inner-page

table physicalmemory

p1

p2

P1 P2 d

d

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Multilevel Page Tables

Figure 3-13. (a) A 32-bit address with two page table fields. (b) Two-level page tables.

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Performance of Multi-level Paging

• Each memory access now requires 3 (or more) accesses to physical memory.

• Benefit of TLBs now even more important.

• Hit ratio even more important

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Performance of Multi-level Paging

• Each memory access now requires 3 (or more) accesses to physical memory.

• Benefit of TLBs now even more important.• Hit ratio even more important• Example: 4 level paging (Motorola)

– Hit ratio = 98%, TLB access time = 2 ns, memory access = 20 ns.

98% * 22 ns + 2% * 102 ns = 23.6 ns effective access time

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Inverted Page Table• One Page table per system

CPUPhysicalMemory

di

pid p

logical address physical address

pid p d

i

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Inverted Page Table• One Page table per system

• Uses hash table to access table

CPUPhysicalMemory

di

pid p

logical address physical address

pid p d

i

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Figure 3-14. Comparison of a traditional page table with an inverted page table.

Inverted Page Tables


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Theories of Program Behavior

• All replacement algorithms try to predict the future

• All replacement algorithms have a theory of how programs behave– Theory is used to predict future behavior of

the process (when the page will be referenced)

– Then replace page that will not be used for the longest time.

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• Optimal page replacement algorithm• Random page replacement• Not recently used page replacement• First-In, First-Out page replacement• Second chance page replacement• Clock page replacement • Least recently used page replacement• Working set page replacement• WSClock page replacement

Page Replacement Algorithms


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Random Page-replacement

• Randomly pick a page to replace

• Theory: Since we can't predict the future, why try.

• Implementation is easy

• Performance: poor

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FIFO Page-replacement Algorithm

• Maintain a queue of pages. Always replace the page that has been in memory the longest

• Theory: Pages are used for a while and then not used.

• Implementation is very easy• Performance is poor...

– old pages are still used

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Expected Page Fault Behavior#

of P

age

Fau

lts

Number of Frames

FIFO Example – Program - 5 pages,

3 frames of Memory allocated

123

1 2 3 4 1 2 5 1 2 3 4 5

1 12

423

413

412

512

512

512

532

534

534

123

1 2 3 4 1 2 5 1 2 3 4 5

1 12

423

413

412

512

512

512

532

534

534

9faults



123

1 2 3 4 1 2 5 1 2 3 4 5

1 12

423

413

412

512

512

512

532

534

534

1234

1 12

123

1234

1234

5234

5134

5124

5123

4123

4523

10faults



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Belady's Anomaly#

of P

age

Fau

lts

Number of Frames

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Figure 3-15. Operation of second chance. (a) Pages sorted in FIFO order. (b) Page list if a page fault occurs at time 20 and A has its R bit set. The numbers above the pages are their load times.

Second Chance Algorithm


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Figure 3-16. The clock page replacement algorithm.

The Clock Page Replacement Algorithm


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Working Set

• The set of pages that a process is “currently referencing”

• Based on concept of Locality of Reference• Generally modeled using a Working Set

Window which is a time period during which the range of page references are monitored.– May be a specific time interval (# of instructions)– May be a specific number of page references

• Example - Sort 3 different arrays.

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Working Set Evolution

Size ofthe workingset

Time

Stable Working Set

Stable Working Set

Stable Working Set

Transition

Transition

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Figure 3-19. The working set is the set of pages used by the k most recent memory references. The function w(k, t) is the

size of the working set at time t.

Working Set Page Replacement (1)


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Figure 3-20. The working set algorithm.

Working Set Page Replacement (2)


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Thrashing• If process does not have "enough" pages, page

fault rate goes up. This leads to:– low CPU Utilization– CPU thinks it needs to increase the degree of

multiprogramming– Another process is added– More processes reduces the number of frames available

to each process

• Thrashing occurs when a process is spending more time managing page faults than processing.

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Thrashing Diagram

thrashing

degree of multiprogramming

CP

U u

tili

zati

on

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Thrashing

• Why does paging work?– locality of reference– Process migrates from one locality to another– Localities may overlap

• Why does thrashing occur? (size of locality) > total memory size

• Solution!– if thrashing occurs, suspend a process

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When the hand comes all the way around to its

starting point there are two cases to consider:

• At least one write has been scheduled.• No writes have been scheduled.

The WSClock Page Replacement Algorithm (1)


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Figure 3-21. Operation of the WSClock algorithm. (a) and (b) give an example of what happens when R = 1.



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Figure 3-21. Operation of the WSClock algorithm. (c) and (d) give an example of R = 0.



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Figure 3-22. Page replacement algorithms discussed in the text.

Summary of Page Replacement Algorithms


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Summary

• Translation Look-aside Buffers

• Multi-level Paging Tables

• Page Replacement Algorithms

• Working Sets

• Page Fault Behavior– Thrashing– Belady’s Anomaly

Questions

• How are TLBs used to improve main memory performance? What is the effective access time for a system with 2 ns TLBs, 20 ns memory access time, and a hit rate of 98%?

• Page tables are needed to find physical addresses in paging systems. What is the major disadvantage of paging tables, and how do modern operating systems get around this disadvantage?

• How much memory would be needed for a 1 MB program using a single level page table (32 bit address space, 4 bytes per page, 4kb pages)? How much would be needed for a 4 level page table?

• What is Belady's Anomaly? • What is a working-set model? How does it help determine the

allocation of frames of main memory to active processes? • What is thrashing in the context of virtual memory?

Memory Management 2 Tanenbaum Ch. 3 Silberschatz Ch. 8,9.

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Transcript of Memory Management 2 Tanenbaum Ch. 3 Silberschatz Ch. 8,9.