MC9211 Computer Organization

Unit 2 : Combinational and Sequential Circuits

Lesson1 : Combinational Circuits

(KSB) (MCA) (2009- 12/ODD) (2009 - 10/1 A&B)

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Coverage – Lesson1

Outlines the formal procedures for the analysis and design of combinational circuitsSome basic components such a adders and code converters are introduced as design examplesFrequently used logic functions like parallel adders and subtractors, decoders , encoders ,multiplexers and demultiplexers are explained

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Lesson1 – Combinational Circuits

1. Introduction2. Design Procedure3. Binary Adder Subtractor4. Comparators5. Decoders - Demultiplexer6. Encoders7. Multiplexers

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1. IntroductionA combinational circuit consists of input

variables, logic gates and output variablesCombinational circuits react to the values of

signals at their inputs and produce the value of the output signal , transforming binary information from the given input data to a required output data

For n input variable there will be 2n binary input combinations, for each input value there will be one output value

Combinational circuit can be specified by truth table or Boolean functions

Combinational Circuits

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2.Design ProcedureDesign of combinational circuits starts from the

verbal outline of the problem and ends in logic circuit diagram or a set of Boolean functions.

The steps involved are:1.State the problem2.The number of available input variables and

required output variables is determined3.The input and output variables are assigned

letter symbols

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Design Procedure (contd..)

4.The truth table that defines the required relationships between inputs and outputs is derived

5.The simplified Boolean function for each output is obtained

6.The logic diagram is drawn

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Code Conversion ExampleInput- BCD Output-Excess 3 Code

A B C D W X Y Z0 0 0 0 0 0 1 10 0 0 1 0 1 0 00 0 1 0 0 1 0 10 0 1 1 0 1 1 00 1 0 0 0 1 1 10 1 0 1 1 0 0 00 1 1 0 1 0 0 10 1 1 1 1 0 1 01 0 0 0 1 0 1 11 0 0 1 1 1 0 0

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1 1

1 1

d d

1 d

AB

CD00 01 11 10

00

01

11

10

1 1

1 1

d d d d

1 d d

AB

CD00 01 11 10

00

01

11

10

Y=CD+C’D’

1 1 1

1 1

d d d d

1 d d

AB

CD00 01 11 10

Z=D’

00

01

11

10

1 1 1

d d d d

1 1 d d

AB

CD00 01 11 10

00

01

11

10

X=B’C+B’D+BC’D’ W=A+BC+BDTruth Table for all outputs

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3.a)Binary Adder The simple addition consists of four possible

elementary operations0+0 = 0 0+1=1 1+0=1 1+1= 10 (0 with carry)A combinational circuit that performs the addition

of two bits is called half adderA combinational circuit that performs addition of

three bits (two significant bits and a carry) is called full adder

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers

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x y C S0 0 0 00 1 0 11 0 0 11 1 1 0

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Full Adderx y z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

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3 b)Binary SubtractorThe simple subtraction consists of four possible elementary operations

x y Borrow B

Difference D

0 0 0 00 1 1 11 0 0 11 1 0 0

x Minuendy Subtrahend

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Half SubtractorA half subtractor is a is a combinational circuit that subtracts two bits and produces their differenceThe truth table is shown in the previous slide and the equations are:

D=x’y+xy’B=x’y

A combinational circuit that performs subtraction of three bits (two significant bits and a borrow) is calledfull subtractor

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Full Subtractor

x y z B D0 0 0 0 00 0 1 1 10 1 0 1 10 1 1 1 01 0 0 0 11 0 1 0 01 1 0 0 01 1 1 1 1

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Full Subtractor (contd..)The Boolean Functions for full subtractor are

D=x’y’z+x’yz+xy’z’+xyzB=x’y+x’z+yz

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Binary adder

Binary adder that produces the arithmetic sum of binary numbers can be constructed with full adders connected in cascade, with the output carry from each full adder connected to the input carry of the next full adder in the chain

Note that the input carry C0 in the least significant position must be 0

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Binary Adder

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Binary AdderFor example to add A= 1011 and B= 0011

subscript i: 3 2 1 0Input carry: 0 1 1 0 CiAugend: 1 0 1 1 AiAddend: 0 0 1 1 Bi

--------------------------------Sum: 1 1 1 0 Si

Output carry: 0 0 1 1 Ci+1

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Binary Subtractor

The subtrcation A – B can be done by taking the 2’s complement of B and adding it to A because A- B = A + (-B)

It means if we use the inverters to make 1’s complement of B (connecting each Bi to an inverter) and then add 1 to the least significant bit (by setting carry C0 to 1) of binary adder, then we can make a binary subtractor.

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4 bit 2’s complement Subtractor

= 1

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Adder SubtractorThe addition and subtraction can be combined

into one circuit with one common binary adder (see next slide).

The mode M controls the operationWhen M=0 the circuit is an adderWhen M=1 the circuit is subtractorIt can be don by using exclusive-OR for each Bi

and MNote that 1 ⊕ x = x’ and 0 ⊕ x = x

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Checking Overflow

Note that in the previous slide if the numbers are considered to be signed V detects overflow

V=0 means no overflow and V=1 means the result is wrong because of overflow

Overflow can occur when adding two numbers of the same sign (both negative or positive) and result can not be accommodated with in the available bits

It can be detected by observing the carry into sign bit and carry out of sign bit position

If these two carries are not equal it results in overflow

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4. ComparatorA magnitude comparator is a combinational

circuit that compares two numbers A and B and determines their relative magnitudes

Outcome of the comparison is specified by Binary variables that indicate whether A > B, A = B or A < B

The circuit for comparing two n-bit numbers has 22n entries in the truth table which makes it cumbersome

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Comparator (contd..)A1 A0 B1 B0 E0 0 0 0 10 0 0 1 00 0 1 0 00 0 1 1 00 1 0 0 00 1 0 1 10 1 1 0 00 1 1 1 0

A1 A0 B1 B0 E1 0 0 0 01 0 0 1 01 0 1 0 11 0 1 1 01 1 0 0 01 1 0 1 01 1 1 0 01 1 1 1 1

E= A’1A’0B’1B’0 + A’1A 0B’1B 0 + A 1A 0B 1B 0 + A 1A’0B 1B’0 Example of comparison of two 2 bit numbers for equivalence

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Comparator (contd..)In order to reduce the complexity we will use

algorithmic approachAn algorithm is a procedure that specifies a finite

set of steps, that, if followed, give the solution to a problem

For example, consider two numbers with four digits A = A3A2A1A0 and B = B3B2B1B0

The two numbers are equal if all pairs of signi-ficant digits are equal ie A3 = B3, A2= B2,

A1 = B1, and A0 = B0

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Comparator (contd..)This can be expressed logically by an equi-

valence functionxi = AiBi + A’iB’i for i = 0,1,2,3 where xi = 1

only if a pair of bits in a position i are equalNumbers A and B are equal, which is represented

by binary variable E, only if x3x2x1x0 = 1To determine if A > B or A < B, we inspect pairs

of significant digits starting from most significant bit position – if the two digits are equal, we compare the next lower significant pair of digits

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Comparator (contd..)

This comparison continues until a pair of unequal digits is reached

If the corresponding digit of A is 1 and that of B is 0, we conclude A > B

If the corresponding digit of A is 0 and that of B is 1, we conclude A < B

G(A>B) = A3B’3+x3A2B’2+x3x2A1B’1+x3x2x1A0B’0

L(A<B) = A’3B3+x3A’2B2+x3x2A’1B1+x3x2x1A’0B0

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5. DecodersA decoder is a combinational circuit that converts

binary information from n input lines to a maximum of 2n unique output lines – if the n bit decoded information has don’t care combinations, the decoder output will have less than 2n outputs

The decoders are called n-to-m line decoders where m <= 2n

Their purpose is to generate the 2n minterms of n input variables

Other name used for decoder is code converter

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Decoder (contd..)

3-to-8 linedecoder

3 inputlines

Enable line

8 outputlines

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Decoder with Enable Line

Decoders usually have an enable line,If enable=0 , decoder is off. It means all output

lines are zeroIf enable=1, decoder is on and depending on

input, the corresponding output line is 1, all other lines are 0

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Example: 3-to-8 line decoderInputs Outputs

x y z D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1

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Combinational Logic Implementation

A decoder provides the 2n minterms of n input variables

Any Boolean function can be represented in sum of minterms canonical form

Decoder can then be used to generate the minterms and an external OR gate can be used to form the sum

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Application of DecoderDecoder is used to implement any combinational circuit ( F n )For example the truth table for full adder is S (x,y,z) = ∑ ( 1,2,4,7)and C(x,y,z)= ∑ (3,5,6,7). The implementation with decoder is:

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4 X 16 decoder using 3 X 8 Decoders

3 X 8decoder

3 X 8decoder

xy

z

w

D0 to D7

D8 to D15

E

E

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DemultiplexerA demultiplexer is a circuit that receives

information on a single line and transmits this information on one of 2n possible lines

The selection of a specific output is controlled by the bit values of n selection lines

1 X 4demultiplexer

D0

D1E

input D2

D3

A BSelect

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6. EncodersAn encoder is a digital circuit that performs the

inverse operation of a decoderAn encoder has 2n (or fewer) input lines and n

output linesThe output lines generate the binary code

corresponding to the input valueExample: Octal to Binary Converter has eight

inputs, one for each of the octal digits and three outputs that generate the corresponding binary number

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Example: Octal to Binary EncoderInputs Outputs

D0 D1 D2 D3 D4 D5 D6 D7 X Y Z1 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1

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Octal Binary converter Boolean Functions

From the truth table we can obtain the Boolean Functions directlyx = D4 + D5 + D6 + D7

y = D2 + D3 + D6 + D7

z = D1 + D3 + D5 + D7

This can be implemented using three OR gatesWhat is the output when all inputs are 0? What

is the output only when D0 is equal to 0? How to distinguish between the two? What happens if two inputs are present simultaneously ?

Priority EncoderA priority encoder is an encoder circuit that includes the priority functionIf two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence

Inputs OutputsD0 D1 D2 D3 x y V0 0 0 0 x x 01 0 0 0 0 0 1x 1 0 0 0 1 1x x 1 0 1 0 1x x x 1 1 1 1

If all inputs are 0, there is no valid input. For detecting this situation weconsider a third output named V.V is equal to 0 when all inputsare 0 and is 1 for rest of the situations

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2-bit Priority Encoder

By using Truth Table and K-map we get following Boolean functions for 4-input (or 2-bit) priority encoder:

X = D2 + D3

Y = D3 + D1D’2V= D0 + D1 + D2 + D3

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7. MultiplexersA multiplexer is a combinational circuit that

selects binary information from one of many input lines and directs it to a single output line

The selection of a particular input line is controlled by a set of selection lines

Normally there are 2n input lines and n selection lines whose bit combinations determine which input is selected

Multiplexing means transmitting a large number of information units over a smaller number of channels

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4 X 1MUX Output

Inputs

Select

(c) Block Diagram

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MUX may have enable input to control operation of the unit – when E = 0 all outputs are disabled- when E = 1, circuit functions in a normal stateEnable can be used to expand two or more MUX’s

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Boolean Function ImplementationAnother method for implementing Boolean function is

using multiplexerFor doing that assume Boolean function has n+1

variables We take n of these variables and connect them to

selection lines of MUXThe remaining single variable of the function is used for

the inputs of the MUX If A is the variable the inputs of MUX are chosen as A

or A’By judicious use of these variables for inputs and by

connecting the other variables to the selection lines, one can implement any Boolean function with a MUX

Example: Implementation of function with three variables F(A,B,C) = ∑(1,3,5,6) is shown on next slide

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Minterm A B C F0 0 0 0 01 0 0 1 12 0 1 0 03 0 1 1 14 1 0 0 05 1 0 1 16 1 1 0 17 1 1 1 0

4 X 1MUX

S0S1I3

I2

I1

I0

Y

0

1F

A

A’

B

C

MUX Implementation

I0 I1 I2 I3A’ 0 1 2 3A 4 5 6 7

0 1 A A’ Truth Table

Implementation Table

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Implementation 1.Express the function in its sum of minterms form2.Assume that the ordered sequence of

variables chosen for the minterms is ABCD----, where A is the left most variable in the ordered sequence of n variables and BCD---- are the remaining n-1 variables

3.Connect the n-1 variables to the selection lines of the MUX, with B connected to the high order selection line, C to the next lower selection line, and so on down to the last variable

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Implementation (contd..)4.Consider now the single variable A, it is

complemented in the 1st half minterms in the truth table and and uncomplemented in the 2nd

half5.List the inputs of the MUX and under them list

all minterms in two rows – the 1st row lists all those minterms where A is complemented, and the second row all the minterms with A uncomplemented

6. Circle all the minterms of the function and inspect each column separately

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Implementation (contd..)-If the two minterms in a column are not circled,

apply 0 to the corresponding MUX input-If the two minterms are circled , apply 1 to the

corresponding MUX input-If the bottom minterm is circled and the top is

not circled, apply A to the corresponding MUX input

-If the top minterm is circled and the bottom is not circled, apply A’ to the corresponding MUX input

Exercise: F(A,B,C,D) = ∑(0,1,3,4,8,9,15)