MAX 10 Development Board - TIFR

MAX 10 Development Board User Manual

Document version 1.2.2 for Max_10 Board v1.2

Contents 1. Introduction ..................................................................................................................................................3

1.1. Board Features .....................................................................................................................................3

1.2. About the kit .........................................................................................................................................3

2. Max_10_Dev Board Architecture .................................................................................................................4

2.1. Layout and Components .......................................................................................................................4

2.2. Block Diagram of the Max_10_Dev Board............................................................................................4

3. Using the Max_10_Dev Board ......................................................................................................................5

3.1. Powering the Max_10_Dev Board ........................................................................................................5

3.2. Configuring the Max 10 FPGA...............................................................................................................5

3.2.1. Configure the FPGA in JTAG mode ...............................................................................................6

3.2.2. Configure the FPGA using Internal Configuration ........................................................................6

3.3. Clock Circuitry .......................................................................................................................................6

3.4. Power Supply ......................................................................................... Error! Bookmark not defined.

3.5. User Interface .......................................................................................................................................6

3.5.1. Pushbuttons ..................................................................................................................................6

3.5.2. LEDs ..............................................................................................................................................7

3.5.3. 7-Segment LED Displays ...............................................................................................................7

3.6. Expansion Headers ...............................................................................................................................8

3.7. Pmod Connector ................................................................................................................................ 10

3.8. USB to UART Interface ....................................................................................................................... 10

1. Introduction Field Programmable Gate Arrays (FPGAs) are pre-fabricated silicon devices that can be electrically

programmed to become almost any kind of digital circuit or system. FPGAs have come a long way from the

devices that were once considered only as glue logic to the devices that can now implement complete

applications. FPGAs are now widely used for implementing digital circuits in a wide variety of markets including

telecommunications, automotive systems and consumer electronics.

The MAX-10 Development board presents a compact and low priced FPGA development platform suitable for

new comers to the FPGA world. The on-board Altera/Intel® MAX® 10 FPGA revolutionizes non-volatile

integration by delivering advanced processing capabilities in a low-cost, single chip small form factor

programmable logic device. The board is designed to be used in the simplest possible implementation

targeting the Intel/Altera MAX 10 device up to 2000 Logic Elements (LEs).

The board has a collection of interfaces including two external General Purpose Input Output (GPIO) headers

to extend designs beyond the MAX-10 board, on-board USB-to-UART device for interfacing to a PC, as well as

general user peripherals viz., Light Emitting Diodes (LEDs), 7-segment displays and push-button switches.

1.1. Board Features Altera/Intel® MAX® 10 FPGA – 10M02SCE144C8G

o 2000 Logic elements (LEs)

o 108 Embedded memory (Kbits)

o 12 User flash memory (KBytes)

o Single Internal Configuration memory

o 16 Embedded 18 x 18 multipliers

o 2 General-purpose PLLs

o 101 Maximum FPGA I/O pins

Configuration Status and Set-Up Elements

o On-board USB-Blaster compatible circuit for FPGA programming and debugging

Expansion Header

Two 40-pin headers (GPIOs) provide 68 3.3V I/O pins

Two 5V power pins, two 3.3V power pins and four ground pins

One 6-pin header provides four 3.3V digital I/O pins one 3.3V power pin and one ground pin,

compatible with Digilent Pmod™ connector.

General User Interface Peripherals

o 2 Yellow LEDs

o 2 Push-buttons

o 2 7-Sement LED Displays

Clock System

o On-board 50MHz clock oscillator

USB to UART Interface

o CH340G based USB-UART converter for interfacing to a PC, including TxD and RxD LEDs

Power Supply

o Any of the two USB Type mini-AB ports (5V) (one for the Programmer, and one for the

USB-Serial Interface)

o Two DC 5V pins of the GPIO headers (5V)

1.2. About the kit The kit comes with the following contents:

MAX-10 Development Board

USB Cable

User Manual

2. Max-10 Development Board Architecture

2.1. Layout and Components The picture of the MAX-10 Development Board is shown below in figure 1 and 2 marking the various

components on-board.

Figure 1. The Max_10_Dev Board Top Side

Figure 2. The Max_10_Dev Board bottom side

2.2. Block Diagram of the Max_10_Dev Board The figure 3 below shows the block diagram. The board comes with basic user I/O, like push button switches,

LEDs and 7-segment displays, a lot of general purpose I/O pins, a USB to serial interface and a built-in

programmer.

7-Segment Display (2)

Push Button Switches (2)

(J4) USB Mini-AB for USB to UART

(J2) USB Mini-AB for FPGA Programming

40-pin GPIO Header

40-pin GPIO

Header

Altera Max 10 FPGA

PMOD Connector

User LEDs

FPGA Programming Microcontroller

USB to UART (CH340G)

Figure 3. Block Diagram of the MAX_10_Dev Board

3. Using the Max_10_Dev Board

3.1. Powering the Max_10_Dev Board The board is preloaded with a configuration bit stream. This allows to quickly see if the board is working

properly. On powering up the LEDs and the 7-segment displays start flashing. The board can be powered up

by the following two options.

1. Connect either of the USB Mini-AB ports of the board (J2 or J4) to a USB host using the USB Mini-B

cable provided with the board.

2. Alternatively the board can be powered up by supplying 5V to the two DC +5V pins of the GPIO

headers.

3.2. Configuring the Max 10 FPGA The Max-10 Development board contains a Max 10 FPGA which can be programmed by using the on-board

JTAG circuitry. This allows the users to configure the FPGA with a specific design using the Quartus II software.

The board supports two types of configuration methods.

1. JTAG configuration: Configuration using the Joint Test Action Group (JTAG) port. (Volatile

Configuration)

JTAG configuration scheme allows you to directly configure the device core through JTAG pins - TDI, TDO,

TMS, and TCK pins. The Quartus II software automatically generates “.sof” files that are used for JTAG

configuration with a download cable in the Quartus II software program. In this method the programmed

design will remain functional on the FPGA as long as the board is powered on, or until the FPGA is

reprogrammed. The configuration information will be lost when the power is turned off.

2. Internal configuration: Configuration using internal flash. (Non-Volatile Configuration)

Before internal configuration, you need to program the configuration data into the on-chip configuration

flash memory (CFM) which provides a non-volatile storage for the bit stream. The information is retained

within CFM even if the board is turned off. When the board is powered on, the configuration data in the

CFM is automatically loaded into the MAX 10 FPGA.

40 Pin GPIO Header

40 Pin GPIO Header

7-Segment Display (2)

User

LEDs (2)

USB - Serial

Push Buttons (2)

USB - Programmer

Power Supply

5V to 3.3V

X68

X14

50MHz

Clock

X2

3.2.1. Configure the FPGA in JTAG mode To download a bit stream file using JTAG configuration into the Max 10 FPGA, perform the following steps:

1. Connect a USB Mini-B cable between a host computer running Quartus and the Max 10 board.

2. The FPGA can now be programmed through the Quartus II Programmer by selecting a configuration

bit stream file with the .sof filename extension.

3.2.2. Configure the FPGA using Internal Configuration 1. The configuration data to be written to CFM will be part of the programmer object file (.pof). This

configuration data is automatically loaded from the CFM into the MAX 10 devices when the board is

powered up.

2. Please refer to Appendix: Programming the Configuration Flash Memory (CFM) for the basic

programming instructions on the configuration flash memory (CFM).

3.3. Clock Circuitry The Max_10_Dev board includes a 50 MHz crystal oscillator. The oscillator is connected directly to a dedicated

clock input pin of the Max 10 FPGA. The 50 MHz clock input can be used as a source clock to drive the phase

lock loop (PLL) circuits inside the FPGA. The clock pin assignment is shown in the table 9 below.

Table 1. Pin Assignments for Clock input

Signal Name FPGA Pin No. Description I/O Standard

CLOCK_50 PIN_28 50 MHz Clock Input 3.3V

3.4. User Interface

3.4.1. Pushbuttons The Max 10 board contains two pushbuttons shown in figure 4. The two outputs called SW0, and SW1 are

connected directly to the Max 10 FPGA. Each pushbutton provides a high logic level when it is not pressed,

and provides a low logic level when pressed. Since the pushbuttons are not de-bounced, appropriate logic may

have to be built in the FPGA. Table 2 gives the pin assignment for the pushbuttons switches.

Figure 4. Connections between the push-buttons and Max 10 FPGA

Table 2. Pin Assignments for Pushbuttons


SW[0] PIN_70 Pushbutton[0] 3.3V

SW[1] PIN_74 Pushbutton[1] 3.3V

SW0

SW1

VCC3.3

70

74

3.4.2. LEDs There are 2 yellow user-controllable LEDs on the Max_10_Dev board. The two LEDs, which are shown in figure

5, allow users to display status and debugging information. Each LED is driven directly by a pin on the Max 10

FPGA; driving its associated pin to a high logic level turns the LED on, and driving the pin low turns it off. Table

2 gives the pin assignment for the LEDs

Figure 5. Connections between the push-LEDs and Max 10 FPGA

Table 3. Pin Assignments for LEDs


LED[0] PIN_54 LED Yellow[0] 3.3V

LED[1] PIN_55 LED Yellow[1] 3.3V

3.4.3. 7-Segment LED Displays The Max_10_Dev board has two common anode 7-segment displays. The segments can be turned on or off by

applying a low logic level or high logic level from the FPGA, respectively. Each segment in a display is indexed

from 0 to 6 and DP (decimal point), with corresponding positions given in figure 6. The decimal points have

not been connected to the FPGA. Table 3 shows the pin assignments of FPGA to the 7-segment displays.

Figure 6. Connections between the 7-segment display HEX0 and the MAX 10 FPGA

Table 4. Pin Assignments for 7-Segment LED Display HEX0


HEX0[0] PIN_92 Segment A 3.3V

HEX0[1] PIN_90 Segment B 3.3V

HEX0[2] PIN_88 Segment C 3.3V

HEX0[3] PIN_86 Segment D 3.3V

HEX0[4] PIN_87 Segment E 3.3V

HEX0[5] PIN_91 Segment F 3.3V

HEX0[6] PIN_89 Segment G 3.3V

54

55

A

B

C

D

E

F

G

DP

HEX0[5]

HEX0[0]

HEX0[1]

HEX0[2]

HEX0[3]

HEX0[4]

HEX0[6]

Table 5. Pin Assignments for 7-Segment LED Display HEX1


HEX1[0] PIN_101 Segment A 3.3V

HEX1[1] PIN_99 Segment B 3.3V

HEX1[2] PIN_97 Segment C 3.3V

HEX1[3] PIN_94 Segment D 3.3V

HEX1[4] PIN_95 Segment E 3.3V

HEX1[5] PIN_100 Segment F 3.3V

HEX1[6] PIN_98 Segment G 3.3V

3.5. Expansion Headers The Max_10_Dev board provides two 40 pin expansion headers. Each header connects directly to 34 pins of

the Max 10 FPGA and also provides DC +5V, DC +3.3V and two GND pins. Figure 7 shows pin-out of the GPIO

headers. Tables 5 and 6 give the pin assignments for the headers GPIO_0 and GPIO_1 respectively.

Figure 7. Pin Arrangement of the GPIO expansion headers

Table 6. Pin Assignments for GPIO_0


GPIO_0_00 PIN_19 GPIO signal connection 3.3V




































GPIO_1



































3.6. Pmod Connector The Max_10_Dev board provides one 6-pin Digilent Pmod™ compatible connector, which is used to connect

low frequency, low I/O pin count peripheral modules. The connector connects to 4 pins of the Max 10 FPGA

and also provides DC +3.3V and GND pins. Figure 8 shows pin-out of the Pmod connector. Table 7 gives the

pin assignment for the Pmod connector.

Figure 8. Pin Arrangement of the PmodTM Connector



PMOD_IO[0] PIN_85 PMOD In/Out 3.3V




3.7. USB to UART Interface The board uses a USB based UART bridge chip (CH340G) to bridge communication to a host for general

software debug for NIOS soft processor and non-NIOS systems. This chip uses TXD and RXD for transmission

and reception of data. A mini B plug receptacle (PCB reference J4) is used to minimize board space. The related

I/O utilization is implemented in Bank 2.

Table 9. Pin Assignments for USB to UART Interface


FPGA_TX PIN_26 Transmit asynchronous data output 3.3V

FPGA_RX PIN_27 Receive asynchronous data input 3.3V

MAX 10 Development Board - TIFR

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