Lecture 6 Logic Simulation - Iran University of Science...

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 6 1

Lecture 6Logic Simulation

Lecture 6Logic Simulation

What is simulation? Design verification Circuit modeling True-value simulation algorithms

Compiled-code simulation Event-driven simulation

Summary


Simulation DefinedSimulation Defined Definition: Simulation refers to modeling of a

design, its function and performance. A software simulator is a computer program;

an emulator is a hardware simulator. Simulation is used for design verification:

Validate assumptions Verify logic Verify performance (timing)

Types of simulation: Logic or switch level Timing Circuit Fault


Simulation for VerificationSimulation for Verification

True-valuesimulation

Specification

Design(netlist)

Input stimuliComputedresponses

Responseanalysis

Synthesis

Designchanges

A 32-bit ripple-carry adderA 32-bit ripple-carry adder


11

00

00

00 0000

111

1

1

Design verification Vectors for 4-bit adder circuit (functional correctness)Design verification Vectors for 4-bit

adder circuit (functional correctness)


Delay Test for longest path : C0 C4 , vector 2,6(3,7) C4: 0 1


5.2:Simulation forTest Evaluation

Determines the Fault CoverageProduce a set of test vector

Test evaluation for single stuck at fault Four-bit adder

Test evaluation for single stuck at fault Four-bit adder


Reverse-Order simulationReverse-Order simulation


Reverse-Order simulation cannot be used for sequential Circuits

101010101100110011011001100010101010


5.3: Modeling Circuits for Simulation

5.3: Modeling Circuits for Simulation

Modules, blocks or components described by Input/output (I/O) function Delays associated with I/O signals Examples: binary adder, Boolean gates, FET,

resistors and capacitors Interconnects represent

ideal signal carriers, or ideal electrical conductors

Netlist: a format (or language) that describes a design as an interconnection of modules. Netlist may use hierarchy. ( HDL (Verilog ), VHDL)


Modeling Levels and Type of simulaton

Modeling Levels and Type of simulaton

Circuitdescription

Programminglanguage-like HDL

Connectivity ofBoolean gates,flip-flops andtransistors

Transistor sizeand connectivity,node capacitances

Transistor technologydata, connectivity,node capacitances

Tech. Data, active/passive componentconnectivity

Signalvalues

0, 1

0, 1, Xand Z

0, 1and X

Analogvoltage

Analogvoltage,current

Timing

Clockboundary

Zero-delayunit-delay,multiple-delay

Zero-delay

Fine-graintiming

Continuoustime

Modelinglevel

Function,behavior, RTL

Logic

Switch

Timing

Circuit

Application

Architecturaland functionalverification

Logicverificationand test

Logicverification

Timingverification

Digital timingand analogcircuitverification


Example: A Full-AdderExample: A Full-AdderHA; inputs: a, b;outputs: c, f;AND: A1, (a, b), (c);AND: A2, (d, e), (f);OR: O1, (a, b), (d);NOT: N1, (c), (e);

a

b

c

d e

f HA

FA;inputs: A, B, C;outputs: Carry, Sum;HA: HA1, (A, B), (D, E);HA: HA2, (E, C), (F, Sum);OR: O2, (D, F), (Carry);

HA1HA2

AB C

D E F

Sum

Carry

A2O1

N1

O2


Ca

Logic Model of MOS CircuitLogic Model of MOS Circuit

Cc Cb

VDD

a

b c

pMOS FETs

nMOS FETs

Ca , Cb and Cc are parasitic capacitances

DcDa c

a

b

Da and Db are interconnect or propagation delays

Dc is inertial delayof gate

Db


Options for Inertial Delay(simulation of a NAND gate)

Options for Inertial Delay(simulation of a NAND gate)

b

a

c (CMOS)

Time units0 5

c (zero delay)

c (unit delay)

c (multiple delay)

c (minmax delay)

Inpu

tsLo

gic

sim

ulat

ion

min =2, max =5

rise=5, fall=3

Transient region

Unknown (X)

X


Signal StatesSignal States Two-states (0, 1) can be used for purely

combinational logic with zero-delay. Three-states (0, 1, X) are essential for

timing hazards and for sequential logic initialization.

Four-states (0, 1, X, Z) are essential for MOS devices. See example below.

Analog signals are used for exact timing of digital logic and for analog circuits.

00

Z(hold previous value)

٤Week Fault-Tolerant System Design ١٦

Level of SimulationLevel of Simulation Register-level , for systems modeled entirely

in RTL or as an interconnection of components modeled in RTL

Functional-level, for systems modeled as an interconnection of primitive functional blocks

Gate-level simulation;

Transistor-level (we consider logic level and not circuit-level analog simulation)

Mixed-level simulation


True-Value Simulation Algorithms

True-Value Simulation Algorithms

Compiled-code simulation Applicable to zero-delay combinational logic Also used for cycle-accurate synchronous sequential

circuits for logic verification Efficient for highly active circuits, but inefficient for

low-activity circuits High-level (e.g., C language) models can be used

Event-driven simulation Only gates or modules with input events are

evaluated (event means a signal change) Delays can be accurately simulated for timing

verification Efficient for low-activity circuits Can be extended for fault simulation


Compiled-Code AlgorithmCompiled-Code Algorithm

Step 1: Levelize combinational logic and encode in a compilable programming language

Step 2: Initialize internal state variables (flip-flops)

Step 3: For each input vectorSet primary input variablesRepeat (until steady-state or max. iterations) Execute compiled code

Report or save computed variables

٤Week Fault-Tolerant System Design ١٩

Compiled Simulation

Delay can be modeled by

Explicitly adding them to

Software model

٤Week Fault-Tolerant System Design ٢٠

Example: A Full-AdderExample: A Full-AdderHA; inputs: a, b;outputs: c, f;AND: A1, (a, b), (c);OR: O1, (a, b), (d);NOT: N1, (c), (e); AND: A2, (d, e), (f);

a

b

c

d e

f

FA;inputs: A, B, C;outputs: Carry, Sum;HA: HA1, (A, B), (D, E);HA: HA2, (E, C), (F, Sum);OR: O2, (D, F), (Carry);

HA1HA2

AB C

D E F

Sum

Carry

A1

O1A2

N1

o2

٤Week Fault-Tolerant System Design ٢١

Asynchronous circuit simulation with compiled-code mode

٤Week Fault-Tolerant System Design ٢٢

0 0 011

1 0

Correct model for compiled simulati

Shows that a compiled simulator cannot deal with

Races and hazards

٤Week Fault-Tolerant System Design ٢٣

Main flow of event-driven simulation


Event-Driven Algorithm(Example)

Event-Driven Algorithm(Example)

2

2

4

2

a =1

b =1

c =1 0

d = 0

e =1

f =0

g =1

Time, t0 4 8

g

t = 0

1

2

3

4

5

6

7

8

Scheduledevents

c = 0

d = 1, e = 0

g = 0

f = 1

g = 1

Activitylist

d, e

f, g

g

Tim

e st

ack


Time Wheel (Circular Stack)Time Wheel (Circular Stack)

t=01

2

3

4

56

7

maxCurrenttimepointer Event link-list


Efficiency of Event-driven Simulator

Efficiency of Event-driven Simulator

Simulates events (value changes) only Speed up over compiled-code can be ten

times or more; in large logic circuits about 0.1 to 10% gates become active for an input change

Large logicblock without

activity

Steady 0

0 to 1 event

Steady 0(no event)

٤WeekFault-Tolerant System Design٢٧

Delay ModelsDelay Models Delay modeling

is a key element controlling the trade-off between the accuracy and the complexity of the simulation algorithm.

Delay Modeling for gates:

٤Week Fault-Tolerant System Design ٢٨

٤Week Fault-Tolerant System Design ٢٩

d

dfd

r

Transition-independent delay

model

dI=4

dI=2d

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Output Inertial Delay

٤Week Fault-Tolerant System Design ٣١

Delay Modeling for Functional element

Delay Modeling for Functional element

٤Week Fault-Tolerant System Design ٣٢

Wire delays Modeled by delay element


SummarySummary Logic or true-value simulators are essential

tools for design verification. Verification vectors and expected responses

are generated (often manually) from specifications.

A logic simulator can be implemented using either compiled-code or event-driven method.

Per vector complexity of a logic simulator is approximately linear in circuit size.

Modeling level determines the evaluation procedures used in the simulator.

Lecture 6 Logic Simulation - Iran University of Science...

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