Lecture 12 –Building Blocks (Adders)een.iust.ac.ir/profs/Abrishamifar/Digital Integrated Circuit...

Adib AbrishamifarEE Department

IUST

Lecture 12 – Building Blocks (Adders)

Digital Integrated Circuit Design

CPA

CSA

P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11

CSA CSA CSA

CSACSA

CSACSA

CSA

CSA

IUST: Digital IC Design LECTURE 12 : Building BlocksLECTURE 12 : Building Blocks Adib Abrishamifar 20082/87

Contents

} Outline} Adders

} Half Adder} Full Adder

• Ripple-Carry Adder (Parallel Adder)– Calculation of Circuit Delays

• Carry-Bypass Adder (Carry-Skip Adder)– Manchester Carry Chain (MCC)

• Carry Select Adder– Linear– Square Root

• Conditional Carry Adder• Carry Save Adder• Wallace Tree• Look-Ahead Adder

} Adder Delays - Comparison} Example} Summary


Outline

} Types of logic circuit} Combinational } Sequential

} Design methods} Gate level design

• Example: Full adder} Block level design

• Example: Parallel adder, ALU

} Propagation Delay


Outline

} Building Blocks for Digital Architectures} Arithmetic unit

• Bit-sliced datapath (Adders, Multipliers, Shifters, Comparators, etc.)

} Memory• RAM, ROM, Buffers, Shift registers

} Control• Finite state machine (PLA, random logic)• Counters

} Interconnect• Switches• Arbiters• Bus


Contents

} Outline} Adders








HalfAdder

X

Y

S

C

(X + Y)

X Y C S0 0 0 00 1 0 11 0 0 11 1 1 0

} Half Adder (Gate-level Design)

} C = XY} S = X'Y + XY' = X⊕Y

Adders


Adders

} Half Adder (Gate-level Design)


1 1 1 carry0 0 1 1 X

+ 0 1 1 1 Y1 0 1 0 S

FullAdder

XYZ

S

C

(X + Y + Z)

Adders

} Half Adder } To add two binary numbers, we need to add 3 bits

(including the carry)

} Need Full Adder (so called as it can be made from two half-adders)


Contents

} Outline} Adders








X Y Z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

0

1

00 01 11 10XYZ

111

1

C

0

1

00 01 11 10XYZ

11

11

S

Adders

} Full Adder (Gate-level Design)

} C = XY + XZ + YZ} S = X'Y'Z + X'YZ'+XY'Z'+XYZ


Adders

} Full Adder } Alternative formula using algebraic manipulation

• C = XY + XZ + YZ• = XY + (X + Y)Z• = XY + ((X ⊕ Y) + XY)Z• = XY + (X ⊕ Y)Z + XYZ• = XY + (X ⊕ Y)Z

• S = X'Y'Z + X'YZ' + XY'Z' + XYZ• = X'(Y'Z + YZ') + X(Y'Z' + YZ)• = X'(Y ⊕ Z) + X(Y ⊕ Z)'• = X ⊕ (Y ⊕ Z) or (X ⊕ Y) ⊕ Z


Adders

} Full Adder C = XY + (X⊕Y)ZS = (X⊕Y)⊕Z


Adders

H.A. H.A.

OR

X

Y

Z

S

C

C

C

S SF

CF

H.A. H.A.

ORgate

Y

Z

S

C

C

C

S SF

F

} Full Adder made from two Half-Adders (+ OR gate)


} FA Gate Level (XOR FA, 16 Transistors)

Cout

S

CinA

B

Adders


} CPL FA (20 + 8 transistors)

Adders


Signal set-up Carry generation Sum generation

Adders

} Delay Balanced FA (Identical Delays for Carry and Sum, 20 +2 transistors)


} N-bit adder called CPA (Carry Propagate Adder)} Each sum bit depends on all previous carries} How do we compute all these carries quickly?

11111 1111 +0000 0000

A4...1

carries

B4...1

S4...1

CinCout

00000 1111 +0000 1111

CinCout

Adders


Contents

} Outline} Adders








4-bitParallel Adder

C4 C0

X1 X0 Y3 Y2

S3 S2 S1 S0

Y1 Y0X3 X2

Adders

} Ripple-Carry Adder (Parallel Adder)} Consider a circuit to add two 4-bit numbers together and

a carry-in, to produce a 5-bit result


Adders

} Ripple-Carry Adder (Parallel Adder)} Simplest design: cascade full adders

• Critical path goes from Cin to Cout

• Design full adder to have fast carry delay• Addition formulae for each pair of bits (with carry in), has

the same function as a full adder

• Ci+1 = Xi Yi + (Xi ⊕ Yi ) Ci

• Si = Xi ⊕ Yi ⊕ Ci


C0

Y0 X0

S0

FA

C1

C4

Y1 X1

S1

FA

C2

Y2 X2

S2

FA

C3

Y3 X3

S3

FA

OutputInput

Adders

} Ripple-Carry Adder (Parallel Adder)} Cascading 4 full adders via their carries


Adders

} Ripple-Carry Adder (Parallel Adder)} Note that carry propagated by cascading the carry from

one full adder to the next

} Called Parallel Adder because inputs are presented simultaneously (in parallel)

Full Adder

B A CIN

COUT SUM

Full Adder

B A CIN

COUT SUM

Full Adder

B A CIN

COUT SUM

B1 A1 B0 A0 B2 A2

CIN = 0

Q1 Q0 Q2


Adders

} Ripple-Carry Adder (Parallel Adder)} Output Inverting (Carry-Sum)

Full Adder

B A CIN

COUT SUM

Full Adder

B A CIN

COUT SUM

Full Adder

B A CIN

COUT SUM

B1 A1 B0 A0B2 A2

CIN = 0

S1 S0S2

COUT


Adders

} Ripple-Carry Revisited} Gi:0 = Gi + Pi . Gi-1:0

S1

B1A1

P1G1

G0:0

S2

B2

P2G2

G1:0

A2

S3

B3A3

P3G3

G2:0

S4

B4

P4G4

G3:0

A4 Cin

G0 P0

C0C1C2C3

Cout

C4


Adders

} How To Subtract ?} Suppose added input to the adder that gave the one’s

complement of B} What happens if set C0 to 1 in the parallel adder?} Sum = A + B + 1} Then if select inverted B', Sum is A + B' + 1 = A + (B' + 1)

= A + (-B) = A - B} Therefore can do subtract with the parallel adder if we

add inverters and set C0 to 1


Adders

} Subtraction


} Add / Sub Circuits Comparison} Both the addition and subtraction circuits are based around

the parallel adder

} For addition:• A and B are inputted directly to the adder• CIN = 0

} For subtraction:• A is inputted directly• All the bits of B are complemented• CIN = 1

Adders


Adders

} An Adder / Subtraction Circuit


Adders

} Ripple-Carry Adder (Parallel Adder)} Advantage:

• Simple logic, so small (low cost)} Disadvantage:

• Slow (O(N) for N bits) and lots of glitching (so lots of energy consumption)

• Propagation delay of ripple-carry parallel adders is proportional to the number of bits it handles

• Maximum Delay: ((n-1)×2+3)t (it is shown in near future!)


Contents

} Outline} Adders








Adders

} Calculation of Circuit Delays} As a simple example, consider the full adder circuit

where all inputs are available at time 0. (Assume each gate has delay t)


Adders

} Calculation of Circuit Delays} More complex example: 4-bits parallel adder


FullAdder

Xi

Yi

Ci

Si

Ci+1

00mt

Adders

} Calculation of Circuit Delays} Analyze the delay for the repeated block} where Xi, Yi are stable at 0t, while Ci is assumed to be

stable at mt


Adders

} Calculation of Circuit Delays

t

00

mt

max(0,0) + t = tmax(t,mt) + t

max(t,mt) + t

max(t,mt) + 2t

iC i+1C

iSiXiY


Adders

} Calculation of Circuit Delays} When i = 1, m = 0: S1 = 2t and C2 = 3t } When i = 2, m = 3: S2 = 4t and C3 = 5t} When i = 3, m = 5: S3 = 6t and C4 = 7t} When i = 4, m = 7: S4 = 8t and C5 = 9t

} In general for an n-bit ripple-carry parallel adder } Sn = ((n-1)×2+2)t} Cn+1 = ((n-1)×2+3)t


Adders

} Ways of improving the speed} Use better technology (e.g. ECL faster than TTL gates)

• Faster technology is more expensive, needs more power, lower-level of integrations

• Physical limits (e.g. speed of light, size of atom)} Use gate-level designs to two-level circuits! (use sum-of-

products/product-of-sums)• Complicated designs for large circuits• Product/sum terms need MANY inputs!

} Use clever (other) techniques


Contents

} Outline} Adders








} Carry-Bypass Adder (Carry-Skip Adder)} Carry-ripple is slow through all N stages} Carry-Bypass Adder allows carry to skip over groups of

n bits• Decision based on n-bit propagate signal

Cin+

S4:1

P4:1

A4:1 B4:1

+

S8:5

P8:5

A8:5 B8:5

+

S12:9

P12:9

A12:9 B12:9

+

S16:13

P16:13

A16:13 B16:13

CoutC4

1

0

C81

0

C121

0

1

0

Adders


Carrypropagation

SetupBit 0–3

Sum

M bits

tsetup

tsum

Carrypropagation

SetupBit 4–7

Sum

tbypass

Carrypropagation

SetupBit 8–11

Sum

Carrypropagation

SetupBit 12–15

Sum

Adders

} Carry-Bypass Adder (Carry-Skip Adder)} Carry-skip allows carry to skip over groups of m bits


FA

iSiP

ia ib

FAS

P

FAS

P

nC

jC

Carry Skip Circuit

FAS

P

FAS

P

FAS

P

1nC +

1+jC

Carry Skip Circuit2nC +

Adders

} Carry-Bypass Adder (Carry-Skip Adder)

} Pi = XOR (ai , bi)


Adders

} Carry-Bypass Adder (Carry-Skip Adder)} Carry Skip Circuit} This Circuit calculate the carry for the next stage rapidly

1P2P

iP

nC

jC

1nC +


Ci,0

Sum

CarryPropagation

Setup

Sum

CarryPropagation

Setup

Sum

CarryPropagation

Setup

Sum

CarryPropagation

Setup

bits 0 to 3bits 4 to 7bits 8 to 11bits 12 to 15

Adders

} Carry-Bypass Adder (Carry-Skip Adder)} 4 (B)-bit Block} Worst-case delay → carry from bit 0 to bit 15 = carry generated in bit 0,

ripples through bits 1, 2, and 3, skips the middle two groups (B is the group size in bits), ripples in the last group from bit 12 to bit 15

} Tadd = tsetup + B tcarry + ((N/B) -1) tskip +B tcarry + tsum


Adders

} Carry-Bypass Adder (Carry-Skip Adder)} Variable block sizes

• A carry that is generated in, or absorbed by, one of the inner blocks travels a shorter distance through the skip blocks, so can have bigger blocks for the inner carries without increasing the overall delay


≡

Adders

} Inversion Property} Inverting all inputs to a FA results in inverted values for

all outputs

inin

out inin out

S(A,B,C )=S(A,B,C )

C (A,B,C )=C (A,B,C )


Adders

} Exploiting the Inversion Property} Minimizes the critical path (the carry chain) by

eliminating inverters between the FAs


Adders

} Fast Carry Chain Design} The key to fast addition is a low latency carry network} What matters is whether in a given position a carry is} generated Gi = Ai & Bi = AiBi

} propagated Pi = Ai ⊕ Bi (sometimes Ai | Bi)} annihilated (killed) Ki = Ai & Bi

} Giving a carry recurrence of Ci+1 = Gi | PiCi

C1 = G0 | P0C0

C2 = G1 | P1G0 | P1P0 C0

C3 = G2 | P2G1 | P2P1G0 | P2P1P0 C0

C4 = G3 | P3G2 | P3P2G1 | P3P2P1G0 | P3P2P1P0 C0


Contents

} Outline} Adders








Adders

} Manchester Carry Chain (MCC)} Switches controlled by Gi and Pi

} Total delay of• time to form the switch control signals Gi and Pi

• setup time for the switches• signal propagation delay through N switches in the worst

case


G P

C0

clk

G PG PG P&&&&

A0 B0A1 B1A2 B2A3 B3

S0S1S2S3

C1C2C3

C4

Adders

} Manchester Carry Chain (MCC)} 4-bit Sliced MCC Adder


G2

φ

C3

G3Ci,0

P0

G1

VDD

φ

G0

P1 P2 P3

C3C2C1C0

Adders

} Manchester Carry Chain (MCC)


Pi + 1 Gi + 1 φ

Ci

Inverter/Sum Row

Propagate/Generate Row

Pi Gi φ

Ci - 1Ci + 1

VDD

GND

Adders

} Manchester Carry Chain (MCC)} Stick Diagram


Contents

} Outline} Adders








4- b Setup

“0”

“1” 1

0

CinCout

P’s G’s

C’s

4- b Setup

“ carry propagation

“1” carry propagation 1

0

multiplexer Cin

Sum generation

P’s G’s

C’s

A’s B’s

S’s

Adders

} Carry Select Adder} Trick for critical paths

dependent on late input X

} Precompute the carry out of each block for both carry_in = 0 and carry_in = 1 (can be done for all blocks in parallel) and then select the correct one by Mux


Adders

} Carry Select Adder

Cin+

A4:1 B4:1

S4:1

C4

+

+

01A8:5 B8:5

S8:5

C8

+

+

01

A12:9 B12:9

S12:9

C12

+

+

01

A16:13 B16:13

S16:13

Cout

0

1

0

1

0

1


Contents

} Outline} Adders








Adders

} Carry Select Adder (Linear)

Setup

0 carry

1 carry 1

0

muxC in

Sum gen

P’s G’s

C’s

S’s

A’s B’s

“0” carry

“1” carry

mux

P’s G’s

C’s

S’s

A’s B’s

Setup

0 carry

1 carry

mux

Sum gen

P’s G’s

C’s

S’s

B’s

“0” carry

“1” carry

mux

P’s G’s

C’s

S’s

A’s B’s

Setup

0 carry

1 carry

mux

Sum gen

P’s G’s

C’s

S’s

B’s

Setup

0 carry

1 carry

muxCout

Sum gen

P’s G’s

C’s

S’s

A’s B’sbits 0 to 3bits 4 to 7bits 8 to 11bits 12 to 15


11

+4+4

+1+1+1+1+1+1+1+1+1+1

Adders

} Carry Select Adder (Linear): Critical Path

add setup carry mux sumT =t +Bt +N/Bt +t


Contents

} Outline} Adders








Adders

} Carry Select Adder (Square Root)} This idea can be carried on in a logarithmic tree

fashion to obtain the addition in log2(N) time


11

+2+2

+1+1+1+1+1+1+1+1+1+1

+1+1

+3+3+4+4+5+5+6+6

Adders

} Carry Select Adder (Square Root)

add setup carry mux sumT =t +2t + Nt +t


Contents

} Outline} Adders








Adders

} Conditional Carry Adder} Increase speed twice!

AdderS C

0

HA

HB

Adder

S C

1

HA

HB

Mux

outCHS

Adder

LS

inC

LA

LB


Contents

} Outline} Adders








FA a b

co ci s

FA FA FA FA

FA FA FA FA

FA FA FA FA FA FA

FA FA

FA FA

FA

FA

FA

P0,0 P1,0 P0,1 P1,1 P0,2 P1,2 P0,3 P1,3 P0,4 P1,4 P1,5

P2,0 P2,1 P2,2 P2,3 P2,4 P2,5 P2,6

P3,0 P3,1 P3,2 P3,3 P3,4 P3,5 P3,6 P3,7

S0 S1 S2 S3 S4 S5 S6 S7

Adders

} Carry Save Adder} When adding k n-bit numbers

• Linear Array (or Tree) Summation


CPA CPA CPA CPA CPA CPA

CPA

CPA

CPA

CPA

CPA

P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11

Adders

CPA

(Carry Propagate Adder)


• Tree Summation


Adders


FAa b

cicos

a0 b0

x0

FAa b

cicos

a1 b1

x1

FAa b

cicos

a2 b2

x2

FAa b

cicos

a3 b3

x3

CSA:A + B + C = X + Y

c3

y4

c2

y3

c1

y2

c0

y1

CPA:A + B = S FA

a bcoci

s

a0 b0

s0

FAa b

cocis

a1 b1

s1

FAa b

cocis

a2 b2

s2

FAa b

cocis

a3 b3

s3

ci,0 co,3


FA FA FA FA FA FA

P0,0 P1,0 P0,1 P1,1 P0,2 P1,2 P0,3 P1,3 P0,4 P1,4 P1,5P2,0 P2,1 P2,2 P2,3 P2,4 P2,5 P2,6

P3,0 P3,1 P3,2 P3,3 P3,4 P3,5 P3,6 P3,7

FA

FA FA FA FA FA FA FA FA


S0 S1 S2 S3 S4 S5 S6 S7

Adders

} Carry-Save Adder


Adders

} Carry Save Adder} Intermediate FA Cells

• Better to have the same sum and carry delays(both contribute to critical path)


Adders

} Speed up summation with faster adders (Logarithmic)} Linear (Tree) array has several equal-length critical

paths⇒ All adders need to be replaced

} The carry-save array has only ONE critical path⇒ Replace only the final CPA (see next slide)


Adders

} Speed up summation with faster adders} Replace only the final CPA

FA FA FA FA FA FA

P0,0 P1,0 P0,1 P1,1 P0,2 P1,2 P0,3 P1,3 P0,4 P1,4 P1,5P2,0 P2,1 P2,2 P2,3 P2,4 P2,5 P2,6

P3,0 P3,1 P3,2 P3,3 P3,4 P3,5 P3,6 P3,7

FA



S0 S1 S2 S3 S4 S5 S6 S7

CPA


Contents

} Outline} Adders








CPA

CSA

P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11

CSA CSA CSA

CSA CSA

CSA CSA

CSA

CSA

Adders

} Wallace Tree} Sums in O(log m) steps


Contents

} Outline} Adders








} LookAhead - Basic Idea} Carry-lookahead adder computes Gi:0 for many bits in

parallel} Uses higher-valency cells with more than two inputs

Cin+

S4:1

G4:1P4:1

A4:1 B4:1

+

S8:5

G8:5P8:5

A8:5 B8:5

+

S12:9

G12:9P12:9

A12:9 B12:9

+

S16:13

G16:13P16:13

A16:13 B16:13

C4C8C12Cout

Adders


AN-1, BN-1A1, B1

P1

S1

• • •

• • • SN-1

PN-1Ci, N-1

S0

P0Ci,0 Ci,1

A0, B0

Co k, f A k Bk Co k, 1–, ,( ) Gk P kCo k 1–,+= =

Adders

} LookAhead - Basic Idea} C1 = G0 + P0C0

} C2 = G1 +P1G0 + P1P0 C0

} C3 = G2 + P2G1 + P2P1G0 + P2P1P0 C0

} C4 = G3 +P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0 C0


Co,3

Ci,0

VDD

P0

P1

P2

P3

G0

G1

G2

G3

Adders

} Look-Ahead: Topology


Adders

} Look-Ahead} Expanding Lookahead equations

• Co,k = Gk + Pk(Gk-1 + Pk-1Co,k-2)

} All the way• Co,k = Gk + Pk(Gk-1 + Pk-1(… + P1(Go + PoCi,o)))


A7

F

A6A5A4A3A2A1

A0

A0A1

A2A3

A4A5

A6

A7

F

tp∼ log2(N)

tp∼ N

Adders

} Logarithmic Look-Ahead Adder


Co 0, G0 P0Ci 0,+=

Co 1, G1 P1 G0 P1P0 Ci 0,+ +=

Co 2, G2 P2G1 P2 P1G0 P+ 2 P1P0C i 0,+ +=

G2 P2G1+( )= P2P1( ) G0 P0Ci 0,+( )+ G 2:1 P2:1Co 0,+=

Adders

} Carry Lookahead Trees

} Can continue building the tree hierarchically


Contents

} Outline} Adders








Square root select

Linear select

Ripple adder

20 40N

t p(in

uni

t del

ays)

600

10

0

20

30

40

50

Adders

} Adder Delays - Comparison


Contents

} Outline} Adders








VDD

Clk Pi= ai + bi

Clk

ai bi

VDD

Clk Gi = aibi

Clk

ai

bi

Generate (G) = ABPropagate (P) = A ⊕ B

Adders

} Example: Domino Adder


VDD

Clkk

Pi:i-k+1

Pi-k:i-2k+1

Pi:i-2k+1

VDD

Clkk

Gi:i-k+1

Pi:i-k+1

Gi-k:i-2k+1

Gi:i-2k+1

Propagate Generate

Adders

} Example: Domino Adder


VDD

Clk

Gi:0

Clk

Sum

VDD

Clkd

Clk

Gi:0

Clk

Si1

Clkd

Si0

Keeper

Adders

} Example: Domino Sum


Contents

} Outline} Adders








Summary

} This lecture describes one of the basic building blocks (Adders) and also implementation of them in transistor level

} Also noted how to choose an adder and designing fast ones

Lecture 12 –Building Blocks (Adders)een.iust.ac.ir/profs/Abrishamifar/Digital Integrated Circuit...

Documents

Transcript of Lecture 12 –Building Blocks (Adders)een.iust.ac.ir/profs/Abrishamifar/Digital Integrated Circuit...