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Introduction to

CMOS VLSIDesign

Adders

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AddersSlide 2CMOS VLSI Design

Outline

Single-bit Addition

Carry-Ripple Adder

Carry-Skip Adder

Carry-Lookahead Adder

Carry-Select Adder

Carry-Increment Adder

Tree Adder

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AddersSlide 3CMOS VLSI Design

Single-Bit Addition

Half Adder Full Adder

A B Cout S

!

!

! !

A B C Cout S

!

!

! !

! ! !

! !

! ! !

A B

S

Cout

A B

C

S

Cout

out

S

C

=

= out

S

C

=

=

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AddersSlide 4CMOS VLSI Design

Single-Bit Addition

Half Adder Full Adder

A B Cout S

! !

! !

! ! !

A B C Cout S

! !

! !

! ! !

! !! ! !

! ! !

! ! ! ! !

A B

S

Cout

A B

C

S

Cout

out

S A B

C A B

=

= g out ( , , )

S A B C

C MAJ A B C

=

=

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AddersSlide 5CMOS VLSI Design

PGK

For a full adder" define #hat happen$ to carrie$

% &enerate' Cout( ! independent of C

) & (

% *ropagate' Cout( C) * (

% +ill' Cout( independent of C

) + (

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AddersSlide 6CMOS VLSI Design

PGK

For a full adder" define #hat happen$ to carrie$

% &enerate' Cout( ! independent of C

) & ( A ) B

% *ropagate' Cout( C) * ( A B

% +ill' Cout( independent of C

) + ( ,A ) ,B

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AddersSlide 7CMOS VLSI Design

Full Adder Design I

Brute force implementation from en$

out ( , , )

S A B C

C MAJ A B C

=

=

ABC

S

Cout

.A/

ABC

A

B BB

A

C SC

CC

B BB

A A

A B

C

B

A

CBA A B C

Cout

C

A

A

BB

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AddersSlide 8CMOS VLSI Design

Full Adder Design II

Factor S in term$ of Cout

S ( ABC 0 1A 0 B 0 C21,Cout2

Critical path i$ u$ually C to Coutin ripple adder

SS

Cout

A

B

C

Cout

.I34RIT5

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AddersSlide 9CMOS VLSI Design

Layout

Cle6er layout circum6ent$ u$ual line of diffu$ion

% 7$e #ide tran$i$tor$ on critical path

% 8liminate output in6erter$

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AddersSlide 10CMOS VLSI Design

Full Adder Design III

Complementary *a$$ Tran$i$tor Logic 1C*L2

% Slightly fa$ter" but more area

A

C

S

S

B

B

C

C

C

B

B

Cout

Cout

C

C

C

C

B

B

B

B

B

B

B

B

A

A

A

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AddersSlide 11CMOS VLSI Design

Full Adder Design IV

9ual-rail domino

% :ery fa$t" but large and po#er hungry

% 7$ed in 6ery fa$t multiplier$

Cout;h

A;h B;h

C;h

B;h

A;h

Cout;l

A;l B;l

C;l

B;l

A;l

S;hS;l

A;h

B;h B;hB;l

A;l

C;l

C;h C;h

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AddersSlide 12CMOS VLSI Design

Carry Propagate Adders

3-bit adder called C*A

% 8ach $um bit depend$ on all pre6iou$ carrie$

% Ho# do #e compute all the$e carrie$ uickly===!

carrie$

B>===!S

>===!

Cin

Cout

00000

1111

+0000

1111

Cin

Cout

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AddersSlide 13CMOS VLSI Design

Carry-ipple Adder

Simple$t de$ign' ca$cade full adder$

% Critical path goe$ from Cin to Cout

% 9e$ign full adder to ha6e fa$t carry delay

Cin

Cout

B!

A!

B?

A?

B@

A@

B>

A>

S!

S?

S@

S>

C!C?C@

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AddersSlide 14CMOS VLSI Design

In!ersions

Critical path pa$$e$ through maority gate

% Built from minority 0 in6erter

% 8liminate in6erter and u$e in6erting full adder

Cout

Cin

B!

A!

B?

A?

B@

A@

B>

A>

S!

S?

S@

S>

C!C?C@

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AddersSlide 16CMOS VLSI Design

Generate " Propagate

8uation$ often factored into & and *

&enerate and propagate for group$ $panning i'

Ba$e ca$e

Sum'

: : : 1:

: : 1:

i j i k i k k j

i j i k k j

G G P G

P P P

= +

=

g

g

:

:

i i i i i

i i i i i

G G A B

P P A B

=

=

g

: :: :

0:0 0

0:0 0 0

inG G C

P P

=

=

1:0i i iS P G =

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AddersSlide 17CMOS VLSI Design

PG Logic

S!

B!

A!

*!

&!

&'

S?

B?

*?

&?

&!'

A?

S@

B@

A@

*@

&@

&?'

S>

B>

*>

&>

&@'

A>

Cin

&

*

!' Bit#i$e *& logic

?' &roup *& logic

@' Sum logicC

C

!C

?C

@

Cout

C>

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AddersSlide 18CMOS VLSI Design

Carry-ipple e!isited

:0 1:0

i i i iG G P G = + g

S!

B!A!

*!

&!

&'

S?

B?

*?

&?

&!'

A?

S@

B@A@

*@

&@

&?'

S>

B>

*>

&>

&@'

A> Cin

&

*

C

C!

C?

C@

Cout

C>

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AddersSlide 19CMOS VLSI Design

Carry-ipple PG

Diagra#

9elay

!?@>DEF!!!!?!@!>!

!' !>' ! @' !?' !!' !' F' E' D' ' ' >' @' ?' !' '

Bit *o$ition

ripplet =

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AddersSlide 20CMOS VLSI Design

Carry-ipple PG

Diagra#

9elay

!?@>DEF!!!!?!@!>!

!' !>' ! @' !?' !!' !' F' E' D' ' ' >' @' ?' !' '

Bit *o$ition

ripple xor ( 1)pg AOt t N t t = + +

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AddersSlide 21CMOS VLSI Design

PG Diagra# $otation

i'

i'

i'k k-!'

i'

i'k k-!'

i'

&i'k

*k-!'

&k-!'

&i'

*i'

*i'k

&i'k

&k-!'

&i' &

i'

*i'

&i'

*i'

*i'k

Black cell &ray cell Buffer

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AddersSlide 22CMOS VLSI Design

Carry-S%ip Adder

Carry-ripple i$ $lo# through all 3 $tage$

Carry-$kip allo#$ carry to $kip o6er group$ of n bit$

% 9eci$ion ba$ed on n-bit propagate $ignal

Cin

0

S>'!

*>'!

A>'!

B>'!

0

SE'

*E'

AE'

BE'

0

S!?'

*!?'

A!?'

B!?'

0

S!'!@

*!'!@

A!'!@

B!'!@

Cout

C>

!

CE

!

C!?

!

!

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AddersSlide 23CMOS VLSI Design

Carry-S%ip PG Diagra#

For k n-bit group$ 13 ( nk2

skipt =

!?@>DEF!!!!?!@!>!!

!' !>' !@' !?' !!' !' F' E' D' ' ' >' @' ?' !' '!'

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AddersSlide 24CMOS VLSI Design

Carry-S%ip PG Diagra#

For k n-bit group$ 13 ( nk2

( )skip xor 2 1 ( 1)pg AOt t n k t t = + + +

!?@>DEF!!!!?!@!>!!

!' !>' !@' !?' !!' !' F' E' D' ' ' >' @' ?' !' '!'

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AddersSlide 25CMOS VLSI Design

Varia&le Group Si'e

9elay gro#$ a$ 41$rt1322

!?@>DEF!!!!?!@!>!!

!' !>' !@' !?' !!' !' F' E' D' ' ' >' @' ?' !' '!'

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AddersSlide 26CMOS VLSI Design

Carry-Loo%a(ead Adder

Carry-lookahead adder compute$ &i' for many bit$

in parallel=

7$e$ higher-6alency cell$ #ith more than t#o input$=

Cin

0

S>'!

&>'!

*>'!

A>'!

B>'!

0

SE'

&E'

*E'

AE'

BE'

0

S!?'

&!?'

*!?'

A!?'

B!?'

0

S!'!@

&!'!@

*!'!@

A!'!@

B!'!@

C>

CE

C!?

Cout

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AddersSlide 27CMOS VLSI Design

CLA PG Diagra#

!?@>DEF!!!!?!@!>!!

!' !>' !@' !?' !!' !' F' E' D' ' ' >' @' ?' !' '!'

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AddersSlide 28CMOS VLSI Design

)ig(er-Valency Cells

i'

i'k k-!'l l-!'m m-!'

&i'k

&k-!'l

&l-!'m

&m-!'

&i'

*i'

*i'k

*k-!'l

*l-!'m

*m-!'

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AddersSlide 29CMOS VLSI Design

Carry-Select Adder

Trick for critical path$ dependent on late input G

% *recompute t#o po$$ible output$ for G ( " !

% Select proper output #hen G arri6e$

Carry-$elect adder precompute$ n-bit $um$% For both po$$ible carrie$ into n-bit group

Cin0

A>'!

B>'!

S>'!

C>

0

0

!

AE'

BE'

SE'

CE

0

0

!

A!?'

B!?'

S!?'

C!?

0

0

!

A!'!@

B!'!@

S!'!@

Cout

!

!

!

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AddersSlide 30CMOS VLSI Design

Carry-Incre#ent Adder

Factor initial *& and final G4R out of carry-$elect

B'>

C'>

D'>

F'E

!'E

!!'E

!@'!?

!>'!?

!B'!?

!?@>DEF!!!!?!@!>!

!' !>' !@' !?' !!' !' F' E' D' ' ' >' @' ?' !' '

increentt =

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AddersSlide 32CMOS VLSI Design

Varia&le Group Si'e

Al$o buffer

noncritical

$ignal$

@'?'>

'>

E'D

F'D

!?'!!

!@'!!

!>'!!

!'!!

!'D

@'?'>

'>

E'D

F'D

!?'!!

!@'!!

!>'!!

!'!!

!'D '

@'

!'

!?@>DEF!!!!?!@!>!

!' !>' !@' !?' !!' !' F' E' D' ' ' >' @' ?' !' '

!?@>DEF!!!!?!@!>!

!' !>' !@' !?' !!' !' F' E' D' ' ' >' @' ?' !' '

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AddersSlide 33CMOS VLSI Design

*ree Adder

If lookahead i$ good" lookahead acro$$ lookahead

% Recur$i6e lookahead gi6e$ 41log 32 delay

.any 6ariation$ on tree adder$

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AddersSlide 34CMOS VLSI Design

Brent-Kung

!'@'?'>D''E!!'!!@'!?!'!>

@'D'>!!'E!'!?

D'!'E

!!'

''!@'

!?@>DEF!!!!?!@!>!

!' !>' !@' !?' !!' !' F' E' D' ' ' >' @' ?' !' '

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AddersSlide 35CMOS VLSI Design

S%lans%y

!'

?'@'

@'?'>D''E!!'!!@'!?!'!>

'>D'>!'E!!'E!>'!?!'!?

!?'E!@'E!>'E!'E

!?@>DEF!!!!?!@!>!

!'!>'!@'!?'!!'!' F' E' D' ' ' >' @' ?' !' '

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AddersSlide 36CMOS VLSI Design

Kogge-Stone

!'?'!@'?>'@'>'D'E'D'E!'!!'!!?'!!!@'!?!>'!@!'!>

@'>'!'?'@D'>E''!'D!!'E!?'!@'!!>'!!!'!?

>'''D'E'!'?!'@!!'>!?'!@'!>'D!'E

?'

!?@>DEF!!!!?!@!>!

!'!>'!@'!?'!!'!' F' E' D' ' ' >' @' ?' !' '

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AddersSlide 37CMOS VLSI Design

*ree Adder *a+ono#y

Ideal 3-bit tree adder #ould ha6e

% L( log 3 logic le6el$

% Fanout ne6er eceeding ?

% 3o more than one #iring track bet#een le6el$

9e$cribe adder #ith @-9 taonomy 1l" f" t2

% Logic le6el$' L0 l

% Fanout' ?f0 !

% Jiring track$' ?t

+no#n tree adder$ $it on plane defined by

l 0 f0 t( L-!

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AddersSlide 39CMOS VLSI Design

*ree Adder *a+ono#y

f 1Fanout2

t 1Jire Track$2

l 1Logic Le6el$2

0 (2)

1 (3)

2 (5)

3 (9)

0 (4)

1 (5)

2 (6)

3 (8)

2 (4)

1 (2)

0 (1)

3 (7)

Kogge-Stone

Bent-K!ng

S"#$ns"%

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AddersSlide 40CMOS VLSI Design

)an-Carlson

!'@'?'>D''E!!'!!@'!?!'!>

@''?D'>'!!'E!@'!!'!?

'D''?!!'>!@'!'E

!?@>DEF!!!!?!@!>!

!'!>'!@'!?'!!'!' F' E' D' ' ' >' @' ?' !' '

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AddersSlide 41CMOS VLSI Design

Kno,les ./ 0/ 0/ 01

!'?'!@'?>'@'>'D'E'D'E!'!!'!!?'!!!@'!?!>'!@!'!>

@'>'!'?'@D'>E''!'D!!'E!?'!@'!!>'!!!'!?

>'''D'E'!'?!'@!!'>!?'!@'!>'D!'E

?'

!?@>DEF!!!!?!@!>!

!'!>'!@'!?'!!'!' F' E' D' ' ' >' @' ?' !' '

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AddersSlide 42CMOS VLSI Design

Ladner-Fisc(er

!'@'?'>D''E!!'!!@'!?

@'D'>!!'E!'!?

'D'!@'E!'E

!'!>

!'E !@' !!' '

!?@>DEF!!!!?!@!>!

!'!>'!@'!?'!!'!' F' E' D' ' ' >' @' ?' !' '

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AddersSlide 43CMOS VLSI Design

*a+ono#y e!isited

f 1Fanout2

t 1Jire Track$2

l 1Logic Le6el$2

0 (2)

1 (3)

2 (5)

3 (9)

0 (4)

1 (5)

2 (6)

3 (8)

2 (4)

1 (2)

0 (1)

3 (7)

+ogge-

Stone

Sklan$ky

Brent-

+ung

Han-

Carl$on+no#le$

K?"!"!"!

+no#le$

K>"?"!"!

Ladner-

Fi$cher

Han-

Carl$on

Ladner-

Fi$cher

3e#

1!"!"!2

1c2 +ogge-Stone

!'?'!@'?>'@'>'D'E'D'E!'!!'!!?'!!!@'!?!>'!@!'!>

@'>'!'?'@D'>E''!'D!!'E!?'!@'!!>'!!!'!?

>'''D'E'!'?!'@!!'>!?'!@'!>'D!'E

?'

!?@>DE!!!!?!@!>!

!'!> '!@'!? '!! '!' ' E ' D ' ' ' > ' @ ' ? ' ! ' '

1e2 +no#le$ K?"!"!"!

!'?'!@'?>'@'>'D'E'D'E!'!!'!!?'!!!@'!?!>'!@!'!>

@'>'!'?'@D'>E''!'D!!'E!?'!@'!!>'!!!'!?

>'''D'E'!'?!'@!!'>!?'!@'!>'D!'E

?'

!?@>DE!!!!?!@!>!

!' !>' !@ '!?' !! '!' ' E ' D ' ' ' > ' @ ' ? ' ! ' '

1b2 Sklan$ky

!'

?'@'

@'?'>D''E!!'!!@'!?!'!>

'>D'>!'E!!'E!>'!?!'!?

!?'E!@'E!>'E!'E

!?@>DE!!!!?!@!>!

!' !> '!@' !? '!!' !' ' E ' D ' ' ' > ' @ ' ? ' ! ' '

!'@'?'>D''E!!'!!@'!?

@'D'>!!'E!'!?

'D'!@'E!'E

!'!>

!'E !@' !!' '

!?@>DE!!!!?!@!>!

!' !>' !@' !?' !!' !' ' E' D' ' ' >' @' ?' !' '

1f2Ladner-Fi$cher

1a2 Brent-+ung

!'@'?'>D''E!!'!!@'!?!'!>

@'D'>!!'E!'!?

D'!'E

!!'

''!@'

!?@>DE!!!!?!@!>!

!'!> '!@'!? '!!'! ' ' E ' D ' ' ' > ' @ ' ? ' ! ' '

!'@'?'>D''E!!'!!@'!?!'!>

@''?D'>'!!'E!@'!!'!?

'D''?!!'>!@'!'E

!?@>DE!!!!?!@!>!

! '! >'! @' !? ' !! ' ! ' ' E ' D ' ' ' > ' @ ' ? ' ! ' '

1d2 Han-Carl$on

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Su##ary

&'ite't!e C#$ssii'$tion Logi'

Le*e#s

M$+

,$no!t

$'"s Ce##s

Carry-Ripple 3-! ! ! 3

Carry-Skip n(> 3M> 0 ? ! !=?3

Carry-Inc= n(> 3M> 0 ? > ! ?3

Brent-+ung 1L-!" " 2 ?log?3 % ! ? ! ?3Sklan$ky 1" L-!" 2 log?3 3M? 0 ! ! = 3log?3

+ogge-Stone 1" " L-!2 log?3 ? 3M? 3log?3

Adder architecture$ offer area M po#er M delay tradeoff$=

Choo$e the be$t one for your application=