Lecture 12 - Jon TseLecture 12 Logic Families I Professor Sunil Bhave CU School of Electrical and...

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Transcript of Lecture 12 - Jon TseLecture 12 Logic Families I Professor Sunil Bhave CU School of Electrical and...

Page 1: Lecture 12 - Jon TseLecture 12 Logic Families I Professor Sunil Bhave CU School of Electrical and Computer Engineering March 10, 2010 Ratioed Logic Ratioed Logic VDD LoadRL VDD VDD
Page 2: Lecture 12 - Jon TseLecture 12 Logic Families I Professor Sunil Bhave CU School of Electrical and Computer Engineering March 10, 2010 Ratioed Logic Ratioed Logic VDD LoadRL VDD VDD
sunil
Rectangle
Page 3: Lecture 12 - Jon TseLecture 12 Logic Families I Professor Sunil Bhave CU School of Electrical and Computer Engineering March 10, 2010 Ratioed Logic Ratioed Logic VDD LoadRL VDD VDD
Page 4: Lecture 12 - Jon TseLecture 12 Logic Families I Professor Sunil Bhave CU School of Electrical and Computer Engineering March 10, 2010 Ratioed Logic Ratioed Logic VDD LoadRL VDD VDD
Page 5: Lecture 12 - Jon TseLecture 12 Logic Families I Professor Sunil Bhave CU School of Electrical and Computer Engineering March 10, 2010 Ratioed Logic Ratioed Logic VDD LoadRL VDD VDD

Lecture 12Lecture 12

Logic Families I

Professor Sunil BhaveCU School of Electrical and Computer p

Engineering

March 10, 2010

Ratioed Logic

Ratioed Logicg

VDD

RLLoad

VDD VDD

V

Resistive DepletionLoad

PMOSLoadVT < 0

PDNIn1In2I

FIn1In2I

F

PDNIn1In2I

FVSS

PDN

VSS

In3

VSS

In3

VSS

In3

(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS

Goal: to reduce the number of devices over complementary CMOSGoal: to reduce the number of devices over complementary CMOS

Ratioed LogicgVDD

N i L d

RLLoadResistive

N transistors + Load

• VOH = VDD

•

F

• VOL = RPN

RPN + RL

PDNIn1In2In3

• Assymetrical response

• Static power consumption

VSS

3 p p

• tpL= 0.69 RLCL

Page 6: Lecture 12 - Jon TseLecture 12 Logic Families I Professor Sunil Bhave CU School of Electrical and Computer Engineering March 10, 2010 Ratioed Logic Ratioed Logic VDD LoadRL VDD VDD

Active LoadsVDD VDD

VSS

DepletionLoad

PMOSLoadVT < 0

In1

F

In1

F

VSS

In2In3

PDNIn2In3

PDN

VSS VSS

depletion load NMOS pseudo-NMOS

Pseudo-NMOS

VDDDD

FCA B C D CL

VOH = VDD (similar to complementary CMOS)O p y

kn VDD VTn–( )VOLVOL

2

2-------------–

⎝ ⎠⎜ ⎟⎛ ⎞ kp

2------ VDD VTp–( )

2=

VOL VDD VT–( ) 1 1kpkn------–– (assuming that VT VTn VTp )= = =

SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!

P d NMOS VTCPseudo-NMOS VTC

2.5

3.0

1 5

2.0

]

W/Lp = 4

1.0

1.5

Vou

t[V

]

W/Lp = 2

W/L = 1W/L = 0 5

0.0 0.5 1.0 1.5 2.0 2.50.0

0.5W/Lp = 1

W/Lp = 0.25

W/Lp 0.5

Vin [V]

Improved Loadsp

V

M1

VDD

F

M1M2 M1 >> M2Enable

A B C D

F

CL

Ad ti L dAdaptive Load

Page 7: Lecture 12 - Jon TseLecture 12 Logic Families I Professor Sunil Bhave CU School of Electrical and Computer Engineering March 10, 2010 Ratioed Logic Ratioed Logic VDD LoadRL VDD VDD

Improved Loads (2)p ( )VDD VDD

M1 M2

Out Out

APDN1 PDN2A

BB

VSS VSS

Differential Cascode Voltage Switch Logic (DCVSL)g g ( )

DCVSL Examplep

Out

B B B B

Out

B

A A

B B B

XOR-NXOR gate

DCVSL T i t RDCVSL Transient Response

2.5

1.5

ge[V

] A B

A B

0.5

Vol

tag A B

A,BA,B

0 0.2 0.4 0.6 0.8 1.0-0.5

Time [ns][ ]


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