ESE 570: Digital Integrated Circuits and VLSI Fundamentalsese570/spring2016/handouts/lec15.pdfVLSI...
Transcript of ESE 570: Digital Integrated Circuits and VLSI Fundamentalsese570/spring2016/handouts/lec15.pdfVLSI...
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ESE 570: Digital Integrated Circuits and VLSI Fundamentals
Lec 15: March 3, 2016 Combination Logic: Ratioed & Pass Logic,
and Performance
Penn ESE 570 Spring 2016 – Khanna
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Lecture Outline
! CMOS NOR2 Worst Case Analysis ! Pass Transistor Logic ! Performance
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Parasitic Caps for NOR2 (worst case)
3
Vx
2Cg
Cdbn1 = Cdbn2 = Cd
Cdbp1 = Cdbp2 = Cd
Csb1p = Csb2p = Cd Cd
Cd
Cd
Cd Cd
V1 = 0, V2 = VDD-> 0 @t=0 & Vx ≈ Vout = 0 -> VDD
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Parasitic Caps for NOR2 (worst case)
4
Vx
2Cg
Cdbn1 = Cdbn2 = Cd
Cdbp1 = Cdbp2 = Cd
Csb1p = Csb2p = Cd Cd
Cd
Cd
Cd Cd
V1 = 0, V2 = VDD-> 0 @t=0 & Vx ≈ Vout = 0 -> VDD
Elmore Model? Cload-NR2 ≈ 2Cd + 3Cd + Cint + 2Cg
RpEQV = Rp2+Rp1
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Parasitic Caps for NOR2 (worst case)
5
Vx
2Cg
Cd
Cd
Cd
Cd Cd
Penn ESE 570 Spring 2016 – Khanna
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Parasitic Caps for NOR2 (worst case)
6
Vx
2Cg
Cd
Cd
Cd
Cd Cd
Penn ESE 570 Spring 2016 – Khanna
τ = (2Cd)(Rp2)+(3Cd+Cint+2Cg)(Rp1+Rp2)
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Parasitic Caps for NOR2 (worst case)
7
Vx
2Cg
Cdbn1 = Cdbn2 = Cd
Cdbp1 = Cdbp2 = Cd
Csb1p = Csb2p = Cd Cd
Cd
Cd
Cd Cd
V1 = 0, V2 = 0 ->VDD @t=0 & Vx ≈ Vout=VDD-> 0
Penn ESE 570 Spring 2016 – Khanna
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Parasitic Caps for NOR2 (worst case)
8
Vx
2Cg
Cdbn1 = Cdbn2 = Cd
Cdbp1 = Cdbp2 = Cd
Csb1p = Csb2p = Cd Cd
Cd
Cd
Cd Cd
V1 = 0, V2 = 0 ->VDD @t=0 & Vx ≈ Vout=VDD-> 0
Elmore Model? Penn ESE 570 Spring 2016 – Khanna
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Parasitic Caps for NOR2 (worst case)
9
Vx
2Cg
Cd
Cd
Cd
Cd Cd
Penn ESE 570 Spring 2016 – Khanna
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Parasitic Caps for NOR2 (worst case)
10
Vx
2Cg
Cd
Cd
Cd
Cd Cd
Penn ESE 570 Spring 2016 – Khanna
τ = (2Cd)(Rp1+Rn2)+(3Cd+Cint+2Cg)(Rn2)
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Pass Transistor Logic
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Teaser
! What does this do?
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Identify Function
! What function is this?
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Output
! What is Vout if A=1, B=1?
14
A B Y
0 0
0 1
1 0
1 1
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Output
! What is Vout if A=1, B=1?
15
A B Y
0 0
0 1
1 0
1 1 0
Penn ESE 570 Spring 2016 – Khanna
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Output
! What is Vout if A=0, B=1?
16
A B Y
0 0
0 1
1 0
1 1 0
Penn ESE 570 Spring 2016 – Khanna
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Output
! What is Vout if A=0, B=1?
17
A B Y
0 0
0 1 1
1 0
1 1 0
Penn ESE 570 Spring 2016 – Khanna
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Output
! What is Vout if A=0, B=0? if A=1, B=0?
18
A B Y
0 0
0 1 1
1 0
1 1 0
Penn ESE 570 Spring 2016 – Khanna
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Output
! What is Vout if A=0, B=0? if A=1, B=0?
19
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
Penn ESE 570 Spring 2016 – Khanna
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Area
! Compare PT with CMOS circuit?
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Output
! Is this a regenerating/restoring gate?
21
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
Penn ESE 570 Spring 2016 – Khanna
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Output
! What does output look like (DC transfer)? " (B=1, notB=0, sweep A, notA=CMOS inv(A))
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Pass TR transfer (B=1)
23 Sweep A
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CMOS Inverter Transfer
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Reasonable Input to CMOS Inverter?
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Pass Transistor xor2 with inv restore
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Compare CMOS
! Is this a fair comparison?
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Required to use?
! What should we add to make substitutable with CMOS?
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Restore Output
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Restore Output
! Area? (compare to CMOS)
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Chain Together
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Analyze Stage
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Delay A=1, B=0, CDB=Cdiff=0?
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Delay A=1, B=0, Cdiff=0?
! What’s the equivalent RC circuit?
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Delay A=1, B=0, Cdiff=0?
! What’s the equivalent RC circuit?
35 Penn ESE 570 Spring 2016 – Khanna
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Delay A=1, B=1, Cdiff=0?
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Delay A=1, B=1, Cdiff=0?
! What’s the equivalent RC circuit?
37 Penn ESE 570 Spring 2016 – Khanna
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Delay A=1, B=1, Cdiff=0?
! What’s the equivalent RC circuit? " What are we ignoring?
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Cdiff>0
39 Penn ESE 570 Spring 2016 – Khanna
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Contact/Diffusion Capacitance
! Cj – diffusion depletion ! Cjsw – sidewall capacitance ! LS – length of diffusion
40
€
Cdiff = C jLSW +C jsw 2LS +W( )
LS
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Inverter Delay
! Delay driving another min-sized inverter? " Include Cdiff
41
W=1
Penn ESE 570 Spring 2016 – Khanna
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Delay A=1, B=1, Cdiff≠0? (W=1)
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43
! What’s the equivalent RC circuit?
Delay A=1, B=1, Cdiff≠0? (W=1)
Penn ESE 570 Spring 2016 – Khanna
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Bonus
! What does this do?
44
A
B
A B Y
0 0
0 1
1 0
1 1
Penn ESE 570 Spring 2016 – Khanna
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Transmission Gates
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CMOS Transmission Gates
46
Kenneth R. Laker, University of Pennsylvania,
updated 26Feb15
Penn ESE 570 Spring 2016 – Khanna
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CMOS Transmission Gates
47
Kenneth R. Laker, University of Pennsylvania,
updated 26Feb15
at t = 0-: Vin = 0, Vout = 0 at t = 0+: Vin = 0 -> VDD
Note
Penn ESE 570 Spring 2016 – Khanna
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CMOS Transmission Gates
48
Kenneth R. Laker, University of Pennsylvania,
updated 26Feb15
at t = 0-: Vin = 0, Vout = 0 at t = 0+: Vin = 0 -> VDD
Note
- VTp
≥ ≥
≤
Penn ESE 570 Spring 2016 – Khanna
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CMOS Transmission Gates
49
Kenneth R. Laker, University of Pennsylvania,
updated 26Feb15
at t = 0-: Vin = 0, Vout = 0 at t = 0+: Vin = 0 -> VDD
Note
- VTp
≥ ≥
≤
Penn ESE 570 Spring 2016 – Khanna
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CMOS Transmission Gates
50
Kenneth R. Laker, University of Pennsylvania,
updated 26Feb15
at t = 0-: Vin = 0, Vout = 0 at t = 0+: Vin = 0 -> VDD
Note
- VTp
≥ ≥
≤
Penn ESE 570 Spring 2016 – Khanna
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CMOS Transmission Gates
51 - VTp
≥ ≥
≤
Penn ESE 570 Spring 2016 – Khanna
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Transmission Gate, Req
52
kp (- VDD - VTp)2
kp [2(- VDD - Vtp) (Vout – VDD) - (Vout – VDD)2]
kp [2(- VDD - Vtp) - (Vout – VDD)]
kp [2(- VDD - Vtp) (Vout – VDD) - (Vout – VDD)2]
kp [2(- VDD - Vtp) - (Vout – VDD)]
Penn ESE 570 Spring 2016 – Khanna
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Kenneth R. Laker, University of Pennsylvania,
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Transmission Gate, Req
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Kenneth R. Laker, University of Pennsylvania,
updated 26Feb15
Transmission Gate, Req
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Transmission Gate Layouts
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Kenneth R. Laker, University of Pennsylvania,
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Performance Design
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NOR2 Layout
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Kenneth R. Laker, University of Pennsylvania,
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NAND2 Layout
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Layout of Complex CMOS Gate
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Kenneth R. Laker, University of Pennsylvania,
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DS DSGND
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Layout of Complex CMOS Gate
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Kenneth R. Laker, University of Pennsylvania,
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Penn ESE 570 Spring 2016 – Khanna
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Kenneth R. Laker, University of Pennsylvania,
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d
d d
d
d
i.e. n, p Euler paths with identical sequences of inputs
.
diffusion breaks
Layout of Complex CMOS Gate
Penn ESE 570 Spring 2016 – Khanna
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Minimize Number of Diffusion Paths
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Kenneth R. Laker, University of Pennsylvania,
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Penn ESE 570 Spring 2016 – Khanna
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Minimize Number of Diffusion Paths
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Kenneth R. Laker, University of Pennsylvania,
updated 26Feb15
Penn ESE 570 Spring 2016 – Khanna
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Minimize Number of Diffusion Paths
64
Kenneth R. Laker, University of Pennsylvania,
updated 26Feb15
Penn ESE 570 Spring 2016 – Khanna
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Minimize Number of Diffusion Paths
65
Kenneth R. Laker, University of Pennsylvania,
updated 26Feb15
Penn ESE 570 Spring 2016 – Khanna
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Gate Layout Algorithm
! 1. Find all Euler paths that cover the graph ! 2. Find common n- and p- Euler paths ! 3. 3. If no common n- and p- Euler paths are found
in step 2, partition the gate n- and p- graphs into the minimum number of sub-graphs that will result in separate common n- and p- Euler paths
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Kenneth R. Laker, University of Pennsylvania,
updated 26Feb15
Penn ESE 570 Spring 2016 – Khanna
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Idea
! CMOS " Design for worst case input switching case and delay
! There are other logic disciplines " Ratioed logic " Can use pass transistors for logic
" Transmission gates " Will see in use in dynamic logic
! Gate layout optimization " Euler Paths
67 Penn ESE 570 Spring 2016 – Khanna
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Midterm Exam
! Midterm – 3/15 " In class in Towne 303
" Starts at exactly 4:30pm, ends at exactly 5:50pm (80 minutes) " Covers Lec 1- 14 (slides 1-26) " Closed book, no notes or cheat sheets " Calculators allowed " Old exams posted online with and without solutions
" Review Session by TA on Sunday 3/13 7-8:30pm in Moore 100C
" Office Hours " cancelled during spring break, use Piazza for questions " Tania: Monday (3/14) 2-4pm and Tuesday (3/15) 12-2pm " Di and Ao: Monday (3/14) 7-9pm in TBD
68 Penn ESE 570 Spring 2016 – Khanna
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Midterm Topics List
! Identify CMOS/non-CMOS
! Any logic function #$ CMOS gate
! Noise Margins ! Circuit first order
switching rise/fall times " Output equivalent
resistance " Load capacitance
! Transistor " Regions of operation " Parasitic Capacitance
Model
! Layout and stick diagrams
! Sizing ! Lumped 1st order delay
" Worst case estimation
! Elmore-delay " Worst case estimation
69 Penn ESE 570 Spring 2016 – Khanna
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Admin
! Happy Spring Break!
70 Penn ESE 570 Spring 2016 – Khanna