Jvc Gr-dvm5 Technical Guide

VIDEO TECHNICAL GUIDE

COPYRIGHT © 1999 VICTOR COMPANY OF JAPAN, LTD. March 1999

GR-DVM5 NTSC/PAL

DIGITAL VIDEO MOVIE

INDEX

INDEX-1

SECTION 1 OUTLINE OF THE PRODUCT1.1 DIFFERING POINTS BETWEEN MODELS ................................................................................. 1-1

1.1.1 Table list differing points between models(GR-DV1/GR-DVM1/GR-DVX/GR-DVL9000/GR-DVM5/DV3) ........................................................ 1-1

SECTION 2 OPERATION OF MECHANISM2.1 OPERATION OF LOADING CONTROL ....................................................................................... 2-1

2.1.1 Motor bracket assembly and Rotary encoder operation ......................................................... 2-32.1.2 Tension arm and pad arm assembly operation....................................................................... 2-42.1.3 Slide deck assembly and loading brake assembly operation.................................................. 2-42.1.4 Rail assembly and slant pole arm assembly operation........................................................... 2-42.1.5 Sub brake assembly and release guide operation.................................................................. 2-42.1.6 Charge arm assembly and pinch roller arm assembly operation ............................................ 2-5

2.2 OPERATION OF MECHANISM.................................................................................................... 2-62.2.1 Outline ................................................................................................................................... 2-62.2.2 Mechanism modes................................................................................................................. 2-6

SECTION 3 CIRCUIT DESCRIPTION3.1 DESCRIPTION OF CCD OPERATIONS ...................................................................................... 3-1

3.1.1 CCD pin assignment .............................................................................................................. 3-33.1.2 CCD pin functions.................................................................................................................. 3-33.1.3 Electrical Image Stabilizer...................................................................................................... 3-4

3.2 V. DRIVER ................................................................................................................................... 3-53.2.1 V. DRIVER (IC5501) pin functions.......................................................................................... 3-5

3.3 T. G .............................................................................................................................................. 3-63.3.1 T. G (IC5502) pin functions .................................................................................................... 3-6

3.4 CDS AGC..................................................................................................................................... 3-73.4.1 CDS AGC (IC5601) pin assignment....................................................................................... 3-73.4.2 CDS AGC (IC5601) pin functions........................................................................................... 3-8

3.5 ADC FUNCTION .......................................................................................................................... 3-93.5.1 ADC (IC4201) pin functions ................................................................................................... 3-9

3.6 Focus & zoom driver .................................................................................................................. 3-103.6.1 Focus & Zoom driver (IC4851) pin assignment .................................................................... 3-103.6.1 Focus & Zoom driver (IC4851) pin functions ........................................................................ 3-11

3.7 YMCA & SSG............................................................................................................................. 3-123.7.1 YMCA & SSG (IC4301) pin assignment ............................................................................... 3-123.7.2 YMCA & SSG (IC4301) pin functions................................................................................... 3-13

3.8 FM.............................................................................................................................................. 3-173.8.1 FM (IC4302) pin functions.................................................................................................... 3-17

3.9 DVIO FUNCTION....................................................................................................................... 3-173.9.1 DVIO (IC3202) pin assignment ............................................................................................ 3-173.9.2 DVIO (IC3202) pin functions ................................................................................................ 3-193.9.3 PLL circuit description.......................................................................................................... 3-23

1-2

3.10 COMPRESS/AUDIO/SHUFFLE (CAS) FUNCTION.................................................................. 3-243.10.1 CAS IC3001 pin assignment .............................................................................................. 3-243.10.2 CAS IC3001 pin functions .................................................................................................. 3-25

3.11 ECC/DCI/ATF (EDA) FUNCTION ............................................................................................. 3-283.11.1 EDA IC3003 pin assignment .............................................................................................. 3-283.11.2 EDA (IC3003) pin functions................................................................................................ 3-29

3.12 PB EQ FUNCTION................................................................................................................... 3-333.12.1 PB EQ (IC3501) pin assignment ........................................................................................ 3-333.12.2 PB EQ (IC3501) pin functions ............................................................................................ 3-343.12.3 PB EQ circuit ..................................................................................................................... 3-36

3.13 PRE/REC FUNCTION.............................................................................................................. 3-373.13.1 PRE/REC (IC3502) pin assignment ................................................................................... 3-373.13.2 PRE/REC (IC3502) pin functions ....................................................................................... 3-38

3.14 Digital interface FUNCTION ..................................................................................................... 3-403.14.1 Digital IF (IC8001) pin assignment ..................................................................................... 3-403.14.2 Digital IF (IC8001) pin functions ......................................................................................... 3-41

3.15 monitor function........................................................................................................................ 3-443.15.1 LCD driver (IC7201) pin assignment .................................................................................. 3-473.15.2 LCD driver (IC7201) pin functions ...................................................................................... 3-48

3.15.3 LCD SUBTG (IC7203) pin assignment............................................................................... 3-503.15.4 LCD SUBTG (IC7203) pin functions................................................................................... 3-50

3.16 MIC CIRCUIT ........................................................................................................................... 3-51

3.17 SYSCON CPU ......................................................................................................................... 3-523.17.1 SYSCON CPU (IC1001) pin functions................................................................................ 3-52

3.18 MSD CPU................................................................................................................................. 3-563.18.1 MSD CPU (IC1401) pin functions....................................................................................... 3-56

3.19 MDA FUNCTION...................................................................................................................... 3-603.19.1 MDA (IC1601) pin assignment ........................................................................................... 3-603.19.2 MDA (IC1601) pin functions ............................................................................................... 3-61

SECTION 4 ERROR RATE ADJUSTMENT·PB EQ (Error Rate) Adjustment......................................................................................................... 4-1

SECTION 1OUTLINE OF THE PRODUCT

1-1

1.1 DIFFERING POINTS BETWEEN MODELS1.1.1 Table list differing points between models (GR-DV1/GR-DVM1/GR-DVX/GR-DVL9000/GR-DVM5/DV3)-1/4

ModelFunctionBattery Single cell BN-V712

(3.6V, 1250 mAh)When charging twobatteries, charging ofboth is completed at thesame timeCharging one battery:140 min.Charging two batteries:210 min.Continuous shootingtime: 30 min.

2 cells BN-V812(2.2V, 1250 mAh)When charging twobatteries continuously,they are charged in theorder attachedCharging one battery:100 min.Charging two batteries:200 min.Continuous shootingtime: 60 min.

2 cells BN-V907(7.2V, 750 mAh)When charging twobatteries continuously,they are charged in theorder attachedCharging one battery:100 min.Charging two batteries:200 min.Continuous shootingtime: 45 min.(When VF is used)

2 cells BN-V814(7.2V, 1400 mAh) (BN-V812 available)When charging twobatteries continuously,they are charged in theorder attachedCharging one battery:110 min.Charging two batteries:220 min.Continuous shootingtime: 100 min.

2 cells BN-V607(7.2V, 770 mAh) (BN-V615 available)At AA-V68 used:When charging twobatteries continuously,they are charged in theorder attachedCharging one battery:90 min. (BN-V607) /180 min. (BN-V615)Charging two batteries:180 min. (BN-V607) /360 min. (BN-V615)

Continuous shootingtime: 40 min.(When LCD is used)

(When VF is used)Continuous shootingtime: 80 min.(When LCD is used)

At AA-V60 used:To charge the batterypack installed in thecamcorder, be sure toswitch off thecamcorder first.If two battery packs areattached to the ACcharger station (oneattached to the ACcharger station and onein the camcorderattached to it), they willbe charged in the orderthat they were attached.The charging time fortwo BN-V607 batterypacks is approx. 190min.

Charging of Batteryin the unit bydocking station

Yes No No(Can be performed byGV-DS2)

No docking station ←

Weight main unit:Approx. 450gduring shooting: Approx.520g(Including battery BN-V712, tape M-DV30ME,hand strap)

main unit:Approx. 520gduring shooting: Approx.730g(Including battery BN-V812, tape M-DV30ME,hand strap)

main unit:Approx. 500gduring shooting: Approx.590g(Including battery BN-V907, tape M-DV30ME)

main unit:Approx. 670gduring shooting: Approx.780g(Including battery BN-V814, tape M-DV30ME)

main unit:Approx.440g (GR-DVM5) / 630g(GR-DV3)during shooting: Approx.530g (GR-DVM5) / 510g(GR-DV3)(Including battery BN-V607, tape M-DV30ME)

GR-DVM5/DV3GR-DV1 GR-DVM1 GR-DVX GR-DVL9000

Table 1-1-1 Table list differing points between models (GR-DV1/GR-DVM1/GR-DVX/GR-DVL9000/GR-DVM5/DV3)-1/4

1-2

• Table list differing points between models (GR-DV1/GR-DVM1/GR-DVX/GR-DVL9000/GR-DVM5/DV3)-2/4

ModelFunctionViewfinder Yes

0.55"Horizontal resolution260 linesHigh temperaturepolycrystal silicontransistor

No Yes0.55"Horizontal resolution:260 linesHigh temperaturepolycrystal silicontransistor

← ←

Lens cover Yes(Finder operationlinked)

No(With lens protectionglass)

Yes(Finder/LCD linked)

YesMotor-driven(Power SW/Finder/LCDlinked)

←

LCD monitor None YesThe image can beturned off2.5"Horizontal resolution:400 linesLow temperaturepolycrystal silicontransistor

Yes (Priority toViewfinder)The image can not beturned off2.5"Horizontal resolution:400 linesLow temperaturepolycrystal silicontransistor

Yes (Priority toViewfinder)4"Horizontal resolution:240 linesAmorphous silicontransistor

Yes (Priority toViewfinder)2.5"Horizontal resolution:350 linesLow temperaturepolycrystal silicontransistor

Image device 1/3" 570k (670k) pixelsEffective area 330k(420k) pixels2-line accumulationtransfer

← ← 1/3" 380k (450k) pixelsEffective aria 360k(420k) pixelsProgressive scan CCDJVC originalComplementary Colorfilter

1/4" 460k (540k) pixelsEffective aria 290k(350k) pixels

Progressivescanning

No ← ← Yes No

Electric ImageStabilizer

Excess pixel method ← ← Magnification method ←

Sensitivity 7 lux (Shutter 1/30seconds)

← ← 4.7 lux (shutter 1/60second)

6 lux (GR-DVM5)7lux (GR-DV3)(shutter 1/60 second)

Lens specification F1.6 f=4.5 to 45 mm ← ← F1.2 f=5.0 to 50 mm F1.8 f=3.6 to 36 mm

Zoom Ratio Optical zoom: 10xElectronic zoom: 2x/10xTotal zoom: 100x

← ← Optical zoom: 10XElectronic zoom:4X/20X(10X)Total zoom: 200X(100X)

Optical zoom: 10XElectronic zoom:4X/10XTotal zoom: 100X



1-3


ModelFunctionSnapshot Only frame Can select whether to

set the frame or notThe shutter sound canbe turned on and offusing the "Buzzer/tarry"of the system menu(Forcibly recorded onthe tape)

← 6 modeWith frame, no-frame,negative/positive(During recording)Pin-up, Pin-up 4-divisionPin-up 9-division

5 modeWith frame, no-frame,Pin-up,Pin-up 4-divisionPin-up 9-division

Snapshot inPlayback

No ← ← Yes (Excludingnegative-positive)

←

Zoom in Playback By main unit/remotecontrol unit

← Only by the remotecontrol unit

←(Maximum 10 times)

←(Maximum 10 times)

Auto flash No ← Yes No ←

LP mode No Yes(After LP recording,Audio dubbing andInsert editing cannot beperformed)

← ← ←

Audio 2 ch (48k)/4 ch (32k)initial setting 48 kHz(After recording editingcannot be performed for48 kHz recording)

2 ch (48k)/4 ch (32k)initial setting 32 kHz

← ← 2 ch (48k)/4 ch (32k)initial setting 48 kHz(After recording editingcannot be performed for48 kHz recording)

Snapshot search Yes ← No ← ←

Record end search Yes No ← ← ←

Audio dubbing andInsert editing

Docking station isrequired

← Docking station is notrequired

← No

Time code In the case of shootingfrom an unrecordedportion of the tape, theapproximate time codeis calculated andrecorded (changed toDVM1/DVXspecifications fromhalfway)

In the case of shootingfrom the unrecordedportion of the tape, thetime code is recordedfrom 00:00:00

← ← ←



1-4


ModelFunctionHeadphone terminal No Yes Yes (Shared with AV

terminal)← ←

AV-integratedoutput terminal

Yes No (Audio, videoseparately)

Yes (Shared withheadphone terminal)

← ←

S output terminal No (only Dockingstation)

← ← Yes No (only AC chargingstation)

JLIP terminal No (only Dockingstation)

← ← Yes (Shared with stillimage output terminal)

No (only AC chargingstation)

Editing terminal No (only Dockingstation)

← ← Yes No (only AC chargingstation)

Still image outputterminal

No ← ← Yes (Shared with JLIPterminal)

No

DV output terminal No ← ← Yes (Digital In/Out)

JLIP related

Software

JLIP video capture box

GV-CB1JLIP video captureJLIP movie player

JLIP video capturedocking station GV-DS1JLIP video captureJLIP movie player

JLIP video capturedocking station GV-DS2JLIP video captureJLIP video producer

JLIP video capturekit HS-V3KITJLIP video producer HS-V5KIT

JLIP video capturebox GV-CB1JLIP video producer HS-V5KIT

JLIP ID number 7 6 ← ← ←

Remote controlsensor

No (Docking stationonly)

← Yes main unit (GR-DVX) onlyProvided for GV-DS2(When using GV-DS2,the GR-DVX light-receiving sensorbecomes ineffective)

Yes ←

Power ON/OFFbutton in Remotecontrol unit

Yes ← No(However, it can beturned OFF only by theremote control unit ofGR-DV1)

No ←

System backupbutton battery

Primary battery (lifeabout 1 year) can beattached and detachedResetting is performedby removing the battery

← Equipped withsecondary battery (Lifeabout 3 months)solderingUnit has a Reset button

← ←



SECTION 2OPERATION OF MECHANISM

2-1

2.1 OPERATION OF LOADING CONTROLFor flow chart of main parts, refer to Fig. 2-1-1 with the numbers in square brackets following the partname. For further details, refer to the disassembled view, mechanism parts list, electrical parts list in theservice manual.

MAIN DECK(RELAY GEAR)

[M3-401]

SUB CAM

[M3-429]

SYSCON CPU(IC1001)

M D A(IC1601)

MOTOR BRACKET ASSY(MODE CONTROL MOTOR)

[M3-413]

W O R M W H E E L

[M3-415]

ROTARY ENCODER

[M3-417]

CONNECTGEAR

[M3-427]

MAIN CAM

[M3-422]

BRAKE CONTROLASSY

[M3-435] [M3-433]

CONTROLPLATE ASSY

[M3-456]

CATCHER(T) ASSY

[M3-410]

SLANT POLEARM ASSY

[M3-402]

GUIDE ARMASSY

[M3-441]

CLEANERARM ASSY

[M3-404]

CATCHER(T) ASSY

[M3-410]

RAILASSY

[M3-405]

SLIDE LEVERASSY

[M3-426]

SLIDE GUIDEPLATE

[M3-442]

LOADINGBRAKE ASSY

[M3-458]

SLIDE DECKASSY

[M3-472]

RELEASEGUIDE

[M3-458]

SUB BRAKEASSY

[M3-460]

[Refer to 2.1.2]

TC LEVERASSY

[M3-425]

TENSIONA R M

PAD ARMASSY

[M3-446]

[M3-444]

PINCH ROLLERARM ASSY

[M3-431]

CASSETTEHOUSING ASSY

(RELEASE LEVER)

[M3-184]

CHARGE ARMASSY

[Refer to 2.1.3]

[Refer to 2.1.1]

[Refer to 2.1.4]

[Refer to 2.1.6]

[Refer to 2.1.5]

Fig. 2-1-1 Loading operation chart

2-2

2.1.1 Motor bracket assembly and Rotary encoder operation1. Motor bracket assembly [M3-413]The motor bracket assembly includes the Mode control motor and worm gear. The Mode control motordrives the rotary encoder via the worm wheel.The mode control motor performs loading and unloading operations and selects the mechanism mode.Motor on/off and forward/reverse are controlled by the syscon CPU (IC1001). The mode control motorrotation is transmitted via the worm wheel to the rotary encoder of the switch board for detecting andchanging the mechanism mode.

2. Rotary encoder [M3-417]The rotary encoder is composed of the switches and a gear. The switch on/off states are detected fromthe gear rotation. The switch on/off states correspond to each mechanism mode and the data are sentto the syscon CPU (IC1001), The CPU determines the mechanism states from these data and controlsthe mode control, drum and capstan motors.The mode control motor drive force is transmitted by the worm wheel to the rotary encoder, whichcontrols the main cam and sub cam.

3. Main cam [M3-422]The main cam control operations of the supply and take-up loading mechanism and slide deckassembly.Refer to Fig. 2-1-2. There are two control grooves on the main cam. One functions to control the tensionarm and pad arm assembly through the TC lever assembly, and the other functions to control theloading brake assembly and slide guide plate through the slide lever assembly.

To contro l the Sl ide leverassembly [M3-426]

To contro l the TC leverassembly [M3-433]

Fig. 2-1-2 Main cam

4. Sub camThe sub cam control operations of the take-up mechanism, cassette housing assembly and sub brakeassembly.Refer to Fig. 2-1-3. There are two control grooves on the sub cam . One functions to control the controlplate assembly through the brake control assembly, and the other functions to control the pinch rollerarm assembly and cassette housing assembly through the charge arm assembly.

To control thecharge armassembly [M3-433]

To control the brakecontrol assembly[M3-435]

Fig. 2-1-3 Sub cam

2-3

2.1.2 Tension arm and pad arm assembly operationThe TC lever assembly drives the tension arm and pad arm assembly being controlled by the controlgroove on the main cam.

1. Tension arm [M3-444]With operation of the main cam, the tension arm functions to draw out the tape from the supply side aswell as to drive the pad arm assembly being controlled by the control pin on the tension arm.

2. Pad arm assembly [M3-446]With operation of the tension arm, the pad arm assembly applies the brake on the supply reel disk toprevent the tape from slackening in the stand-by status (STOP mode) after the tape was pulled out ofthe cassette.

2.1.3 Slide deck assembly and loading brake assembly operationThe slide lever assembly drives the slide deck assembly through the slide guide plate and loading brakeassembly being controlled by the control groove on the main cam.

1. Loading brake assembly [M3-458]With operation of the slide lever assembly, the loading brake assembly applies the brake on the supplyreel disk to prevent the tape from slacking in the loading and unloading mode.

2. Slide deck assembly [M3-472]The slide deck assembly slides for inserting and taking out the digital video cassette tape according tooperation of the slide lever assembly.The slide deck assembly drives the guide arm assembly and the rail assembly being controlled by thecontrol groove on the main cam via the slide lever assembly.

2.1.4 Rail assembly and slant pole arm assembly operation1. Rail assembly [M3-405]With operation of the slide deck assembly, the rail assembly (supply/take-up guide rail) controlsloading/unloading the cassette tape.

2. Slant pole arm assembly [M3-402]The slide deck assembly drives the slant pole assembly through the guide arm assembly and catcher(T) assembly.With operation of the slide deck assembly, the slant pole arm assembly functions to draw out the tapefrom take-up side as well as to drive the cleaner arm assembly.

2.1.5 Sub brake assembly and release guide operationThe brake control assembly, which is controlled by the control groove on the sub cam, functions to drivethe sub brake assembly (take-up side) and release guide through the control plate assembly.

1. Sub brake assembly [M3-460]With operation of the brake control assembly, the sub brake assembly applies the brake on the take-upreel disk to prevent the tape from slackening in the stand-by status (STOP mode) after the tape waspulled out of the cassette.

2. Release guide [M3-458]In the EJECT mode, the release guide is moved by the control plate assembly so that the digital videocassette tape is correctly sent in place. The release guide also serves to control reel to cassettelocking.

2-4

2.1.6 Charge arm assembly and pinch roller arm assembly operation1. Charge arm assembly [M3-433]Being controlled by the control groove on the sub cam, the charge arm assembly drives the pinch rollerarm assembly and release lever of cassette housing assembly.The charge arm assembly functions to unlock and eject the cassette housing assembly. However, thecassette housing assembly cannot be ejected without slide operation of the slide deck assemblybecause the cassette housing assembly is otherwise locked by it. 2. Pinch roller arm assembly [M3-431]With operation of the charge arm assembly, the pinch roller arm assembly presses the tape to thecapstan shaft.

2-5

2.2 OPERATION OF MECHANISM2.2.1 OutlineMechanism mode is switched by rotation of the mode control motor.Mechanism mode is switched and controlled by the syscon CPU (IC1001) that detects the mechanismstatus with 3-bit signals supplied from the rotary encoder.This model has six mechanism modes.

2.2.2 Mechanism modesThe following roughly explains the six mechanism modes. For details of the respective modes andoperation timing of main mechanism parts, refer to the mechanism modes chart (Fig. 2-2-1).

1. EJECT mode (Assembling mode)This mode is used for ejecting the cassette tape and for assembling the mechanism. Whendisassembling/re-assembling the mechanism, enter the mechanism into this mode before starting thejob. Since the mechanism is generally set in the STOP mode, make sure to refer to the service manualfor shifting the mechanism mode from the STOP mode to the EJECT mode.Namely, set the mechanism to the EJECT mode while applying DC 3V to the motor similarly accordingto the tape taking-out method in Section 1 "TO TAKE OUT CASSETTE TAPE" of service manual.

2. STD-BY modeThe mechanism automatically enters the C-IN mode after it completes the eject operation, and itcontinues to stand by in this mode until a digital video cassette tape is inserted or the cassette housingis closed.

3. SHORT FF modeThe Short FF mode operation is the tape transported in the forward direction to take-up tape slackduring shift to STOP mode from C-IN mode.

4. STOP modeThe STOP mode is the reference position of the mechanism. With insertion of a digital video cassettetape into the cassette housing, the mechanism performs the full loading operation and thenautomatically enters the STOP mode again. Therefore, mode shift of the mechanism to another mode iscarried out in a short time.The mechanism enters the STOP mode in the following conditions.1) When the set is turned on or off (power on/off).

2) When a digital video cassette tape is inserted, the mechanism automatically enters the STOP modefrom the EJECT mode.

3) When the STOP button is pressed in the PLAY, REV, FF/REW mode.

4) When the tape reaches the end in the FF/REW mode.

5. PLAY modeWhen the PLAY button is pressed, the mechanism is shifted to this mode from the STOP mode.

6. REV modeWhen the FF/REV button is pressed, the mechanism enters this mode.

2-6

· Mechanism mode timing chart

Pad Arm Assy(SUP Brake)

Tens ion Arm

Pinch Rol ler ArmAssy

Sub Brake Assy(TU Brake)

Release Guide

Loading BrakeAssy

Eject Lever(Change ArmAssy)

SUP/TU PoleBase(Rai l Assy)

Sl ide Lever Assy

<Sl ide Deck>

Main Cam

Main Cam

EJECT C IN SHORT FF PLAYREVSTOPM o d eParts

H I G H

L O W

H I G H

L O W

H I G H

L O W

0 31.7 45.6 211.5 280.3

Sub Cam

Encoder

SLIDE END SLIDE START

Sub Cam 0 30 43.1 200 265

Encoder 0 33 47.4 220 291.5

C a m S W 1

C a m S W 2

C a m S W 3

49.5

46.8

51.5

74.04

70

77

129.5

122.5

134.7

156.6

148.1

162.9

169.2

160

176

47.2

44.6

49.1

52.0

49.2

54.1

155.5

147.0

161.7

265.0

250.5

275.6

Fig. 2-2-1 Mechanism mode timing chart

SECTION 3CIRCUIT DESCRIPTION

3-1

3.1 DESCRIPTION OF CCD OPERATIONS

Transfer system Interline transfer CCD image sensorOptical size 1/4 inch size formatTotal pixels 766 H × 596 V approx. 460k pixels

(* for PAL model :766H × 711V approx. 540k pixels)Effective pixels 724 H × 582 V approx. 420k pixels

(* for PAL model :724H × 697V approx. 500k pixels)Horizontal drive frequency 13.5MHz drive (DV standard SD mode )Chip size 4.60mm (H) × 3.97mm (V)Unit cell size 5.15µm (H) × 4.70µm (V)

(* for PAL model :5.15µm (H) × 3.95µm (V))Optical black Horizontal (H) Front 2 / Back 40

Vertical (V) Front 12 / Back 2

Dummy bits Horizontal 20Vertical 1 (only even field)

Color filter Ye, Cy, Mg, G Complementary color filter

2

12

402

V

H

1pin

8pin

Fig. 3-1-1 Optical black diagram

3-2

3.1.1 CCD pin assignment

HØ

1

HØ

2

ØS

UB

ØR

G

VØ

1

VØ

2

VØ

3

VO

UT

Pho toSensor

VØ

4

1

Ye

G

Ye

Mg

Ye

G

Cy

Mg

Cy

G

Cy

Mg

Ye

G

Ye

Mg

Ye

G

Horizontal-Register

Ver

tical

-Reg

iste

r

1 4131211108 9

7 6 5 4 3 2G

ND

VD

D

GN

D

*

Cy

Mg

Cy

G

Cy

Mg

VL

CS

UB

*

Fig. 3-1-2 CCD pin location

3.1.2 CCD pin functions

Pin No. Label In/Out Description

1 Vf4 In Vertical register transfer clock




5 VL - Protect transistor bias

6 GND - GND

7 VOUT Out Video signal output

8 VDD - Power supply

9 GND - GND

10 fSUB In Substrate clock

11 CSUB - Substrate bias

12 fRG In Reset gate clock

13 Hf1 In Horizontal register transfer clock

14 Hf2 In Horizontal register transfer clock

Table 3-1-1 pin functions

3-3

3.1.3 Electrical Image StabilizerIn this unit, the extra area in the vertical direction is used as the handshake correction area by using thePAL CCD (effective pixels 724H x 582V) for the NTSC format. Handshake correction in the verticaldirection is carried out by the extra pixel framing method in which the position for the valid area of the 494pixels is corrected based on movement vector detection from the 582-pixel area. However there is noextra pixel area in the horizontal direction, and reproducing images using the NTSC format will also resultin oblong pictures. In this case, electronic zooming is carried out in which 611 pixels in the horizontaldirection are enlarged 1.2 times to 720 pixels with interpolation pixels. By controlling the reading positionof the line memory and changing the framing position of the 611 pixels, handshake in the horizontaldirection is corrected.The camera images of this unit are always electronic-zoomed in the horizontal direction by 1.2 times (evenwhen handshake correction is OFF), therefore the angle of view cannot be changed by turning handshakecorrection ON or OFF. The actual resolution (number of pixels) is however 611H x 480V, approx. 290000pixels.(*For PAL models, a CCD called special PAL (effective pixels 724H x 697V) is used, the actual resolution(number of pixels) is 601H x 576V, approx. 350000 pixels.)

582

724

494

Vert ical EIS operat ioncontrol led cutt ing out posit ion

Us ing PAL CCDfor NTSC camera The image in NTSC

monitor

494

611

1.2 X Digi tal ZoomHorizontal :611 ® 720

(*601 ® 720)Horizontal EIS operat ion

control led l ine memory access

(*697) (*582)

(*582)

(*601)

The image on NTSCmonitor

Fig. 3-1-3 Electrical Image Stabilizer

3-4

3.2 V. DRIVER

3.2.1 V. DRIVER (IC5501) pin functions


1 OSUB Out Substrate pulse output

2 VL - Low level power supply (-6.5V)

3 OV2 Out V2 transmission pulse output (2 state)

4 VM13 - Middle level power supply (GND)


6 VCC - Power supply for input section (3V)

7 IV1 In V1 transmission pulse input

8 CH1 In Signal charge gate pulse


10 ISUB In Substrate pulse input

11 NC - Not used


13 CH2 In Signal charge gate pulse


15 GND - GND

16 VH - High level power supply (16.5V)



19 VM24 - Middle level power supply (GND)

20 VHH - High level power supply (16.5V)

Table 3-2-1 V. DRIVER (IC5501) pin functions

3-5

3.3 T. G

3.3.1 T. G (IC5502) pin functionsPin No. Label In/Out Description

1 XSG2 Out CCD signal charge gate pulse2 XV3 Out CCD vertical transfer clock3 XSG1 Out CCD signal charge gate pulse4 VSS1 - GND5 XV1 Out CCD vertical transfer clock6 XV2 Out CCD vertical transfer clock7 XSUB Out CCD signal charge sweep out pulse (for high speed shutter)8 VDD1 - Power supply9 RG Out CCD reset gate pulse10 VSS2 - GND11 VSS3 - GND12 H1 Out CCD horizontal transfer clock13 H2 Out CCD horizontal transfer clock14 VDD2 - Power supply15 VDD3 - Power supply16 XRS Out Sampling pulse17 SHP Out CDS precharge level S/H pulse18 SHD Out CDS data level S/H pulse19 VSS4 - GND20 ADCKO Out A/D converter clock21 CP2 Out A/D converter OB clamp pulse22 PBLK Out Pre block clean pulse23 OBCLP Out CDS OB clamp pulse24 CLPDM Out Dummy signal clamp pulse25 CKO Out Not used26 OSCI In Not used27 OSCO Out Not used28 VDD4 - Power supply29 CKI In Main clock (27MHz)30 TEST1 In Not used31 CLO Out Not used32 VSS5 - GND33 CKSW1 In A/D converter clock phase select34 CKSW2 In A/D converter clock phase select35 VGAT In Vertical transfer clock reduce control36 RCNT In Reset gate pulse control (L:positive /H:negative)37 RST In Reset38 SSCK In Serial data clock39 SSI In Serial data input40 SEN In Serial data strobe41 VDD5 - Power supply42 AHD In HD input43 AVD In VD input44 VSS6 - GND45 ID Out Line ID46 CAMVTR In Mode select after reset47 TEST2 In Not used48 XV4 Out CCD vertical transfer clock

Table 3-3-1 T. G (IC5502) pin functions

3-6

3.4 CDS AGCThis IC incorporates the usual correlation double sampling, AGC, A/D converter reference voltage circuit,as well as the 15-CH EVR-DAC based on serial data inputs. However the number of channels actuallyused are four channels (OB setup adjustment, gamma correction setting, optical block hall gainadjustment, and hall offset adjustment) only. The serial data is input from the SYSCON CPU IC1001based on adjustment values written on the EEPROM.

3.4.1 CDS AGC (IC5601) pin assignment

VRB

VRT

G N D

G _ M O D E _ S W

VCC3

PreApa.DL_IN

V R M H

CCDOUT_ IN

G N D

DS2

GN

D

S_D

T

S_C

LK

CD

S_C

S

H_G

AIN

H_O

FF

SE

T

VD

D_O

UT

DS

1

VC

C1

CD

S_O

UT

AG

C_R

EF

_OU

T

G_M

OD

E_S

W

TR

AP

_OU

T

AG

C_I

N

AG

C_D

ET

PB

LK_I

N

AG

C_O

UT

2

AG

C_O

UT

1

VC

C2

SETUP_ADJ

O B _ C O N T

A/D_OUT

SUBAMP_DET

SUBAMP_IN

PreApa_OUT

V R M _ O U T

G_IN

G N D

OBCLB_IN

Serial_Control15CH_DAC

15

13

14

16

17

18

19

20

21

22

23

24

252627282930313233343536

46

48

47

45

44

43

42

41

40

39

38

37

121110987654321

VrefH3.0V

VrefB1.0V

V C O

+

G A M M A DL

Knee_Cont

+

-G C

G C

DC_Cont

VrefM1.8V

VrefMH2.75V

BIAS

S/H S/H

9dB

3dB G C D CCont

P.sepaTEST

560

Fig. 3-4-1 CDS AGC (IC5601) pin assignment

3-7

3.4.2 CDS AGC (IC5601) pin functions

Pin No. Label In/Out Description1 DAC CH1 OUT Out Not used2 VDD OUT Out Power supply output (3.5V)3 VSS - GND4 DI In Serial data input5 SCLK In Serial data clock6 LOAD In Chip select7 DAC CH8 OUT Out Hole gain adjustment output8 DAC CH9 OUT Out Hole offset adjustment output9 DAC CH12 OUT Out Not used10 DAC CH10 OUT Out Not used11 DAC CH11 OUT Out Not used12 DAC CH15 OUT Out Not used13 DAC CH14 OUT Out Not used14 DAC CH13 OUT Out Not used15 DAC CH4 OUT Out Optical black set up adjustment output16 OB CONTROL In Optical black set up adjustment input17 A/D OUT Out Signal output to A/D converter18 SUB AMP DET -19 SUB AMP IN In Sub amplifier input20 PREAPA OUT Out Not used21 VREFM OUT Out Reference voltage output (1.8V)22 GAMMA IN In23 GND2 - GND24 CPOB IN In Optical black clamp pulse input25 VCC2 - Power supply26 AGC OUT1 Out AGC signal output27 AGC OUT2 Out AGC signal output28 PBLK IN In Blanking pulse input29 AGC DET -30 AGC IN In AGC input31 TRAP OUT -32 GAMMA MODE In33 AGC REF OUT Out34 CDS OUT Out CDS signal output35 VCC2 - Power supply36 DS1 IN In CDS signal level S/H pulse37 DS2 IN In CDS pre-charge level S/H pulse38 GND1 - GND39 CCDOUT IN In CCD signal input40 VREFMH OUT Out Reference voltage output (2.75V)41 GAMMA OUT Out Not used42 PREAPA DL IN In Not used43 VCC3 - Power supply44 DAC CH6 OUT Out Gamma mode select45 GND3 - GND46 DAC CH7 OUT Out Not used47 VREFH OUT Out Top reference voltage for A/D converter (3.0V)48 VREFB OUT Out Bottom reference voltage for A/D converter (1.0V)

Table 3-4-1 CDS AGC (IC5601) pin functions

3-8

3.5 ADC FUNCTION

3.5.1 ADC (IC4201) pin functions

Pin No. Label In/Out Description1 NC - Not used2 NC - Not used3 AVSS - GND (analog)4 VRTS - Not used5 VRT In Top reference voltage (3.0V)6 AVSS - GND (analog)7 AVDD - Power supply (analog)8 VRM In Middle reference9 AVDD - Power supply (analog)10 VIN In Analog signal input11 NC - Not used12 NC - Not used13 NC - Not used14 NC Not used15 AVSS - GND (analog)16 VRB In Bottom reference voltage (1.0V)17 VRBS - Not used18 AVSS - GND (analog)19 AVDD - Power supply (analog)20 AVDD - Power supply (analog)21 TEST - Not used22 D0 Out Digital signal output (LSB)23 NC - Not used24 NC - Not used25 NC - Not used26 NC - Not used27 D1 Out28 D2 Out29 D3 Out30 AVSS - GND (analog)31 DVDDL - Power supply (digital)32 D4 Out33 D5 Out34 D6 Out35 NC - Not used36 NC - Not used37 NC - Not used38 NC - Not used39 D7 Out Digital signal output40 D8 Out Digital signal output (MSB)41 NC - Not used42 AVSS - GND (analog)43 AVDD - Power supply (analog)44 CLK In Clock input 13.5MHz45 NOE In L: normal fixed46 POWD In OB clamp input H:power down mode (no output) /L:normal mode47 NC - Not used48 NC - Not used

Digital signal output

Power supply (analog)

Table 3-5-1 ADC (IC4201) pin functions

3-9

3.6 FOCUS & ZOOM DRIVERThis IC drives and controls the FOCUS and ZOOM pulse motors. It is composed of the serial data decoder,drive pulse generator, and current setting and output driver. The serial data is input from the SYSCONCPU, after which first the initial data is sent when the power is turned on, and initial settings are performed.Next, standard data such as pulse width, number of pulses, rotation direction (CW/CCW), and currentsettings are synchronized with the VD, and input sequentially to drive the motor.

3.6.1 Focus & Zoom driver (IC4851) pin assignment

V m 3

D2FBb

Cosc

L G N D

FILd

FILa

VrefV D

EXTb

B2

S D A T A

29

4

3

2

1

35

34

33

32

31

30

R E S E T

L A T C H

36

37

38

5

6

7

8

9

10

SCLK

OSCin

OSCout

Vdd

FILc

FILb

SERIALD E C O D E R

H BRIDGEa 1ch

EXP1

EXP2

FBd

FBc

D1

C1

13

12

11

14

15

16

17

18

19

EXP0

C2

V m 4

P G N D

V m 1

EXTa

EXP3

FBa

20

26

25

24

23

22

21

A1

27

28

A2

V m 2

B1

H BRIDGEb 1ch

H BRIDGEa 2ch

H BRIDGEb 2ch

PULSEG E N E R A T E R

C U R R E N T S E Ta C U R R E N T S E Tb

EVR2 EVR1 EVR1 EVR2

O S C1/N

Fig. 3-6-1 Focus & Zoom driver (IC4851) pin assignment

3-10

3.6.1 Focus & Zoom driver (IC4851) pin functions

Pin No. Label In/Out Description1 LGND - GND for logic section2 COSC - Chopping capacitor3 FILa - Focus 1ch filter capacitor4 FILb - Focus 2ch filter capacitor5 FILc - Zoom 1ch filter capacitor6 FILd - Zoom 2ch filter capacitor7 Vref In Reference voltage8 Vdd - Power supply for logic section9 Vm3 - Power supply for output section10 D2 Out Zoom 2ch output11 FBd Out Zoom 2ch feed back12 D2 Out Zoom 2ch output13 Vm4 - Power supply for output section14 C2 Out Zoom 1ch output15 FBc Out Zoom 1ch feed back16 C1 Out Zoom 1ch output17 EXP0 Out18 EXP1 Out19 EXP2 Out20 PGND - GND for power section21 EXP3 Out Monitor (not used)22 EXTa Out Logic monitor (not used)23 Vm1 - Power supply for output section24 A1 Out Focus 1ch output25 FBa Out Focus 1ch feed back26 A2 Out Focus 1ch output27 Vm2 - Power supply for output section28 B1 Out Focus 2ch output29 FBb Out Focus 2ch feed back30 B2 Out Focus 2ch output31 EXTb Out Logic monitor (not used)32 VD In Vertical drive pulse33 LATCH In Latch signal34 SDATA In Serial data input from SYSCON IC100135 SCLK In Serial clock input from SYSCON IC100136 OSCin In Master clock37 OSCout Out Master clock output38 RESET In Reset input from SYSCON IC1001

Monitor (not used)

Table 3-6-1 Focus & Zoom driver (IC4851) pin functions

3-11

3.7 YMCA & SSGThis IC is the DV camera signal processing DSP. In addition to the current YCA and EISFMC, the SSG,microprocessor IF, and shutter sound generator have been mounted on one chip.The YCA inputs video data from the color difference line sequential method CCD and carries out Y/Csignal processing and high picture quality processing. The Y/C signal processing and high picture qualityprocessing optimizes video outputs by setting data from the SYSCON. It also carries out variouscalculations using the Y/C signal, and outputs the AWB/AE data and AF data to the SYSCON. The YCAalso incorporates a screen photometry circuit and iris control PWM.The EISFMC carries out digital effects and handshake correction by movement vector detection, and fieldmemory access control.

3.7.1 YMCA & SSG (IC4301) pin assignment

179

153

167

180

114

154

141

181

168

128

182

155

169

142

183

129

156

170

184

143

157

171

185

115

116

186

172

158

144

187

173

130

159

188

174

145

131

189

175

160

190

146

176

161

191

132

177

147

46 16 61 2 32 17 47 3 33 18 4 62 48 19 5 34 63 20 6 49 35 21 7 77 78 8 22 36 50 9 23 37 64 10 51 24 38 11 65 25 12 52 39 79 13 26 40 14

GN

DR

OM

OU

T

TD

O

TM

C3

TM

Y4

TM

Y3

GN

DC

OR

E_V

DD

RA

MO

UT

ME

MC

LKM

EM

TE

ST

ME

MIN

SC

AN

OU

TS

CA

NIN

SC

AN

MO

DE

GN

D

VD

D

TD

IT

MS

JTA

GM

OD

EB

TC

KG

ND

CO

RE

_VD

DM

CLR

KR

ST

GN

D

VD

D

TM

C2

TM

C1

TM

C0

TM

Y7

TM

Y6

TM

Y5

GN

D

TM

Y0

TM

Y1

TM

Y2

GN

DV

DD

MC

LKR

AD

OW

AD

OR

AE

OW

AE

OF

MW

RF

MR

EO

FM

WE

OIE

O

5 32 76 62 85 4

6 74 1

4 26 85 55 68 08 16 97 0

9 28 2

8 38 49 39 49 59 69 1

1 0 3

1 0 71 0 8

1 0 61 0 51 2 21 2 11 2 01 0 41 3 61 1 91 3 51 3 41 5 01 1 81 4 91 6 41 3 31 4 81 1 7

1 6 31 7 8

1 6 21 9 2

G N DV D DF M Y 0F M Y 1F M Y 2

F M Y 4F M Y 3

F M Y 5F M Y 6F M Y 7F M C 0F M C 1F M C 2F M C 3G N D

A G N DC O R E _ V D D

A V D DK O U TG N D2 . 2 V D DY O U T 0Y O U T 1Y O U T 2Y O U T 3

Y O U T 4G N D

Y O U T 5Y O U T 6Y O U T 7G N D2 . 2 V D D

C O R E _ V D D

C O U T 0C O U T 1C O U T 2C O U T 3C O U T 4C O U T 5C O U T 6C O U T 7G N DV T R 4 5 MINHINVG N D2 . 2 V D DG N D

MA

D5

VD

DG

ND

MA

D4

MA

D3

MA

D2

MA

D1

MA

D0

CS

YN

C

GN

DP

BV

SP

BH

S

CV

ID3

MA

D15

MA

D14

MA

D13

MA

D12

MA

D11

VD

DG

ND

MA

D10

MA

D9

MA

D8

NR

EN

HW

EN

LWE

OS

C27

VD

DG

ND

CLK

TS

TC

RC

B

MA

D6

MA

D7

GN

DA

LE

DD

FS

K

CV

ID2

CV

ID1

CV

ID0

YV

ID7

YV

ID6

YV

ID5

YV

ID4

YV

ID3

YV

ID2

YV

ID1

YV

ID0

CO

RE

_VD

D1

3 13 01 57 6

6 04 5

2 94 47 54 35 95 87 45 7

7 38 9

7 27 18 88 78 68 59 0

1 0 2

9 89 7

9 91 0 01 0 91 1 01 0 11 1 11 2 31 2 41 1 21 1 31 3 71 3 81 2 51 5 11 2 61 5 21 3 9

1 2 71 6 5

1 6 61 4 0

V D T G RH D T G RO S C B O

V D D

L H FG N D

X O AG N D

XIBX O BV D D

C M P A

V D DG N DADI8ADI7ADI6ADI5ADI4ADI3

ADI0ADI1

V D DG N DF H 2

LHFINF L D Y C A

H D Y C A RV D Y C A R

O S C A OC L K Y C A

F L D T G

ADI2

C M P BF L D F M C

V D F M CH D F M C

G N DA F B E N D

B E N DP W MT N WO M TV D DG N D

C O R E _ V D DG N D

XIA

Y /CA U T O

m- comIF

EISF M C

Y CS E L E C T

O U T P U TS E L E C T

K A S H A

S S G

Fig. 3-7-1 YMCA & SSG (IC4301) pin assignment

3-12

3.7.2 YMCA & SSG (IC4301) pin functions-1/4

Pin No. Label In/Out Description1 VDD - Power supply 3V31 GND - GND30 ADI8 In (MSB)15 ADI7 In76 ADI6 In45 ADI5 In60 ADI4 In Signal input from A/D IC420229 ADI3 In44 ADI2 In75 ADI1 In43 ADI0 In (LSB)59 VDD - Power supply 3V58 GND - GND74 FH2 In Line distinction57 LHFIN -89 FLDYCA -73 VDYCAR Out VD output to TG72 HDYCAR Out HD output to TG71 OSCAO Out Clock 27MHz to TG88 CLKYCA -87 FLDTG -86 VDTGR -85 HDTGR -90 OSCBO -102 VDD - Power supply 3V97 GND - GND98 LHF -99 XIA -100 XOA -109 GND - GND110 XIB -101 XOB -111 VDD - Power supply 3V123 CMPA -124 CMPB -112 FLDFMC Out Field distinction to SYSCON CPU IC1001113 VDFMC Out VD to SYSCON CPU IC1001137 HDFMC Out HD to SYSCON CPU IC1001138 GND - GND125 AFBEND -151 BEND -126 PWM Out IRIS control output152 TNW Out FMC busy139 OMT Out EIS data read out timing165 VDD - Power supply 3V127 GND - GND166 CORE_VDD - Power supply 3V140 GND - GND

Not used

Not used

Not used

Not used

Not used

Not used

Table 3-7-1 YMCA & SSG (IC4301) pin functions-1/4

3-13

·YMCA & SSG (IC4301) pin functions-2/4

Pin No. Label In/Out Description179 MAD15 In/Out (MSB)153 MAD14 In/Out167 MAD13 In/Out CPU data/address 16bits MPX BUS180 MAD12 In/Out114 MAD11 In/Out154 VDD - Power supply 3V141 GND - GND181 MAD10 In/Out168 MAD9 In/Out128 MAD8 In/Out182 MAD7 In/Out CPU data/address 16bits MPX BUS155 MAD6 In/Out169 MAD5 In/Out142 VDD - Power supply 3V183 GND - GND129 MAD4 In/Out156 MAD3 In/Out170 MAD2 In/Out CPU data/address 16bits MPX BUS184 MAD1 In/Out143 MAD0 In/Out (LSB)157 GND - GND171 ALE In Address latch enable185 NRE In Read enable115 NHWE In write enable116 NLWE In write enable186 OSC27 In Clock 27MHz172 VDD - Power supply 3V158 GND - GND144 CLKTST -187 CRCB -173 CSYNC -130 CORE_VDD - Power supply 3V159 GND - GND188 PBVS In VTR PB horizontal reference signal174 PSHS In VTR PB vertical reference signal145 DDFSK In Reference clock 13.5MHz131 CVID3 In189 CVID2 In175 CVID1 In160 CVID0 In190 YVID7 In146 YVID6 In176 YVID5 In161 YVID4 In191 YVID3 In132 YVID2 In177 YVID1 In147 YVID0 In

PB chroma input from deck section

PB luminance input from deck section

Not used


3-14


Pin No. Label In/Out Description192 CORE_VDD - Power supply 3V162 GND - GND163 2.2VDD - Power supply 2.2V178 GND - GND117 INV Out Vertical reference to VTR148 INH Out Horizontal reference to VTR133 VTR45M Out Clock output to FOCUS/ZOOM IC4851164 GND - GND149 COUT7 Out118 COUT6 Out150 COUT5 Out134 COUT4 Out135 COUT3 Out119 COUT2 Out136 COUT1 Out104 COUT0 Out120 2.2VDD - Power supply 2.2V121 GND - GND122 YOUT7 Out105 YOUT6 Out106 YOUT5 Out107 YOUT4 Out108 GND - GND103 YOUT3 Out91 YOUT2 Out96 YOUT1 Out95 YOUT0 Out94 2.2VDD - Power supply 2.2V93 GND - GND84 KOUT Out Shutter sound83 AVDD - Power supply 3V92 AGND - GND82 CORE_VDD - Power supply 3V70 GND - GND69 FMC3 In81 FMC2 In80 FMC1 In56 FMC0 In55 FMY7 In68 FMY6 In42 FMY5 In67 FMY4 In41 FMY3 In54 FMY2 In28 FMY1 In66 FMY0 In27 VDD - Power supply 3V53 GND - GND

Chroma signal input from field memory

Luminance signal input from field memory

Luminance signal output to deck section

Chroma signal output to deck section

Luminance signal output to deck section


3-15


Pin No. Label In/Out Description14 IEO Out Input enable40 FMWEO Out Write enable26 FMREO Out Read enable13 FMWR -79 WAEO -39 RAEO Out Read address enable52 WADO Out Write address12 RADO Out Read address25 MCLK Out Clock output to field memory65 VDD - Power supply 3V11 GND - GND38 TMY0 Out24 TMY1 Out51 TMY2 Out10 TMY3 Out64 TMY4 Out37 GND - GND23 TMY5 Out9 TMY6 Out50 TMY7 Out36 TMC0 Out22 TMC1 Out8 TMC2 Out78 TMC3 Out77 VDD - Power supply 3V7 GND - GND21 KRST In Shutter sound reset35 MCLR In Main reset49 CORE_VDD - Power supply 3V6 GND - GND20 TCK In63 JTAGMODEB In34 TMS In5 TDI In19 TDO Out48 VDD - Power supply 3V62 GND - GND4 SCANMODE -18 SCANIN -33 SCANOUT -3 MEMIN -47 MEMTEST -17 MEMCLK -32 RAMOUT -2 ROMOUT -61 GND - GND16 CORE_VDD - Power supply 3V46 GND - GND

Not used

Luminance signal output to field mamory

Luminance signal output to field mamory

Chroma signal output to field mamory

Not used (for boundaly scan test)

Not used


3-16

3.8 FM

3.8.1 FM (IC4302) pin functions

Pin No. Label In/Out Description1 NC - Not used2 GND - GND3 D11(CIN3) In4 D10(CIN2) In5 D9(CIN1) In6 D8(CIN0) In7 D7(YIN7) In8 D6(YIN6) In9 D5(YIN5) In10 D4(YIN4) In11 D3(YIN3) In12 D2(YIN2) In13 D1(YIN1) In14 D0(YIN0) In15 SWCK In Serial write clock16 RSTW In Reset write17 WE In Write enable18 IE In Input enable19 VCC - Power supply20 NC - Not used21 VCC - Power supply22 OE In Output enable23 RE In Read enable24 RSTR In Reset read25 SRCK In Serial read clock26 Q0(YOUT0) Out27 Q1(YOUT1) Out28 Q2(YOUT2) Out29 Q3(YOUT3) Out30 Q4(YOUT4) Out31 Q5(YOUT5) Out32 Q6(YOUT6) Out33 Q7(YOUT7) Out34 Q8(COUT0) Out35 Q9(COUT1) Out36 Q10(COUT2) Out37 Q11(COUT3) Out38 GND - GND

Data iuput

Data output

Table 3-8-1 FM (IC4302) pin functions

3-17

3.9 DVIO FUNCTIONDuring recording, 4:2:2 video data (Y: 8 bits /Cr, Cb: 8bits 13.5 MHz) from the camera is converted to the4:1:1 (*4:2:0) (Y/C: 8 bits 18 MHz) and output to the shuffle memory. During playback, the 4:1:1 (*4:2:0)DVC data is converted to the 4:2:2 internal data and sent to the analog video output.In the playback digital mode, the 4:1:1 data is sent to the camera (YMCA). At this time, the color differencesignal is sent by the method which divides the data into upper 4 bits and lower 4 bits.The analog output has four DACs-Y, C, Cr, and Cb while a synchronization block has been added for the Ysignal. A color encoder and burst function are also incorporated for the C signal.

3.9.1 DVIO (IC3202) pin assignment

SignalSelector

YDAC

158159160161162163164165166167168169170171172173174175176

133134135136137138139140141142143144145146147148149150151152153154155156157

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

YD

AV

RE

FY

DA

BIA

SY

OU

TA

VD

DA

VS

SC

DA

VR

EF

CD

AB

IAS

CO

UT

AD

VD

DA

DV

SS

CR

DA

VR

EF

CR

DA

BIA

SC

RO

UT

AV

DD

AV

SS

CB

DA

VR

EF

CB

DA

BIA

SC

BO

UT

AV

DD

AV

SS

PW

DN

AD

DA

PO

FF

27P

OF

F18

PO

FF

CG

FIL

SW

27F

ILS

W18

EV

FH

DV

BLK

CG

HD

VS

SC

LK27

INC

LK27

OU

TC

LK18

INC

LK18

OU

TV

DD

3VV

DD

2VC

LKC

GIN

CLK

CG

OU

TV

SS

PC

27C

PC

27H

PC

18C

PC

CG

CLK

CG

69686766656463626160595857565554535251504948474645

76757473727170

888786858483828180797877

DSF1DSF0VDD2VVDD23VSSCLK18M1CLK450KCLK18M2CLK188MCASVDCASHDFRPSDIOSCLKSTPLCDCKVSSVDD2VRSTAPCRSTMCVSVSSXOUTXINVDD3V

VDD2VVDD32VSSPBC7PBC6PBC5PBC4PBC3PBC2PBC1PBC0PBVSPBHSDSF7DSF6DSF5DSF4DSF3DSF2

YS

I3Y

SI2

YS

I1Y

SI0

VD

D2V

VD

D32

VS

SC

SI7

CS

I6C

SI5

CS

I4C

SI3

CS

I2C

SI1

CS

I0C

AM

CLK

RE

FC

LKP

BY

7P

BY

6P

BY

5P

BY

4P

BY

3P

BY

2P

BY

1P

BY

0

TE

ST

1T

ES

T0

VD

D2V

VD

D3V

VS

SD

UM

MY

7D

UM

MY

6D

UM

MY

5D

UM

MY

4D

UM

MY

3D

UM

MY

2D

UM

MY

1D

UM

MY

0IN

VIN

HY

SI7

YS

I6Y

SI5

YS

I411

311

211

111

010

910

810

710

610

510

410

310

210

110

099 98 97 96 95 94 93 92 91 90 8913

213

113

012

912

812

712

612

512

412

312

212

112

011

911

811

711

611

511

4

YADVREFH

AVSSYADVREFMYADVREFL

AVDDAVSS

CINCADVREFH

CADVBSIAVSS

CADVREFMCADVREFL

AVDDAVSS

ADVSSADVDDADVSSADVDD

YADVBSI

TEST2

TEST4TEST5TEST6TEST7TEST8TEST9SCAN

VSSVDD3VVDD2V

INFTRST

TMSTCKTDI

TDOVSS

SHORTCUTVMASK

P W R O F FYADJ

CPSYNCYIN

TEST3

Color BarGenerator

4:2:2®4:1:1

CDAC

CrDAC

CbDAC

ClockConv.

PLL

P C

1/20F R P G E N

1/2

4:2:2¬4:1:1

Fig. 3-9-1 DVIO (IC3202) pin assignment

3-18

3.9.2 DVIO (IC3202) pin functions-1/4

Pin No. Label In/Out Description1 YDAVREF In Y-DAC reference voltage2 YDABIAS In Y-DAC bias3 YOUT Out Luminance signal output4 AVDD - Power supply5 AVSS - GND6 CDAVREF In C-DAC reference voltage7 CDABIAS In C-DAC bias8 COUT Out Color signal output9 ADVDD - Power supply10 ADVSS - GND11 CRDAVREF In Cr-DAC reference voltage12 CRDABIAS In Cr-DAC bias13 CROUT Out Chroma signal output14 AVDD - Power supply15 AVSS - GND16 CBDAVREF In Cb-DAC reference voltage17 CBDABIAS In Cb-DAC bias18 CBOUT Out Chroma signal output19 AVDD - Power supply20 AVSS - GND21 PWDNADDA In Not used H:fixed22 POFF27 - Not used23 POFF18 Out 18M VCO power off control24 POFFCG Out Not used H:fixed25 FILSW27 - Not used26 FILSW18 Out 18M VCO input serect control27 EVFHD Out H pulse for OSD28 VBLK Out Brank pulse for OSD29 CGHD - Not used30 VSS - GND31 CLK27IN In Not used32 CLK27OUT - Not used33 CLK18IN In Clock input 18MHz34 CLK18OUT Out Feed back35 VDD3V - 3V power supply36 VDD2V - 2V power supply37 CLKCGIN In Not used38 CLKCGOUT - Not used39 VSS - GND40 PC27C - Not used41 PC27H - Not used42 PC18C Out 18MHz phase comparison output43 PCCG - Not used44 CLKCG - Not used

Table 3-9-1 DVIO (IC3202) pin functions-1/4

3-19

·DVIO (IC3202) pin functions-2/4

Pin No. Label In/Out Description45 VDD3V - 3V power supply46 XIN In 27MHz X'tal OSC input47 XOUT Out 27MHz X'tal OSC output48 VSS - GND49 MCVS Out Frame reference output50 APCRST In Reset51 RST In Reset52 VDD2V - 2V power supply53 VSS - GND54 LCDCK - Not used55 STP In Serial communication enable from MSD IC56 SCLK In Serial clock from MSD IC57 SDIO In/Out Serial data from MSD IC58 FRP Out Frame pulse output59 CASHD Out H reference for CAS IC60 CASVD Out V reference for CAS IC61 CLK188M In Memory write timing 18/8=2.25MHz62 CLK18M2 Out Clock output 18MHz63 CLK450K Out Clock output 450KHz64 CLK18M1 Out Clock output 18MHz65 VSS - GND66 VDD23 - 2/3V power supply (2V or 3V)67 VDD2V - 2V power supply68 DSF0 In/Out69 DSF1 In/Out70 DSF2 In/Out71 DSF3 In/Out72 DSF4 In/Out73 DSF5 In/Out74 DSF6 In/Out75 DSF7 In/Out76 PBHS Out H reference for PB digital77 PBVS Out V reference for PB digital78 PBC0 Out79 PBC1 Out80 PBC2 Out81 PBC3 Out82 PBC4 -83 PBC5 -84 PBC6 -85 PBC7 -86 VSS - GND87 VDD32 - 2/3V power supply (2V or 3V)88 VDD2V - 2V power supply

Data bus from/to shuffle memory

Cr,Cb signal output for PB digital

Not used


3-20


Pin No. Label In/Out Description89 PBY0 Out90 PBY1 Out91 PBY2 Out92 PBY3 Out93 PBY4 Out94 PBY5 Out95 PBY6 Out96 PBY7 Out97 REFCLK Out Data transfer clock 13.5MHz98 CAMCLK - PLL reference 4.5MHz99 CSI0 In100 CSI1 In101 CSI2 In102 CSI3 In103 CSI4 In104 CSI5 In105 CSI6 In106 CSI7 In107 VSS - GND108 VDD32 - 2/3V power supply (2V or 3V)109 VDD2V - 2V power supply110 YSI0 In111 YSI1 In112 YSI2 In113 YSI3 In114 YSI4 In115 YSI5 In116 YSI6 In117 YSI7 In118 INH In H reference119 INV In V reference120 DUMMY0 -121 DUMMY1 -122 DUMMY2 -123 DUMMY3 -124 DUMMY4 -125 DUMMY5 -126 DUMMY6 -127 DUMMY7 -128 VSS - GND129 VDD3V - 3V power supply130 VDD2V - 2V power supply131 TEST0 -132 TEST1 -

Not used

Camera Cr,Cb signal input

Camera Y signal input

Not used

Y signal output for PB digital


3-21


Pin No. Label In/Out Description133 TEST2 -134 TEST3 -135 TEST4 -136 TEST5 -137 TEST6 -138 TEST7 -139 TEST8 -140 TEST9 -141 SCAN - Not used142 VSS - GND143 VDD3V - 3V power supply144 VDD2V - 2V power supply145 INF In Frame reference pulse from DV I/F146 TRST In147 TMS In148 TCK In149 TDI In150 TDO Out151 VSS - GND152 SHORTCUT -153 VMASK -154 PWROFF -155 YADJ -156 CPSYNC -157 YIN -158 YADVREF -159 YADVBSI -160 AVSS - GND161 YADVREFM -162 YADVREFL -163 AVDD - Power supply164 AVSS - GND165 CIN -166 CADVREFH -167 CADVBSI -168 AVSS - GND169 CADVREFM -170 CADVREFL -171 AVDD - Power supply172 AVSS - GND173 ADVSS - GND174 ADVDD - Power supply175 ADVSS - GND176 ADVDD - Power supply

Not used

Not used

Not used

Not used

Not used

For boundaly scan


3-22

3.9.3 PLL circuit descriptionThe reference clock of the DVC circuit 18 MHz is generated by the VCO inside the PLL IC3201. Duringplayback and camera picture recording, the switch in the PLL IC is connected to the Pin 33 input. At thistime, the 18 MHz clock is locked to the 27 MHz of the crystal oscillator X1401. During DV input recording,the switch is set to the 1394 REC side, and the 18 MHz clock is synchronized with the frame pulse of theDV input (reception) signal from the digital interface. The PC (Phase Comparator) is located inside theMSD IC1401.This 18 MHz clock is sent to the shuffle memory as CLK18M1 from Pin 62 and output from Pin 64 to theCAS, EDA, and digital IF as the CLK18M2. The frequency-divided 450 KHz is sent to the EDA PC as theCLK450K from Pin 63, to become the reference of the recording clock VCO.

V C OP C1/4

1/6

1/20

F R P G E N

S S G

Y M C A

DIF

46

33

XIN

CLK18IN

R E F

P C 1 8 C4.5MHz

X1401

27MHz

R E F

42

62/64

63

58

49145INF

76/77

118/119INV/ INH

PBVS/PBHS

63

62

95 VPLL

CLK540K

CLK18M1/M2

F R P

35

3325

18MHz

1394 REC

C A M E R A R E CPLAY

IC3201PLL

DVIO IC3202

IC1401M S D

P CM C V S

Fig. 3-9-2 PLL circuit block diagram

IC3201 mode switching settingsThe mode of the IC3201 18 MHz PLL is switched by the settings of Pins 29 and 30, while the mode of theaudio FS frequency PLL is switched by the settings of Pins 39 and 40.

H L

L H

L L

29 30

33

35 1394 REC

PB/CAMERA REC

Power Save

H L

L L

H H

40 39

46 12.3M(48K)

FSCLK 11.3M(44.1K)

8.2M(32K)

Table 3-9-2 PLL mode settings

3-23

3.10 COMPRESS/AUDIO/SHUFFLE (CAS) FUNCTIONThis IC carries out digital signal processing of the video and audio signals on conforming to the DV format.Its comes equipped with the usual LSI functions such as COMPRESS, SHUFFLING, and AUDIOPROCESS. During recording, it controls the address read/write enable of the SHUFFLE MEMORY toshuffle the video signals. After that, it carries out, on the video data, adaptive two-dimensional discretecosine transform (DCT), re-digitization, and variable length coding (VLC), and saves the data in thesynchronization block, and outputs the data to the DVC bus. At the same time, it also performs 1 framecompletion shuffling on audio signals, and outputs the data to the DVC bus after saving in thesynchronization block.During playback, it performs the reverse process of recording. It extracts video synchronization block dataand audio synchronization block data on the DVC bus, and decodes video data and audio data from theextracted data.

IC3001

D- IF C A S E D A

IC3003IC8001

SSP

DV BUS: BD0-3 ,SMP

SSP: Sector(1-t rack) Start /Stop Pulse

SMP: DV BUS Star t Mark Pulse

Fig. 3-10-1 DV-BUS connection

3.10.1 CAS IC3001 pin assignment

89 88 90 78 79 77 65 67 66 68 57 53 55 54 42 46 45 44 43 34 36 35 25 23 24

7146

1322333212215

413120114

301019329189281

81 82 80 70 69 71 61 59 60 62 58 51 49 50 47 37 39 38 40 28 26 27 15 17 16

10497

103968776

10286957564637494

101738493

100728392999198

SHM225

VSPDFD7DFD6DFD5DFD4

VSSDFD3DFD2DFD1DFD0

VDDE2VDDE2VDDI2CLK18

VSSSMADD17SMADD16SMADD15SMADD14SMADD13SMADD12SMADD11

VSS

HSP

VS

SF

RP

DIB

CK

DIM

CK

DO

BC

KD

OM

CK

DO

LRC

KD

OD

AT

VS

SX

IX

OV

DD

E3

VD

DE

3V

DD

I2A

IDA

TR

EC

MU

TV

SS

DID

AT

DIL

AC

KLK

FR

PS

CK

SD

AS

TP

CLK

24R

ST

VSSTDIT M STCKTRSTT D OP W M OFS0FS1VSSVCOIV C O OVDDE3VDDI2VSSTINT0TINT1TINT2TINT3TINT4TINT5TINT6TINT7SSPVSS

SM

AD

D10

SM

AD

D9

SM

AD

D8

SM

AD

D7

SM

AD

D6

SM

AD

D5

SM

AD

D4

VS

SS

MA

DD

3S

MA

DD

2S

MA

DD

1S

MA

DD

0V

DD

E2

VD

DI2

SM

EC

SM

RS

VS

SS

MW

ES

MW

SS

MD

IOS

SM

PB

D3

BD

2B

D1

BD

0

Shuff leAddress

CompressDCT/VLC

I-DCT/VLDDV BUS I /F

m-com I/F

ADC/DACI/F

SampleConv.

Audio

Video

Fig. 3-10-2 CAS IC3001 pin assignment

3-24

3.10.2 CAS IC3001 pin functions-1/3


104 SHM225 Out Phase reference for shuffle memory (2.25MHz)

97 HSP In Horizontal timing control for shuffle memory

103 VSP In Vertical timing control for shuffle memory

96 DFD7 In/Out

87 DFD6 In/Out

76 DFD5 In/Out

102 DFD4 In/Out

86 VSS - GND

95 DFD3 In/Out

75 DFD2 In/Out

64 DFD1 In/Out

63 DFD0 In/Out

74 VDDE2 -

94 VDDE2 -

101 VDDI2 - Internal 2V power supply

73 CLK18 In System clock input 18MHz

84 VSS - GND

93 SMADD17 In/Out

100 SMADD16 In/Out

72 SMADD15 In/Out

83 SMADD14 In/Out

92 SMADD13 In/Out

99 SMADD12 In/Out

91 SMADD11 In/Out

98 VSS - GND

81 SMADD10 In/Out

82 SMADD9 In/Out

80 SMADD8 In/Out

70 SMADD7 In/Out

69 SMADD6 In/Out

71 SMADD5 In/Out

61 SMADD4 In/Out

59 VSS - GND

Shuffle memory address output(18 bits)

REC :from shuflle memory to DCT blockPB :from IDCT block to shuffle memory(8 bits)

REC :from shuflle memory to DCT blockPB :from IDCT block to shuffle memory(8 bits)

External 2V power supply


Table 3-10-1 CAS IC3001 pin functions-1/3

3-25

·CAS IC3001 pin functions-2/3


60 SMADD3 In/Out

62 SMADD2 In/Out

58 SMADD1 In/Out

51 SMADD0 In/Out

49 VDDE2 - External 2V power supply


47 SMCE Out Shuffle memory chip enable

37 SMRS Out Shuffle memory read strobe

39 VSS - GND

38 SMWE Out Shuffle memory write enable

40 SMWS Out Shuffle memory write strobe

28 SMDIOS Out Shuffle memory I/O control

26 SMP In/Out DVC start mark pulse

27 BD3 In/Out

15 BD2 In/Out

17 BD1 In/Out

16 BD0 In/Out

1 VSS - GND

8 SSP Out DVC bus sector start pulse

2 TINT7 In

9 TINT6 In

18 TINT5 In

29 TINT4 In

3 TINT3 In

19 TINT2 In

10 TINT1 In

30 TINT0 In

4 VSS - GND


20 VDDE3 - External 3V power supply

31 VCOO Out Clock for PB auodio

41 VCOI In

Mode selectNot used :normal settings "00000000"


DVC bus data (4 bits)


3-26

·CAS IC3001 pin functions-3/3


5 VSS - GND

21 FS1 Out

12 FS0 Out

32 PWMO Out Voltage control for audio PLL

33 TDO Out

22 TRST In

13 TCK In

6 TMS In

14 TDI In

7 VSS - GND

24 RST In Reset

23 CLK24 In/Out Clock output 24.576MHz

25 STP In/Out Serial communication start/stop control from/to MSD CPU

35 SDA In/Out Serial data from/to MSD CPU

36 SCK In Serial clock from MSD CPU

34 LKFRP In Frame pulse for audio

43 DILRCK In Not used

44 DIDAT In Not used

45 VSS - GND

46 RECMUT In Not used

42 AIDAT In Data input from audio A/D converter


55 VDDE3 -

53 VDDE3 -

57 XO Out

68 XI In

66 VSS - GND

67 DODAT Out Serial data output to audio D/A converter

65 DOLRCK Out L/R clock output to audio A/D,D/A converter

77 DOMCK Out Master clock output to audio A/D,D/A converter

79 DOBCK Out Bit clock output to audio A/D,D/A converter

78 DIMCK In Not used

90 DIBCK In Not used

88 FRP In Frame pulse

89 VSS - GND

Clock for audio and digital I/F(24.576MHz)

Audio PLL mode select"00":44.1kHz /"01":off /"10":48kHz /"11":32kHz

For boundaly scan

External 3V power supply


3-27

3.11 ECC/DCI/ATF (EDA) FUNCTIONThis IC carries out error correction coding (ECC), 24-25 modulation/demodulation (DCI), tracking errordetection (ATF), head switch signal generation, VITERBI decoding, and clock phase correction.During recording, the AUDIO and VIDEO data from the DV bus and the AUX and SUBCODE data from themicroprocessor (MSD) are received, error correction coding and 24-25 modulation are performedaccording to the DV format to generate recording signals, which are the output to the REC amplifier.During playback, the playback signal from the PB equalizer is VITERBI decoded, sync block extraction,and corrected by error correction decoding. The AUDIO and VIDEO data are output to the DV bus and theAUX and SUBCODE data to the microprocessor (MSD). In VITERBI decoding, the clock phase for theVITERBI A/D converter is detected, and phase compensation control the PBEQ IC is carried out. At thesame time, the ATF pilot signal components are detected from the playback signal prefiltered in the PBEQ,and the tracking error information is sent to the microprocessor (MSD).

3.11.1 EDA IC3003 pin assignment

140141142143144145146147148149150151152153154155156

125126127128129130131132133134135136137138139

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

VS

SI

CLK

450

CLK

18V

DD

I2V

SS

OV

DD

O3R

LCA

SU

CA

SO

E A8

A7

A6

A5

A4

A3

A2

A1

A0

RA

SW

EV

SS

OV

DD

O3R

VS

SI

VD

DI

DQ

15D

Q14

DQ

13D

Q12

DQ

11D

Q10

DQ

9D

Q8

DQ

7D

Q6

DQ

5D

Q4

DQ

3D

Q2

DQ

1D

Q0

VD

DO

3RV

SS

OA

GN

DA

GN

D

6968676665646362616059585756555453525150494847

76757473727170

7877

V S S OA D D A T 6A D D A T 5A D D A T 4A D D A T 3A D D A T 2A D D A T 1A D D A T 0V D D O 3VSSIH S EV D D O 2V D D O 3R E C C L KVSSIV S S OP B C L KP B D A TV D D I 3D V C C 3A V C C 3ATFIV T O P

N CV I T O NT R I C KM E M PR E F C L KC K P H A S EV C O C T LA D S T BV D D O 3

AD

DT

2A

DD

T1

AD

DT

0V

DD

O2M

VD

DI

VS

SI

VS

SO

VD

DO

3T

SR

SP

AN

CF

EH

ID1

HID

2H

ID3

RE

CI

PB

HR

EC

CT

RL

VD

DO

3N

CN

CN

CN

CV

SS

IV

SS

I

RD

BLW

VS

SO

VD

DO

2MD

T15

AD

DT

14A

DD

T13

AD

DT

12A

DD

T11

AD

DT

10A

DD

T9

AD

DT

8V

SS

OV

DD

O2M

AD

DT

7A

DD

T6

AD

DT

5A

DD

T4

AD

DT

310

510

410

310

210

110

099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 8112

412

312

212

112

011

911

811

711

611

511

411

311

211

111

010

910

810

710

6

V D D I

T R S TT M S

TDIT C KT D O

V D D I 3S S P

V S S OV D D O 2 B

B D 0B D 1B D 2B D 3S M P

V D D I 2 B

VSSI

A L EV D D I 2 M

VSSIV D D I 3

VSSIR S T

C Y L F GC Y L P G

VSSIVSSIVSSIVSSIVSSIVSSI

N C

45 46D

GN

DV

BT

MV

SS

IV

SS

I80 79

ECC/DCI

HIDCTL

Viterbi

MSD I /F

S R A MA U X

S R A MS U B C O D E

A/D

A F T D E T

C K C T L

P C

SPCTL

Fig. 3-11-1 EDA IC3003 pin assignment

3-28

3.11.2 EDA (IC3003) pin functions-1/4

Pin No. Label In/Out Description1 VSSI - Vss for input buffer and inside logic section2 CLK450 In Reference for REC 24MHz VCO3 CLK18 In System clock input 18MHz4 VDDI2 - 2V Vdd for input buffer and inside logic section5 VSSO - Vss for output buffer section6 VDDO3R - 3V Vdd for buffer of D-RAM I/F7 LCAS Out Lower column address strobe8 UCAS Out Upper column address strobe9 OE Out Output enable10 A8 Out11 A7 Out12 A6 Out13 A5 Out14 A4 Out15 A3 Out16 A2 Out17 A1 Out18 A0 Out19 RAS Out Row address strobe20 WE Out Write enable21 VSSO - Vss for output buffer section22 VDDO3R - 3V Vdd for buffer of D-RAM I/F23 VSSI - Vss for input buffer and inside logic section24 VDDI - 2V Vdd for input buffer and inside logic section25 DQ15 In/Out26 DQ14 In/Out27 DQ13 In/Out28 DQ12 In/Out29 DQ11 In/Out30 DQ10 In/Out31 DQ9 In/Out32 DQ8 In/Out33 DQ7 In/Out34 DQ6 In/Out35 DQ5 In/Out36 DQ4 In/Out37 DQ3 In/Out38 DQ2 In/Out39 DQ1 In/Out

Address for ECC memory

Data from/to ECC memory(16 bits)

Table 3-11-1 EDA (IC3003) pin functions-1/4

3-29


Pin No. Label In/Out Description40 DQ0 In/Out Data from/to ECC memory (16 bits)41 VDDO3R - 3V Vdd for buffer of D-RAM I/F42 VSSO - Vss for output buffer section43 AGND -44 AGND -45 DGND - GND for digital section of A/D46 VBTM - A/D reference voltage (top)47 VTOP - A/D reference voltage (bottom)48 ATFI In A/D analog signal input49 AVCC3 - 3V Vcc for analog section of A/D50 DVCC3 - 3V Vcc for digital section of A/D51 VDDI3 - 3V Vdd for input buffer section52 PBDAT In PB data53 PBCLK In PB clock54 VSSO - Vss for output buffer section55 VSSI - Vss for input buffer and inside logic section56 RECCLK In Rec clock57 VDDO3 - 3V Vdd for output buffer section58 VDDO2 - 2V Vdd for output buffer section59 HSE Out Recording signal60 VSSI - Vss for input buffer and inside logic section61 VDDI3 - 3V Vdd for input buffer section62 ADDAT0 In63 ADDAT1 In64 ADDAT2 In65 ADDAT3 In66 ADDAT4 In67 ADDAT5 In68 ADDAT6 In69 VSSO - Vss for output buffer section70 VDDO3 - 3V Vdd for output buffer section71 ADSTB Out Viterbi-A/D power down72 VCOCTL Out Rec clock VCO control output73 CKPHASE Out Viterbi clock phase correction PWM output74 REFCLK Out Auto EQ adjustment reference clock75 MEMP Out76 TRICK Out77 VITON Out78 N.C. - Not used

GND for analog section of A/D

PB data from Viterbi-A/D

Mode settings for PB EQ IC


3-30


Pin No. Label In/Out Description79 VSSI -80 VSSI -81 VSSI -82 VSSI -83 N.C. -84 N.C. -85 N.C. -86 N.C. -87 VDDO3 - 3V Vdd for output buffer section88 RECCTRL Out Recording on control89 PBH Out90 RECI Out91 HID3 Out Head switch pulse 392 HID2 Out Head switch pulse 293 HID1 Out Head switch pulse 194 FE Out Flying erase timing pulse95 N.C. - Not used96 SPA Out ATF sampling pulse97 TSR Out HID reference (Drum 150Hz)98 VDDO3 - 3V Vdd for output buffer section99 VSSO - Vss for output buffer section100 VSSI - Vss for input buffer and inside logic section101 VDDI - 2V Vdd for input buffer and inside logic section102 VDDO2M - 2V Vdd for output buffer of Micom I/F103 ADDT0 In/Out104 ADDT1 In/Out105 ADDT2 In/Out106 ADDT3 In/Out107 ADDT4 In/Out108 ADDT5 In/Out109 ADDT6 In/Out110 ADDT7 In/Out111 VDDO2M - 2V Vdd for output buffer of Micom I/F112 VSSO - Vss for output buffer section113 ADDT8 In/Out114 ADDT9 In/Out115 ADDT10 In/Out116 ADDT11 In/Out117 ADDT12 In/Out

Address (15 bits) /data (16 bits)

Not used

Mode settings for PB EQ IC

Vss for input buffer and inside logic section



3-31


Pin No. Label In/Out Description118 ADDT13 In/Out119 ADDT14 In/Out120 DT15 In/Out Data (16 bits)121 VDDO2M - 2V Vdd for output buffer of Micom I/F122 VSSO - Vss for output buffer section123 BLW In Write strobe124 RD In Read strobe125 ALE In Address lutch enable126 VDDI2M - 2V Vdd for input buffer of Micom I/F127 VSSI - Vss for input buffer and inside logic section128 VDDI3 - 3V Vdd for input buffer section129 VSSI - Vss for input buffer and inside logic section130 RST In Reset131 CYLFG In Drum FG132 CYLPG In Drum PG133 VSSI -134 VSSI -135 VSSI -136 VSSI -137 VSSI -138 VSSI -139 N.C. - Not used140 VDDI - 2V Vdd for input buffer and inside logic section141 VSSI - Vss for input buffer and inside logic section142 TRST In143 TMS In144 TDI In145 TCK In146 TDO Out147 VDDI3 - 3V Vdd for input buffer section148 SSP In Sector start pulse149 VSSO - Vss for output buffer section150 VDDO2B - 2V Vdd for output buffer of DV-BUS I/F151 BD0 In/Out152 BD1 In/Out153 BD2 In/Out154 BD3 In/Out155 SMP In/Out Start mark pulse156 VDDI2B - 2V Vdd for input buffer of DV-BUS I/F


DV-BUS data

For boundaly scan

Vss for input buffer and inside logic section


3-32

3.12 PB EQ FUNCTIONThe PB equalizer equalizes the waveform of the playback signal to prevent coding errors by interferencebetween coding processes when the high-density digital signal is magnetically recorded and played back.In the PLL circuit, the playback clock that is phase controlled for correctly identifying the playback data isgenerated. This IC also has an ATF signal extraction BPF and recording clock 41.85 MHz VCO forrecording.

3.12.1 PB EQ (IC3501) pin assignment

LOGICV ITON

ATFIN

G N D

V C C 1

A T F C

ATFGAIN

ATF IOUT

R E F D E T

R E F C L K

TRICKH

TRICKL

B E T A

A L F A

M O N 1

EQ

HLD

PB

H

AG

CIN

GN

D7

DLA

DJ

TF

ILO

UT

1+D

IN

VC

C7

1+D

OU

T

PLL

IN

ER

RD

L

1+D

OU

T

GN

D6

ER

R2

ER

R1

VC

C6

PR

EE

Q

TF

ILIN

MO

N2

DE

T1

DE

T2

DE

T3

DE

T4

GN

D2

VO

CC

TL

VC

C2

AM

PO

UT

VC

C8

VC

OIN

GN

D3

RE

CC

LK

VC

C3

S D E T 2

G N D 5

S D E T 1

V C C 5

P C O U T

A M P I N

A M P O U T

V C O I N

P H A S E A D J

M O N 3

C K P H A S E

V C C 4

A D C L K

P B C L K

G N D 4

P B D A T

DELAYCONT 1+D

AMP

AMP

AMP

GCA

LPF

DATADET

PC

REFF

PRE-EQ

BUFF AMP

LATCH

VCO OUTPUT

OUTPUT

OUTPUT

OUTPUT

VCO

PS

A-EQ

ERROR DET

TFIL

BPF

BPOUT

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

AMPIN

Fig. 3-12-1 PB EQ (IC3501) pin assignment

3-33

3.12.2 PB EQ (IC3501) pin functions-1/2


1 VIT_ON In Bit by Bit/VITERBI select

2 ATF_IN In ATF BPF input

3 GND1 - GND1

4 BP_OUT Out ATF BPF output

5 AMP_IN In ATF AMP input

6 VCC1 - VCC1

7 ATFC - ATF AMP output

8 ATF_GAIN In ATF gain control adjustment

9 ATFI_OUT Out ATF output

10 REFDET - Reference frequency control voltage detection

11 REFCLK In Reference clock for ATF BRF (450KHz)

12 TRICK_H In Inverter input

13 TRICK_L Out Inverter output

14 BETA In Pre-EQ phase characteristic adjustment (b)

15 ALFA In Pre-EQ characteristic adjustment (a)

16 MON1 - Pre-EQ delay monitor (not used)

17 PRE_EQ Out Pre-EQ output

18 TFIL_IN In TFIL input

19 MON2 - Not used

20 DET1 - Auto-EQ detection 1




24 GND2 - GND2

25 VCOCTL In Phase error input

26 VCC2 - VCC2

27 AMP_OUT Out Phase error amp output

28 VCC8 - VCC8

29 VCO_IN In Rec clock VCO input

30 GND3 - GND3

31 RECCLK Out Rec clock VCO output

32 VCC3 - VCC3

Table 3-12-1 PB EQ (IC3501) pin functions-1/2

3-34

·PB EQ (IC3501) pin functions-2/2


33 PB_DAT Out PB data output

34 GND4 - GND4

35 PB_CLK Out PB clock output

36 AD_CLK Out VITERBI A/D converter clock output

37 VCC4 - VCC4

38 CK_PHASE In Clock phase adjustment input from VITERBI

39 MON3 - Not used

40 PHASEADJ In Clock phase adjustment input from EVR

41 VCO_IN In PB VCO input

42 AMP_OUT Out Phase error amp output

43 AMP_IN In Phase error amp input

44 PC_OUT Out PLL phase error output

45 VCC5 - VCC5

46 SDET1 In Slice level adjustment

47 GND5 - GND5

48 SDET2 - Slice level detection

49 VCC6 - VCC6

50 ERR1 - For error signal detection

51 ERR2 - For error signal detection

52 GND6 - GND6

53 1+D_OUT Out PB 1+D signal output to Viterbi A/D

54 ERRDL In Error timing adjustment

55 PLL_IN In PB data 3-state detect, PLL input

56 1+D_OUT Out 1+D output to 3-state detect, PLL

57 VCC7 - VCC7

58 1+D_IN In 1+D input

59 TFIL_OUT Out TFIL output

60 DLADJ In Delay adjustment

61 GND7 - GND7

62 AGC_IN In Pre-EQ input

63 PB_H In PB/REC select (PB:H)

64 EQHLD In EQ hold select

Table 3-12-1 PB EQ (IC3501) pin functions-2/2

3-35

3.12.3 PB EQ circuitThe playback enveropes input from the PREAMP is subjected to optimum waveform equalization suitablefor decoding at the PRE-EQ and AUTO-EQ. After that it is added with 1+D characteristics, and output tothe VITERBI A/D converter as 1+DOUT. The 1+DOUT signal is an analog waveform with tertiary value (1,0, -1). It is converted to 7-bits digital signal by the A/D converter, and sent to the VITERBI circuit. Thedigitized tertiary information is corrected by the VITERBI detection method and converted into the binary(0, 1) playback data.The 1+DOUT signal is re-input into the IC3501, and output as the PB DATA after tertiary detection andbinary conversion by the fixed threshold value method in the DATA DET circuit, to become the playbackdata when the VITERBI is OFF. However in this unit, as VITERBI is always ON for both SP and LP, thisapplies only when VITERBI is forcibly turned OFF using the service support software.The playback clock is constantly phase-compared with the playback data in the PLL circuit, and outputsynchronized with the playback data. One is output to the A/D converter as the AD CLK, and the other issent to the EDA as the PB CLK. As the sampling point is also changed during A/D conversion by this ADCLK, there is a need for sampling to be carried out at the correct position for the VITERBI detection circuitto operate correctly. Therefore the phase correction information from the VITERBI circuit is output as theCK PHASE, and the PS (phase shift) of the PLL circuit carries out fine adjustments of the phase.The adjustment values are input from the EVR IC3503 based on the data written in the EEPROM. In theadjustments, the service support software adjusts the values to the standard values by VCO Centeradjustment first, after which the error rates are sequentially adjusted to the minimum values according tothe order in which the other adjustment points were specified in the PB EQ adjustment.

PRE-EQ LPF TFIL

From: PREAMPAGC IN

A-EQ ERR DET

1+DA/D

CONV.VITERBI

DATADET

BUFFER

P C

LATCH

V C O

LPF

P S

PLL Phase ADJ

VCO Vol tageADJ

PB DATA

PB CLK

AD CLK

To:ECC/DCI

ADDAT 0 :67bits1+D OUT

a ADJ b ADJ

Delay ADJ

Error TimingADJ

Sl ice LevelADJ

CK PHASE

Q 3 5 0 1 , 3 5 0 3

PB EQ IC3501

IC3005

EDA IC3003

Fig. 3-12-2 PB EQ block diagram

3-36

3.13 PRE/REC FUNCTIONThis IC is a head amplifier for 3 channels, however only 2 channels are used in this unit. During recording,it inputs the recording signal HSE from the EDA IC3003 into Pin 7. At the same time, it also inputs therecording current adjustment value from the EVR into Pin 8.During playback, the playback signal is sent to the PB EQ IC3501 from the Pin 64 AGCOUT. The outputfrom Pin 57 is for ATF. The ATF signal is extracted by the BPF in the PB EQ IC3501. From Pin 59, theENV_OUT is sent to the JIG connector.

3.13.1 PRE/REC (IC3502) pin assignment

S T A B

P B E N

M M C

E N V D E T

E N V O U T

TRICKH

A T F O U T

E N V C T L

H A O U T

V C C 3 V

P B O U T

AGCIN

G N D

A G C O U T

RC

TL

HID

3

HID

2

HID

1

PB

H

RE

CR

HA

2DE

T

HA

2FB

HA

2AC

FB

PB

SW

2

HA

2IN

VC

C3V

MO

N2I

N

GN

D

VC

C3V

RE

CR

1

RE

CR

2

GN

D

HS

E

EV

R

HA

3DE

T

HA

3FB

HA

3AC

FB

PB

SW

3

HA

3IN

VC

C3V

MO

N3I

N

GN

D

PBH2

R A 2 O U T

V C C 5 V

R A 1 O U T

PBH1

G N D

MON1IN

V C C 3 V

HA1IN

P B S W 1

HA1ACFB

HA1FB

H A 1 D E T

V C C 5 V

R A 3 O U T

PBH3

HA2

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

INSRH

E Q H L D

AG

CD

ET

AG

CC

TL

RC

UR

RE

CI

HA1

RA2LOGIC

MONITOR

RA1

H S W

RA3

HA3G C A

3rdAMP LPF

AGCAMP

AGCDET

VREF

E N VD E T

Fig. 3-13-1 PRE/REC (IC3502) pin assignment

3-37

3.13.2 PRE/REC (IC3502) pin functions-1/2


1 AGCCTL - AGC CTL

2 AGCDET - AGC DET-C

3 VCC3V - Main Vcc 3V

4 RECR1 - Resistor for Rec GCA

5 RECR2 - Resistor for Rec GCA

6 GND - GND

7 HSE In Rec IN

8 EVR In Rec GCA adjustment

9 HA3DET Out

10 HA3FB In

11 HA3ACFB In

12 PBSW3 In

13 HA3IN In


15 MON3IN In Not used

16 GND - GND

17 PBH3 Out

18 RA3OUT Out

19 VCC5V - Rec Vcc 5V

20 HA1DET Out CH1 head amp detection

21 HA1FB In CH1 head amp feed back

22 HA1ACFB In CH1 head amp AC feed back

23 PBSW1 In CH1 PB-ON switch

24 HA1IN In CH1 head amp in


26 MON1IN In CH1 REC monitor in

27 GND - GND

28 PBH1 Out PB-H1 switch control

29 RA1OUT Out CH1 REC amp out

30 VCC5V - Rec Vcc 5V

31 RA2OUT Out CH2 REC amp out

32 PBH2 Out PB-H2 switch control

Not used

Not used

Table 3-13-1 PRE/REC (IC3502) pin functions-1/2

3-38

·PRE/REC (IC3502) pin functions-2/2


33 GND - GND

34 MON2IN In CH2 REC monitor in


36 HA2IN In CH2 head amp in

37 PBSW2 In CH2 PB-ON switch

38 HA2ACFB In CH2 head amp AC feed back

39 HA2FB In CH2 head amp feed back

40 HA2DET Out CH2 head amp detection

41 RECR In Resistor for REC monitor

42 RCUR Out REC monitor out

43 RECI In REC insert switch

44 PBH In PB:H control

45 HID1 In Head switch 1



48 RCTL In Rec ON/OFF control ON:H

49 STAB In Stand by

50 PBEN - Not used

51 MMC - Capacitor for mono-mulch

52 INSRH Out Insert :H output

53 EQHLD Out Not used

54 ENVDET Out

55 ENVOUT Out

56 TRICKH In

57 ATFOUT Out ATF signal output

58 ENVCTL In Not used

59 HAOUT Out PB envelope output


61 PBOUT Out PB signal out

62 AGCIN In AGC in

63 GND - GND

64 AGCOUT Out AGC output to PB-EQ

Not used

Table 3-13-1 PRE/REC (IC3502) pin functions-2/2

3-39

3.14 DIGITAL INTERFACE FUNCTIONThe digital interface of this unit corresponds to the input/output of the DV terminal (IEEE 1394). The digitalinterface IC8001 is mounted on one chip with the usual LINK IC and PHY IC. The structure is the same asthe previous model, however with the use of the second generation DVC signal processing LSIincorporated from this unit, it eliminates the need for matching the DV BUS data using the gate array asdone in the previous model, and the DVS BUS data can be input/output to and from the digital IF ICdirectly. The MSD IC serves as the host microprocessor.

3.14.1 Digital IF (IC8001) pin assignment

68707172787980818288899091

101102103114115116

2019353433324948474645626160595869

127

136

104

117

128

137

92 105

118

129

138

93 106

119

130

139

131

140

120

107

94 141

132

121

108

95 142

133

122

109

143

134

123

144

135

124

LD3

LD2

LD1

LD0

LCT

L1LC

TL0

LSY

SC

LKV

CC

GN

DD

GN

DD

VC

CP

C0

PC

1P

C2

LRE

QC

TL0

CT

L1 D0

D1

SY

SC

LKD

VC

CD

GN

DA

GN

DA

GN

DT

PB

IAS

AG

ND

AG

ND

AV

CC

AV

CC

CP

SR

1R

0T

PB

-T

PB

+T

PA

-T

PA

+6 465666773747577768786858483

10099989796

113112111110126125

43445455565763

12303142

NTZIHZN T O U TG N DN T C L KR A N E ZL C N AL P W R D NV C CG N DD V S SC / L K O NL P SC N AT E S T M 1T E S T M 2/RESET/ISOA V C CP W R D NPLLFLTP L L V D DP L L G N DP L L G N DXIX O

A D 1 0A D 1 1G N DA D 1 2A D 1 3A D 1 4A D 1 5VCCA(2/3)V C C/INTPCYCLEIN

BD

3B

D2

BD

1B

D0

VC

CB

(2/3

)V

CC

BC

LK/D

CA

LEN

C/L

CN

TD

GN

DA

D0

AD

1A

D2

AD

3G

ND

AD

4A

D5

AD

6A

D7

VC

CA

(2/3

)A

D8

AD

9

SS

PV

CC

CLK

18V

CC

B(2

/3)

NC

NC

NC

NC

NC

GN

DS

MP

37 24 13 4 51 38 25 5 14 6 15 26 39 52 7 16 27 40 53 8 17 28 41 9 1821 10 1 22 11 2 36 23 12 3 50

F R P

TEST0G N D

TEST1SI /TEST2

S OS C KV C C/SENT M ST C K

/TRSTG N D

TDIT D O

/LISOL L R E Q

V C C

V F R P

G N DN CN CN CN C

V C CN CN CN CN C

G N DN CN CN CN C

V C C/RST

m-c o m I/F

VC

CB

(2/3

)

D V CBUS I /F

LINK PHY

LINK Control(CFR)A R F

ATF

ISOControl /Buffer

Fig. 3-14-1 Digital IF (IC8001) pin assignment

3-40

3.14.2 Digital IF (IC8001) pin functions-1/4

Pin No. Label In/Out Description20 GND - GND19 N.C. -35 N.C. -34 N.C. -33 N.C. -32 VCC - Power supply49 N.C. -48 N.C. -47 N.C. -46 N.C. -45 GND - GND62 N.C. -61 N.C. -60 N.C. -59 N.C. -58 VCC - Power supply69 /RST In Reset input68 FRP In Frame pulse input70 VFRP Out Frame pulse output (when DV input)71 TEST0 In Not used72 GND - GND78 TEST1 In79 TEST2/SI In80 SO Out81 SCK In82 VCC - Power supply88 /SEN In Not used89 TMS In90 TCK In91 /TRST In101 GND - GND102 TDI In103 TDO Out114 /LISO In H:fixed115 LLREQ Out Request signal output to PHY116 VCC - Power supply

For boundaly scan

Not used

Not used

Not used

Not used

For boundaly scan

Table 3-14-1 Digital IF (IC8001) pin functions-1/4

3-41

·Digital IF (IC8001) pin functions-2/4

Pin No. Label In/Out Description127 LD3 In/Out136 LD2 In/Out104 LD1 In/Out117 LD0 In/Out128 LCTL1 In/Out137 LCTL0 In/Out92 LSYSCLK In System clock input from PHY (49.152MHz)105 VCC - Power supply118 GND - GND129 DGND - GND138 DVCC - Power supply93 PC0 In Not used106 PC1 In119 PC2 In130 LREQ In Request signal input from LINK139 CTL0 In/Out131 CTL1 In/Out140 D0 In/Out120 D1 In/Out107 SYSCLK Out System clock output to LINK (49.152MHz)94 DVCC - Power supply141 DGND - GND132 AGND -121 AGND -108 TPBIAS Out Bias supply for DV terminal95 AGND -142 AGND -133 AVCC -122 AVCC -109 CPS In Not used143 R1 -134 R0 -123 TPB- In/Out144 TPB+ In/Out135 TPA- In/Out124 TPA+ In/Out

Not used

DV terminal (twisted pair cable)

Data in/out betweem LINK and PHY

Not used

GND

GND

Power supply

For bias voltage

Control signal in/out between LINK and PHY

Control signal in/out between LINK and PHY

Data in/out betweem LINK and PHY


3-42


Pin No. Label In/Out Description125 XO - Clock (24.576MHz)126 XI - Not used110 PLLGND -111 PLLGND -112 PLLVDD - Power supply113 PLLFLT In For PLL filter96 PWRDN In PHY power down mode97 AVCC - Power supply98 /ISO In Not used99 /RESET In PHY reset100 TESTM2 In83 TESTM1 In84 CNA Out 1394 connection detect (connected :L)85 LPS In Not used86 C/LKON In/Out Not used87 DVSS - GND76 GND - GND77 VCC - Power supply75 LPWRDN Out Power down mode output to PHY74 LCNA In 1394 connection detect input from PHY (connected :L)73 RANEZ In67 NTCLK In66 GND - GND65 NTOUT Out Not used64 NTZIHZ In63 CYCLEIN In57 /INTP Out DIF interrupt to MSD IC56 VCC - Power supply55 VCCA(2/3) - Power supply54 AD15 In/Out44 AD14 In/Out43 AD13 In/Out42 AD12 In/Out31 GND - GND30 AD11 In/Out12 AD10 In/Out

Not used

Data/address from/to Host (MSD IC)

GND

Not used

Not used



3-43


Pin No. Label In/Out Description18 AD9 In/Out9 AD8 In/Out41 VCCA(2/3) - Power supply28 AD7 In/Out17 AD6 In/Out8 AD5 In/Out53 AD4 In/Out40 GND - GND27 AD3 In/Out16 AD2 In/Out7 AD1 In/Out52 AD0 In/Out39 GND - GND26 /LCNTD In Not used15 N.C. - Not used6 ALE In Address lutch enable14 /DC Out Access completion signal to Host (MSD IC)5 BCLK In System clock from MSD IC25 VCCB(2/3) - Power supply38 VCC - Power supply51 VCCB(2/3) - Power supply4 BD0 In/Out13 BD1 In/Out24 BD2 In/Out37 BD3 In/Out50 SMP In/Out DV-BUS start mark pulse3 GND - GND12 N.C. -23 N.C. -36 N.C. -2 N.C. -11 N.C. -22 VCCB(2/3) - Power supply1 CLK18 In System clock input 18MHz10 VCC - Power supply21 SSP In DV-BUS sector start pulse

Not used



DV-BUS data



3-44

3.15 MONITOR FUNCTION

E²PROMEVR

IC7201IC7403

V C O V C O

RGB OUT to VF&MONI

B-Y INR-Y IN

Y IN

R

CLK

EA0

ECL

VF:H /MONI:L

D7401,L7401

VF ON:L MONI ON:L

RP

D

CK

I

SUBT G

IC7203

SY

NC

Y IN

MONI

VF

D ODI

G B

RPD

BLK

LIM

ADJ

IC741111.06MHZ

(*10.97MHz)

IC7410 D7201,L720116.52MHZ

(*16.41MHz)

PLL ADJ

CS

Fig. 3-15-1 LCD driver block diagram

The LCD DRIVER IC7201 is a one chip IC mounting the RGB recorder, driver functions, and the timinggenerator for panel driving. The video signal inputs that can be used include the composite input, Y/Cinput, and Y/color difference input. In this unit, the Y/color difference input is used. The input method isselected by the Pin 8 MODE2. NTSC/PAL is switched by the Pin 7 MODE1.

H N T S CM D-PALL SPAL

H Composi te inputM Y/Chroma inputL Y/C input

M O D E 1 M O D E 2

IC7201 drives both the VF and monitor, but the monitor drive pulse is converted to the drive pulse for thehigh picture quality LCD panel adopted in this unit by the sub timing generator IC7203.To obtain accurate timings, a phase comparator and frequency counter are incorporated. By connectingan external VCO, PLL operations can be performed. The VCO center frequency differs between the VFand monitor and so the two VCOs are used alternately (for VF: variable cap D7401, L7401, and IC7411/for MONITOR: variable cap D7201, L7201, and IC7410).The internal timing generator is switched for VF or monitor by selecting the Pin 19 SLCK input. During theL/R reversal of the monitor, the HST1, HCK1, and HCK2 timings and internal sampling hold pulse timingsare switched by the selection of the Pin 34 RGT.

L M O N I T O RH VF

N T S C 11.06MHzPAL 10.97MHz

SLCK: Dr iv ing LCD select VF: VCO center f requency MONITOR: VCO center f requencyN T S C 16.52MHzPAL 16.41MHz

H Normal scanningL

RGT: Horizontal scanning direct ion

Reverse scanning

3-45

The 3-state detection circuit (IC7401/IC7402) converts the H/M/L tertiary information sent from theSYSCON CPU into two H/L binary information.

VF : LMONI : LM O N I + B L : H

VF : HM O N I : LMONI+BL : L

VF ON : L

IC7406

IC7401

L : V F O NM : MONIH : MONI+BL

U P / D O W N + L / R : HU P / D O W N : LN O M A L : L

UP /DOWN + L /R : LU P / D O W N : LN O M A L : H

IC7402

L : UP/DOWN + L /R ® PLAY ModeM : UP/DOWN ® E-E Mode (Mi r ror Mode)H : NOMAL

L/RContro l

U P / D O W NContro l

BackL igh t ON/OFFContro l

VF ON/OFFContro l

Fig. 3-15-2 3-state detection circuit

The RGB signal output is reversed every 1H as shown in the following diagram by the internal POL SW. Itis then feed back so that the center voltage of the output signal matches the reference voltage Vcc2 /2.The white level output is clipped at the Vsig center voltage level, while the black level output is adjusted bythe Pin 46 BLKLIM, and clipped at the limiter operating point.

Video IN

F R P

R G B O U T

Black Level Limit

Black Level Limit

Vsig Center Vol tage

Fig. 3-15-3 RGB output waveform

The adjustment values are output from IC7403. IC7403 is an IC which is incorporated with both theEEPROM and EVR. The EEPROM is memorized with both the VF adjustment data and monitoradjustment data. The adjustment data is selected by Pin 21 EA0 (VF: H/ MONI: L). The Pin 16 ECL isinput with one pulse each time the VF and monitor are switched. And each time, the adjustment value ofthe VF or monitor is output according to this pulse.

3-46

3.15.1 LCD driver (IC7201) pin assignment

B-YIN

R-YIN

C O U T

X V X O

R _ B R T

B _ B R T

R G B G A I N

G A M M A 2

G A M M A 1

B R I G H T

C O N T

C_IN

R _ G A I N

B_GAIN

RE

G

VC

C1

BLK

LIM

VC

C2

FB

_B

G_O

UT

FB

_R

R_O

UT

GN

D2

NC

NC

NC

RG

T

VD

D

AG

CA

DJ

AG

CT

C

PIC

T

GN

D1

MO

DE

1

MO

DE

2

EX

T_R

EX

T_G

EX

T_B

RP

D

VS

S

CK

I

CK

O

TE

ST

2

N C

V D

H D

H C K 1

H C K 2

H S T 1

H S T 2

C L R

E N

V C K 1

V C K 2

VST1

N C

S L C K

TEST0

TEST1

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

RST/T INT

C O L O R

Y_I

N

SY

NC

FB

_G

B_O

UT

C L A M P

A G C

PIC CONT

C L A M P

MATRIX

C O N T

S U BC O N T

E X T S W

S/H

BRIGHT

G A M M A

RGB GAIN

S U BBRIGHT

P O L S W

PLL PC

S Y N C S E P

M O D ES E L E C T

H S Y N CD E T

V S Y N CS E P

H-CTLH - P O STIMING

PLS GEN

V-CTLV-POSTIMING

PLS GEN

FIELD&LINE CTL

PLLC O U N T

ELIM/M O D E

M C KS U B C K

R G B

Y

1/2 Vcc2

B-Y

R-Y

Fig. 3-15-4 LCD driver (IC7201) pin assignment

3-47

3.15.2 LCD driver (IC7201) pin functions-1/2


1 SYNC In Y signal input for sync

2 Y IN In Y signal input

3 AGCADJ In AGC level adjustment

4 AGCTC - AGC time constant

5 PICT In Picture control (sharpness)

6 GND1 - GND

7 MODE1 In Mode select (H:NTSC /M:DPAL /L:SPAL)

8 MODE2 In Mode select (H:composite /M:Y,Chroma /L:Y,C)

9 EXT-R In

10 EXT-G In

11 EXT-B In

12 RPD Out PLL phase comparison

13 VSS - GND

14 CKI In Clock input (VF:11.06MHz /MONI:16.52MHz)

15 CKO - Not used

16 TEST2 -

17 TEST1 -

18 TEST0 -

19 SLCK In LCD panel select (H:VF /L:MONI)

20 NC - Not used

21 VST1 Out Vertical start pulse output

22 VCK2 Out Vertical clock pulse 2 output

23 VCK1 Out Vertical clock pulse 1 output

24 EN Out Gate select pulse enable

25 CLR Out Uniformity pulse output

26 HST2 - Not used

27 HST1 Out Horizontal start pulse output

28 HCK2 Out Horizontal clock pulse 2 output

29 HCK1 Out Horizontal clock pulse 1 output

30 HD Out HD pulse output

31 VD Out VD pulse output

32 NC - Not used

On-screen input

Not used

Table 3-15-1 LCD driver (IC7201) pin functions-1/2

3-48

·LCD driver (IC7201) pin functions-2/2


33 VDD - Power supply digital 3.5V

34 RGT In H:normal scan /L:reverse scan control

35 NC -

36 NC -

37 NC -

38 GND2 - GND

39 R OUT Out R output

40 FBR In R DC voltage feed back

41 G OUT Out G output

42 FBG In G DC voltage feed back

43 B OUT Out B output

44 FBB In B DC voltage feed back

45 VCC2 - Power supply analog 10V

46 BLKLIM In Black peak limit level adjustment

47 VCC1 - Power supply analog 3.5V

48 REG - Capacitor for regulator

49 B-Y IN In B-Y input

50 R-Y IN In R-Y input

51 C OUT - Not used

52 RST/TINT - Not used

53 COLOR - Not used

54 XVXO - Not used

55 R-BRT In R brightness adjustment

56 B-BRT In B brightness adjustment

57 RGB GAIN In RGB gain adjustment

58 GAMMA2 In Gamma 2 adjustment

59 GAMMA1 In Gamma 1 adjustment

60 BRIGHT In Brightness adjustment

61 CONT In Contrast adjustment

62 C IN - Not used

63 R GAIN In R gain adjustment

64 B GAIN In B gain adjustment

Not used

Table 3-15-1 LCD driver (IC7201) pin functions-2/2

3-49

3.15.3 LCD SUBTG (IC7203) PIN ASSIGNMENT

V-POSIT IONC O U N T E R

XHST

VDDNTPAL

LFRP

FRPI

XEN

HFRP

ENENI

HDI

VDI

HCK1I

1

14

13

12

11

7

6

5

4

3

2

VSS

CLRI

8

9

10

15

16

17

18

19

20

VSTI

HSTI

XCLR

XVST

P C G

XPCG

H-POSIT IONC O U N T E R

D E C O D E R&

V-T IMING PULSEG E N E R A T O R

D E C O D E R&

H-T IMING PULSEG E N E R A T O R

P A L P U L S EE L I M N A T O R

FIELD & L INEC O N T R O L L E R

Fig. 3-15-5 LCD SUBTG (IC7203) pin assignment

3.15.4 LCD SUBTG (IC7203) pin functions

Pin No. Label In/Out Description1 NTPAL In NTSC:H /PAL:L select2 VDI In VD pulse input3 HDI In HD pulse input4 ENI In Gate select pulse enable5 CLRI In Uniformity pulse input6 HCK1I In H clock pulse 1 input7 VSTI In V start pulse input8 HSTI In H start pulse input9 XCLR In System clear (L:clear)10 VSS - GND11 FRPI In Pulse input for alternating current drive 12 LFRP Out Not used13 HFRP Out Pulse output for alternating current drive 14 XPCG Out Uniformity pulse output (inverted PCG)15 PCG Out Uniformity pulse output16 XEN Out Gate select pulse enable output (inverted EN)17 EN Out Gate select pulse enable output18 XVST Out V start pulse output (inverted VST)19 XHST Out H start pulse output (inverted HST)20 VDD - Power supply

Table 3-15-2 LCD SUBTG (IC7203) pin functions

3-50

3.16 MIC CIRCUIT

P S

P S

L-ch

R-chF

C

R

R2611

R2612

R2613 R2614

10k

4.7k

4.7k 4.7k

Q2601

Q2602

0.047or

O P E N

C2610R

C

F

L-ch R-ch

F R O N T

Fig. 3-16-1 Triangle microphone

As the previous pocket type movie's microphone was attached to the top of the unit, directivity was difficultto grasp from the front. In this unit, three microphones are arranged triangularly, and the front directivityhas been improved sharply by vector calculation.As shown in the figure, the microphones are located at the front F, rear R, and center C and the phase ofthe difference in the time to reach the microphone from the L and R is shifted and added to create the L-chand R-ch audio signal.Phase shift (PS) is performed by the capacitor C2610 in the microphone input circuit as shown in thefigure. At phase shifted line, 0.047 mF is input to C2610 while those which are not, the status is OPEN.

3-51

3.17 SYSCON CPU

3.17.1 SYSCON CPU (IC1001) pin functions-1/4


15 S_OPEN Out Lens cover open control forward

29 S_CLOSE Out Lens cover close control reverse

2 AD0 In/Out

42 AD1 In/Out

16 AD2 In/Out

56 AD3 In/Out


43 VSS - GND

4 AD4 In/Out

57 AD5 In/Out

5 AD6 In/Out

31 AD7 In/Out

18 AD8 In/Out

44 AD9 In/Out

6 AD10 In/Out

58 PWR_CTL Out Power control to REG section

19 M16_RDY In MSD IC1401 READY

45 AD11 In/Out

33 AD12 In/Out

46 AD13 In/Out

20 AD14 In/Out

7 AD15 In/Out

59 MODE0 In GND

8 MODE1 In GND

34 MODE2 In AL3V

21 M16_CS Out MSD IC1401 chip select

47 CLK_4MHz Out Not used

22 F/Z_CS Out F/Z DRIVER IC4851 chip select


10 OSCI In System clock (16MHz)

35 OSCO Out System clock (16MHz)

23 VSS - GND

9 VSS - GND

30 VSS - GND

32 VSS - GND

51 VSS - GND

Address/data MPX BUS 16bits from/to YMCA IC4301



Table 3-17-1 SYSCON CPU (IC1001) pin functions-1/4

3-52



142 VSS - GND

37 FLDFMC In Field distinction

36 BATT_DOWN In Battery down detect

38 RST In Reset

49 PIT In Docking station detect

50 V_MUTE Out Video mute

60 JLIP_INT In JLIP interrupt

63 VD In Verticl drive pulse

62 OMT In EIS data read timing

64 EXTINDET In EXT_DC detect

73 MENU_P_A In Menu dial pulse A

77 FRP In Frame reference pulse

75 RTC_INT In Clock 1 second interrupt

76 TNW In FMC busy

74 AH_CTL1 Out Jack select

90 AH_CTL2 Out Jack select

86 OSD_CS Out OSD IC1002 chip select

89 EEPROM_CS Out EEPROM IC1003 chip select


101 TIMER_OUT Out Not used

100 TALLY Out Tally LED on/off control

102 CHG_CTL Out Charge control

99 P_DET In Plug detect

103 REMOTE In Remote input

114 S_DT_IN In Serial data input from MSD, EEPROM, RTC

116 S_DT_OUT Out Serial data output to MSD TG CDS/AGC EEPROM DAC RTC

113 S_CLK Out Serial clock

115 VF_CTL Out VF back light

128 OSD_DATA Out OSD data

127 OSD_CLK Out OSD clock

129 RXD In RS232C data input

140 TXD Out RS232C data output

141 AUDIO_CS Out AUDIO IC2201 chip select

165 AVDD - Power supply




3-53





136 AVSS - GND

125 AVSS - GND

153 RESERVE4 - Not used

139 AFZ_DATA Out Serial data output to AUDIO FZ_MDA

166 AFZ_CLK Out Serial data clock AUDIO FZ_MDA


152 VSS - GND

112 AVSS - GND

151 VRefL - ADCGND

138 BATT_CHK In Battery DC input

164 KEY_A In Deck operation switch input

111 KEY_B In Camera operation switch input

163 ZOOM_SW In Zoom switch input

137 IR_DA In AWB IR sensor AD input

150 HALL_AD In Iris motor hole generator AD input

124 Z_PTR_AD In ZOOM position sensor AD input

162 F_PTR_AD In FOCUS position sensor AD input

110 TG_CS Out TG IC5002 chip select

149 CDS/AGC_CS Out CDS/AGC IC5601 select

123 AVH_DET In Plug detect input AV:H HP:L

135 BATT_SW In Battery detect


148 MONI_RVS In LCD monitor reverse switch

109 VRefH - ADC REG3V


160 WB_IR_DET In Flicker detect

134 M16_RST Out Reset for MSD IC1401

147 BUZZER Out Buzzer signal output

121 MENU_SET_SW In Menu set switch

146 RTC_CS Out RTC IC1004 chip select

133 DAC_CS Out EVR/DAC IC3503 chip select

158 LWE Out Write enable

132 HWE Out Write enable

145 RE In Read enable


3-54



107 VDD(VPP) - Power supply



119 ALE Out Address latch enable


120 VSS - GND

130 DIAL_5S In Dial switch 5S position

108 DIAL_ST In Dial switch ST position

118 DIAL_MANU In Dial switch MANU position

106 DIAL_AUTO In Dial switch AUTO position

105 DIAL_OFF In Dial switch OFF position

95 DIAL_PLAY In Dial switch PLAY position

104 EJECT_SW In Eject switch

93 CAS_SW In Cassette switch

91 MONITOR_SW In LCD monitor switch

94 VF_SW In VF switch

92 MENU_P_B In Menu dial pulse B


78 SHUT_RST Out Reset for YMCA IC4301(shutter sound section)

81 74_RST Out Reset for YMCA IC4301

79 F/Z_RST Out Reset for F/Z DRIVER IC4851

68 M_U/D_LR1 Out

67 M_U/D_LR2 Out

69 BK_L_CTL1 Out

66 BK_L_CTL2 Out


65 IRIS_O/C In/Out IRIS open/close

55 Z_LED Out Zoom wide end sensor LED control

52 F_LED Out Focus infinity sensor LED control

40 SMUTE Out Shutter sound mute

53 S_SPK_ON Out Speaker on/off control


26 FADE_H Out Pulse at fader end

28 AFADER Out During fader:H output

27 A_MUTE Out Audio mute


Back light contrlo 3-state outputH:monitor+backlight M:monitor L:VF on

LCD monitor control (up/down,L/R) 3-state outputH:NORMAL M:PLAY MODE(U/D) L:EE MODE(U/D+L/R)


3-55

3.18 MSD CPU

3.18.1 MSD CPU (IC1401) pin functions-1/4

Pin No. Label In/Out Description1 VSS - GND2 HLDA - Not used3 HOLD - H:fixed4 RESET In Reset input from SYSCON CPU5 MOD0 - L:fixed6 MOD1 - H:fixed7 VCC - Power supply8 VSS - GND9 VPP - Power supply REG 5V10 ADC_DEM0 Out11 ADC_DEM1 Out12 ADC_PWD0 Out D/A power control power down:L to AUDIO AD/DA IC210113 ADC_PWD1 Out A/D power control power down:L to AUDIO AD/DA IC210114 DIC_STP1 Out Serial communication enable to DVIO IC320215 DIC_STP2 In/Out Communication start/stop signal to/from CAS IC300116 TRIG_OUT Out Remote signal output17 P97 - Not used18 VSS - GND19 OSCVCC - Power supply20 XIN In X'tal 27MHz21 XOUT Out X'tal 27MHz22 OSCVSS - GND23 VSS - GND24 VCC - Power supply25 P100 -26 P101 -27 P102 -28 P103 -29 P104 -30 P105 -31 P106 -32 P107 -33 P110 -34 P111 -35 P112 -36 P113 -37 P114 -38 P115 -39 P116 -

Sampling frequency select to AUDIO AD/DA IC2101ADC_DEM0/ADC_DEM1:frequency (L/L:44.1k, L/H:48k, H/L:OFF, H/H:32k)

Not used

Table 3-18-1 MSD CPU (IC1401) pin functions-1/4

3-56

·MSD CPU (IC1401) pin functions-2/4

Pin No. Label In/Out Description40 P117 - Not used41 VCC - Power supply42 VSS - GND43 VCC - Power supply44 CAM0 In45 CAM1 In46 CAM2 In47 REC_SAFE In Rec safety switch48 REEL_LED Out Reel sensor LED control49 RF_TRICK Out Slow/still:H (for EQ PLL gain adjust ) PB EQ50 RF_FAST Out Search:H (for EQ PLL gain adjust ) PB EQ51 RF_STAB Out Safety tab (REC prohibition) to PRE/REC IC350252 VCC - Power supply53 VSS - GND54 DRUM_FG In Drum FG55 CAP_FG In Capstan FG56 TSR In HID reference (drum 150Hz)57 HID In Head switch pulse58 SPA In ATF sample pulse59 T_REEL In TU reel pulse60 S_REEL In SUP reel pulse61 SSP In DVC bus sector start signal from CAS IC300162 FRP In Frame reference pulse from DVIO IC320263 MCVS In 1394 frame reference pulse from DVIO IC320264 PWMO In PWM output for audio PLL65 VSS - GND66 VCC - Power supply67 DIC_RST Out Reset output to CAS, EDA, DVIO68 LD_ON Out Loading motor ON/OFF control69 CAP_BRK Out Capstan motor brake control70 TXD -71 RXD -72 MDA_CS Out MDA IC1601 chip select73 MDA_CLK Out Serial clock to MDA IC160174 MDA_IN Out Serial data output to MDA IC160175 MDA_OUT In Serial data input from MDA IC160176 DIF_RST Out Reset to DIF IC800177 DIC_CLK Out Serial clock to CAS IC3001, DVIO IC320278 DIC_IN Out Serial data output to CAS IC3001, DVIO IC3202

Mechanism position detect from rotary encoder

Not used


3-57


Pin No. Label In/Out Description79 DIC_OUT In Serial data input from CAS IC3001, DVIO IC320280 MREADY Out Serial bus ready to SYSCON CPU IC100181 SYS_CLK In Serial clock to SYSCON CPU IC100182 SYS_IN Out Serial data output to SYSCON CPU IC100183 SYS_OUT In Serial data input from SYSCON CPU IC100184 VCC - Power supply85 VSS - GND86 DIF_INT In DIF interrupt from DIF IC800187 P55/INT3 -88 P56/INT2 -89 P57/INT1 -90 MSELECT In MSD chip select input from SYSCON CPU IC100191 NMI In H:fixed92 DRUM_REF Out Drum offset voltage output to MDA IC160193 CAP_REF Out Capstan offset voltage output to MDA IC160194 V_PLL Out PLL output to PLL IC3201(18MHz when 1394 input)95 A_PLL Out Audio PLL output (PWM) to PLL IC320196 MIC_CTL Out97 MIC_SDA Out98 MIC_SCK Out99 FRP In Frame reference pulse from DVIO IC3202100 TAPE_LED Out Tape LED control101 VSS - GND102 VCC - Power supply103 P72/TA2 -104 P73/TB2 -105 P74/TA3 -106 P75/TB3 -107 P76/TA4 -108 P77/TB4 -109 P84/TA5 -110 P85/TB5 -111 P86/TC5 -112 P87/ADTRG -113 AVSS - GND114 AN12 -115 AN11 -116 AN10 -117 BCID3 In Cassette tape ID board information

Not used

Not used

For memory in cassetteonly information of recorded or brand-new tape

Not used


3-58


Pin No. Label In/Out Description118 BCID2 In119 BCID1 In120 AN06 -121 AN05 -122 AN04 -123 AN03 -124 DEW_SENS In Dew sensor detect125 E_SENS In End sensor detect126 S_SENS In Start sensor detect127 AVREF - Reference Voltage 1/2VCC128 AVCC - Power supply129 VCC2 - Power supply REG 2.2V130 VSS - GND131 AGC_RST Out Reset to VIDEO OUTPUT DRIVER IC3701132 BCLK Out System clock 13.5MHz to DIF IC8001133 DC In Access comletion signal from DIF IC8001134 R/W - Not used135 ALE Out Address latch enable136 RD Out Read strobe to EDA IC3003137 BLW Out Write strobe to EDA IC3003138 BHW - Not used139 D00 In/Out140 D01/A16 In/Out141 D02/A17 In/Out142 D03/A18 In/Out143 D04/A19 In/Out144 D05/A20 In/Out145 D06/A21 In/Out146 D07/A22 In/Out147 D08/A23 In/Out148 D09/A24 In/Out149 D10/A25 In/Out150 D11/A26 In/Out151 D12/A27 In/Out152 D13/A28 In/Out153 D14/A29 In/Out154 D15/A30 In/Out155 VSS - GND156 VCC2 - Power supply REG 2.2V

Data (16 bits) /address (15 bits) from/to EDA,DIF

Not used

Cassette tape ID board information


3-59

3.19 MDA FUNCTION

3.19.1 MDA (IC1601) pin assignment

DR

IVE

SIG

NA

L LOG

IC

UP

PE

R/LO

WE

R D

IVIS

ION

VCC

D.UIN

D.VIN

D.WIN

D.COM

DC

C1

DC

C2

DC

C3

DC

C

U N R E G

D.UH

D.VM

D.U

D.VH

D . W

D . W H

D.V

D.GNDSTARTTIMING

OSC

BRAKE

D R U M _ P W R

D.ECR

D.ECDRUM_REF

REG_5V

TORQUE CTL

D.BRK

CURRENT FEED BACK

D.FG-

D.PG-

D.FGPG+

D R U M _ F G

D R U M _ P G

D.FGSOUT

D.PGSOUT

DR

IVE

SIG

NA

L LOG

IC

UP

PE

R/LO

WE

R D

IVIS

ION

C .HU+C.UH

C.U

C.VH

C . W

C . W H

C.V

C.GND

HALL

HALL

HALL

C.HU-

C.HV+

C.HV-

C . H W +

C.HW-

C.VM

C.EC

C.MODE

DC/DCC.VSC.ECR

C.ECCAP_REF

REG_5V

TORQUE CTL

RIPPLECANCEL

C.RCC

CURRENTLIMITC.TL

C.MODE

DIRECTIONC.FR

BRAKEC.BRK

D.FG-

D.FG+

C.VM

D R U M _ F G

SHIFTREGISTER

&LATCH

CS

CLK

DIN

D O U T

C.FRC.MODEC.TL

D.BRKD.PG.SM

L.FINL.RINP W _ S A V E

CTLLOGIC

L.FIN L.RIN

L .FWD

L.REV

L.GND

U N R E G

D.PG.SM

P O W E RSAVE

P W _ S A V E

CAP.M

LOAD.M

DRUM.MIC1602

IC1603CAP.M

CAP.M

REG_5V

D.OSC

CAP_BRK

MDA_CS

MDA_CLK

MDA_IN

MDA_OUT

CAP_ERR

C A P _ P W R

L.REF

D.FG+

Fig. 3-19-1 MDA (IC1601) pin assignment

3-60

3.19.2 MDA (IC1601) pin functions-1/2

Pin No. Label In/Out Description1 GND1 - GND2 D.U Out Drum motor output3 D.VM In Drum power4 D.V Out Drum motor output5 D.RNF - Drum GND (current detect resistor)6 L.REF In Loading motor output reference voltage7 D.W Out Drum motor output8 L.FWD Out Loading motor output9 GND2 - GND10 L.GND - Loading motor GND11 NC - Not used12 UNREG - Power for load motor driver, drum BEMF comparater (REG 5V)13 L.REV Out Loading motor output14 C.U Out Capstan motor output15 NC - Not used16 C.RNF - Capstan GND (current detect resistor)17 C.V Out Capstan motor output18 C.VM In Drum power19 C.W Out Capstan motor output20 C.CH Out21 C.VH Out22 C.WH Out23 C.HW- In24 C.HW+ In25 C.HV- In26 C.HV+ In27 C.HU- In28 C.HU+ In29 C.FGSOUT Out Capstan FG output30 C.FGOUT Out Capstan FG amp. Output31 C.FG- In32 C.FG+ In33 VCC - Power supply34 C.VS In Capstan motor power control35 C.PCV In Terminal for prevent saturation36 C.PCI In Terminal for prevent saturation37 C.ECR In Capstan torque reference38 C.EC In Capstan torque control39 C.RCC In Capstan ripple cancel40 C.BRK In Capstan brake :H

Capstan motor output (pre-drive)

Capstan motor holl signal input

Capstan FG input

Table 3-19-1 MDA (IC1601) pin functions-1/2

3-61

·MDA (IC1601) pin functions-2/2

Pin No. Label In/Out Description41 NC - Not used42 CLK In Clock input43 CS In Chip select input44 DIN In Serial data input45 DOUT Out Serial data output46 D0 -47 D1 -48 D2 -49 D3 -50 D4 -51 GND2 - GND52 NC - Not used53 D.EC In Drum torque control54 D.ECR In Drum torque reference55 D.PCI In Terminal for prevent saturation56 D.PCV In Terminal for prevent saturation57 D.OSC In Drum osc58 START In Drum start mode time setting59 DETECT In Drum detect mode time setting60 TEST1 -61 TEST2 -62 D.PGSOUT Out Drum PG output63 D.PGOUT Out Drum PG amp output64 D.PG- In Drum PG input65 D.FGPG+ In Drum FG/PG common input66 D.FG- In Drum FG input67 D.FGOUT Out Drum FG amp output68 D.FGSOUT Out Drum FG output69 GND1 - GND70 D.UIN In71 D.VIN In72 D.WIN In73 D.COM - Drum motor common74 DCC3 -75 DCC2 -76 DCC1 -77 DCC In Drum current control78 D.UH Out79 D.VH Out80 D.WH Out

Not used

Not used

Drum BEMF comparater input

Drum slope shape

Drum motor output (pre-drive)

Table 3-19-1 MDA (IC1601) pin functions-2/2

SECTION 4ERROR RATE ADJUSTMENT

4-1

·PB EQ (Error Rate) AdjustmentError rates can be checked on the screen of service support software beginning with the GR-DVM5.(However while the Error Rate is displayed, the time code of the monitor onscreen will stop at the valuejust before and operations will stop.)Adjustment procedures and contents are the same as before. But when PB EQ (error rate) adjustment isselected, the following Error Rate screen appears. The following describes the displays.

The error rate is displayed in thisbox which is the total number ofboth channel, and next boxes areseparate numbers of CH1 and CH2.These numbers wi l l be updatedevery second. The A V means audioand video, usually the error raterepresents the total number of audioand video sect ions, same numberas using the error rate JIG.When the viterbi is switched on oroff, "Error " is appeared in the boxmomentari ly, that is normal.

These six i tems are new function.The error rate of audio and videopart can be shown individually. It iseasy to understand what proport ionof audio and video in the total errorrate, therefore it wil l be able to usefor judgment of tape pass problem.

This bar display is imaged the pattern of tape, that is useful forjudgment of tape problem such as block noise. Sync block numbersof each area wil l be shown in percentage and color. Ordinari ly, i twi l l become O K and BLUE that sync block wil l be detected perfectly(100%). I f they become other than BLUE as f ig.2, that may becaused by tape pass, tape damage or off adjustment of PB EQseriously. It is necessary to check them if there is not BLUE area,even if the error rate values are less than the specif ied value.

f ig.1

fig.2

4-2

·VITERBI ON/OFFEven during PB EQ (error rate) adjustment, viterbi ON/OFF instructions will be given, the GR-DVM5automatically turns On the viterbi when playback starts (from the stop state) for both SP/LP. Whenstopping, viterbi goes off. In other words, even if viterbi is turned off using the Fig. 3 menu during playback,it will turn on in playback after. This will require the viterbi to be turned off again.

When the unit is going to playbackfrom stop mode, the VITERBI modewil l be switched to ON automatical ly,even i f display remains OFF here.Therefore, in order to make VITERBIoff mode, i t is necessary to selectagain after playback.

f ig.3

·ATF ON/OFFIn the ATF OFF state, the 0.13 mm tracking can be shifted for every 01h using the editor shown in Fig. 5.Previously, 80h was the center position and the shift was greatest at 00h and FFh. But with GR-DVM5, thecenter has been changed to 00h and FFh. In this case, the shift is the greatest at 80H.

fig.4

The center posit ion is 00h orFFh.The default value is 00h.

After select ATF OFF, theEdit ing window wil l appear asfig.5.

f ig.5

VICTOR COMPANY OF JAPAN, LIMITED

Printed in Japan9903 (TM1)

Jvc Gr-dvm5 Technical Guide

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