Intro to VLSI System Design

8/8/2019 Intro to VLSI System Design

1/46

ECE425 Intro VLSI System Design

Elec t r ic a l Com put er Eng ineer ing

ECE425

Int roduc t ion t o VLSISyst em DesignProf. Deming Chen


2/46


Lec t u re Not es

The lecture notes will include some material not covered in theprinciple textbook and will be the primary course material.

However, the level of details and description in the notes willnot be as complete as the information that you would find in atextbook. I will also try to include additional information to helpyou understand the material.

Some of the notes used in this course are courtesy of NickCarter, David Harris, and Ken Yang.


3/46


Course Resourc es

Lectures: MW 11-12:20, Transportation building 101

Web page: http://courses.ece.uiuc.edu/ece425

Check the web page a few times per week; this is wherecorrections to homework assignments and changes to officehours will be posted. Class notes will be posted on the sameday of the lecture (usually in the afternoon).

Webboard at the web page

This is the primary means of staff-student communicationoutside of lecture hours and office hours. This is where you

should post questions or information that might be of interestto your fellow students, i.e., a note that the design toolsarent working or that a homework problem is missing anecessary parameter. The TAs or instructor will check thisforum often and will post responses to any queries.


4/46


Reading

Text book

Weste & Harris, CMOS VLSI Design(3rd edition)

Recommended book on synthesis

De Micheli, Synthesis and Optimization of Digital Circuits

Some related research publications

Other reference books:

Sherwani, Algorithms for VLSI Physical Design Automation Rabaey, Chandrakasan, Nikolic, Digital Integrated Circuits:

a Design Perspective (2ndedition)


5/46


Admin is t ra t i ve

Prof. Deming Chen ([email protected])

Office Hours: Mon. 1:00-3:00 PM (or by appointment) at 410 CSL

Phone: (217) 244-3922

TAs:

Liang Deng ([email protected])

Office Hours: TBD

David Krauss ([email protected])

Office Hours: TBD

Additional TA office hours will be added before the MP orhomework due. Please check webboard for update information.


6/46


Grading

Homework assignments (6): 10% Exams (mid-term and final): 40%

Machine Problems (4): 40% Pop-up quiz (4): 10%

MPs will be due in TAs mailboxes in Everitt Lab on the duedates Accepted up to five working days late, 10%/day penalty

Late arrivals counted as of when TAs get them Email TAs right away after you put your reports in their

mailboxes

Hand deliver to them Everyone gets 3 no-questions-asked days of extension to

use during the semester for MPs Homeworks will be due in class (no late acceptance)


7/46



8/46


Lec t ure 1

Overv iew of VLSI :Com plex i t y , Wires, and

Sw i t ches

Deming Chen

Some slides courtesy of Ken Yang (UCLA)

and David Harris (Harvey Mudd)


9/46


Overview

Reading

Weste & Harris; 1.1-3, 1.5, 1.7-12

Background

VLSI is a maturing field; it has its beginning back in the early 60'swith SSI, small scale integration, when a few bipolar transistors

and resistors were fabricated on the same chip. Today chips areboth simpler and more complex. They typically only contain twoactive elements (nMOS and pMOS transistors) and wires. Butthere might be hundreds of millons of these transistors on thechip, and these chips can do amazing functions. You also find

chips in everything. This lecture will look at why this has happenedand what makes VLSI design challenging. It will also take a quicklook at the basic elements that make up VLSI chips: MOStransistors and wires.


10/46


The Big Pic t ure

Want to go from this:


11/46


To this:


12/46


Magni f ied


13/46


Why?

Easier to move/control electrons than real stuff

Electronic calculators, not mechanical

Move information, not things (phone, fax, WWW, etc.)

Building electronics:

Started with tubes, then miniature tubes

Transistors, then miniature transistors

Components were getting cheaper, but:

There is a minimum cost of a component (storage, handling )

Total system cost was proportional to complexity

Integrated Circuits changed that

Print a circuit, like you print a picture, Create components in parallel

Cost no longer depended on # of devices

What happens as resolution goes up?


14/46


Invent ion o f t he Trans ist or

Vacuum tubes ruled in first half of 20th century Large,expensive, power-hungry, unreliable

1947: first point contact transistor John Bardeen and Walter Brattain at Bell Labs

(Nobel Prize in Physics in 1956)

We call it the Transistor,

T-R-A-N-S-I-S-T-O-R,

because it is a resistor

or semiconductor device

which can amplify electrical

signals as they are transferred


15/46


A Br ie f H is t ory

1958: First integrated circuit

Flip-flop using two transistors

Built by Jack Kilby at Texas Instruments 2003

Intel Pentium 4 processor (55 million transistors)

512 Mbit DRAM (> 0.5 billion transistors) 53% compound annual growth rate over 45 years

No other technology has grown so fast so long

Driven by miniaturization of transistors Smaller is cheaper, faster, lower in power!

Revolutionary effects on society


16/46


Am azing Ex ponent ia l Grow t h

Bill Gates: If GM had kept up with the technology like the computerindustry has, we would all be driving $25.00 cars that got 1,000 milesto the gallon.

GM responded (just for fun) If GM had developed technology likeMicrosoft, we would all be driving cars with the followingcharacteristics: 1. Occasionally, executing a maneuver would cause your car to

stop and fail to restart and you'd have to re-install the engine. 2. Occasionally, for no reason whatsoever, your car would lock

you out and refuse to let you in until you simultaneously lifted thedoor handle, turned the key and grabbed hold of the radio antenna.

3. You could only have one person in the car at a time, unless you

bought a "Car 95" or a "Car NT". But then you'd have to buy moreseats. 4. The airbag system would say "Are you sure?" before going off. 5. You'd have to press the "Start" button to turn the engine off.


17/46


Annual Sales

1018 transistors manufactured in 2003

100 million for every human on the planet

0

50

100

150

200

1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002

Year

GlobalSemiconductorBillings

(BillionsofUS

$)


18/46


1970s processes usually had only nMOS transistors

Inexpensive, but consume power while idle

1980s-present: CMOS processes for low idle power

MOS In t egrat ed Ci rc u i t s

Intel 1101 256-bit SRAM Intel 4004 4-bit Proc


19/46


Moores Law

1965: Gordon Moore plotted transistor on each chip

Fit straight line on semilog scale

Transistor counts have doubled every 26 months

Year

Transistors

40048008

8080

8086

80286Intel386

Intel486Pentium

Pentium ProPentium II

Pentium IIIPentium 4

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

1,000,000,000

1970 1975 1980 1985 1990 1995 2000

Integration Levels

SSI: 10 gates

MSI: 1000 gates

LSI: 10,000 gates

VLSI: > 10k gates


20/46


Corol lar ies (1)

Many other factors grow exponentially

Ex: clock frequency, processor performance

Year

1

10

100

1,000

10,000

1970 1975 1980 1985 1990 1995 2000 2005

4004

8008

8080

8086

80286

Intel386

Intel486

Pentium

Pentium Pro/II/III

Pentium 4

C

lockSpeed(MHz)


21/46


Corol lar ies (2)

Since the cost of the printing process (calledwafer fabrication) is growing at a slower rate,

it implies that the cost per function, isdropping exponentially. At each newgenerations, each gate cost about 1/2 what itdid 3 years ago. Shrinking an existing chip

makes it cheaper!

yearyear

diecost

ln(cost/function)


22/46


Bad new s: Produc t iv i t y Gap

xxx

xxx

x 21%/Yr.Productivity growth rate

x

58%/Yr. Complexitygrowth rate

1

10

100

1,000

10,000

100,000

1,000,000

10,000,000

1998

10

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

LogicTransistors/Chip(K)

Transistor/Staff-Mo

nth

Chip Capacity and Designer Productivity

2003

Source: NTRS97

Th C t f N t G t i


23/46


The Cost o f Nex t Generat ion

Product

Source: IBS I nc.

Wireless chip case

Networking chip case

0.18um 0.13um 90nm

10

20

30

40

50

0.15

Total Product Cost ($M) $30M ~ $50M @ 90nmEngineering Cost 60% up

Manufacturing Cost 40% up

NRE/Mask Cost 100% up

Product

Cost

Respin cost 78% up


24/46


ITRS2003

Year of production2004 2006 2008 2010 2012 2015 2018

MPU/ASIC Pitch (nm) 90 70 57 45 35 25 18

Functions per chip (milliontransistors) 553 878 1,393 2,212 3,511 7,022 14,045

Chip size at production(mm2) 310 310 310 310 310 310 310

Maximum power for high-performance withheatsink (W) 158 180 200 218 240 270 300

On chip local clock (MHz) 4,171 6,783 10,972 15,079 20,065 33,403 53,207

Maximum wiring level 14 15 16 16 16 17 18


25/46


Sense of Sc ale

What fits on a VLSI Chip today?

130nm chip

20mm on a side (400mm2)

0.13mm drawn gate length 0.5mm wire pitch

8-level metal

For comparison

32b RISC processor 8K x 16K

SRAM

about 32 x 32 per bit

8K x 16K is 128Kb, 16KB

DRAM 8 x 16 per bit

8K x16K is 1Mb, 128KB

20mm(40,000 wire pitches)

320,000

0.13m (2 )

32b RISCProcessor

64b FPProcessor

0.5m

(8 )


26/46


Tec hnology Sc a l ing

Number of grids per chipdoubles every 3 years

more functionality perchip

harder to design

Two problems

What do you do with allthat space -- whatfunction?

How do you make sureit works

2010

2004

1998

The Cha l lenge in VLSI Design


27/46


The Cha l lenge in VLSI Design

Managing Com plex i t y

Simplify the design problem

Cant understand 10M transistors, or 100M rectangles

Need to make less complex (and less numerous) models

Abstraction Simplified model for a thing, works well in some subset of the design

space

Modeling Constraints

Needed to ensure that the abstractions are valid

Might work if you violate constraints, but guarantees are off

Understand the underlying technology

Provide a feeling for what abstractions and constraints are needed.

Determine efficient solutions (make the right tradeoffs).

CAD tools use the abstractions and constraints to help us manage thecomplexity.

They do not replace the need to understand the technology.

In fact, we now need to understand how tools work.

Real i t y o f VLSI Design


28/46


Real i t y o f VLSI Design J uggl ing Tradeoffs

Bottom line is $$$$

To the VLSI designer, the external constraints and issues aremulti-dimensional.

Portables (power - performance/area)

DRAM (area - features/performance)

DSP (design time/area - performance)

Military (robustness - power/performance)

Area

Design time andresources Robustness

Performance

Power


29/46


VLSI Des ign

Besides all that,

I think it is fun.

I hope you agree.

What is on an In t egrat ed


30/46


What is on an In t egrat ed

Ci rcu i t?

Actually only two types of devices:

Conducting layers which form the wires on the IC.

There are many layers of wires (used to have 1 layer of metal,now advanced processes have 8-10 metal layers). Wires haveelectrical properties like resistance and capacitance.

(Requires insulators and contacts between layers.)

Transistors (the free things that fit under the wires).

There are a few kinds of transistors. In this class we will studyMOS ICs, so we will work with MOS transistors. Thesetransistors can be thought of as a voltage controlled switch.The voltage on one terminal of the transistor determineswhether the other two terminals are connected or not.

Physic a l Topology of an


31/46


Physic a l Topology of an

In t egra t ed Ci rc u i t

The transistors are built in the silicon, and then there are lots of wiringlayers deposited on top. In cross-section it looks like (abstractly):

Silicon

Many more metals

Diffusion layer, poly layer, and various metal layers.


32/46


- Anot her V iew :

Chip consists of

transistors:fabricated onthe silicon surface and

wires:that connect thetransistors fabricated onlayers of metal separatedby insulators

Most of the area are the wires

Top View

Cross Section

polygate

metalwire contactdiffusion

n-well

n-well


33/46


Trans is tors

The voltage on the gate (poly connection) controls the current

that flows between the source and drain (diffusion terminals).

The transistor model is often displayed by drawing its current-voltage curve. We will talk about more later.

0 0.5 1 1.5 2 2.50

100

200

300

400

500

600

Vds(V)

I

d

s

(

u

A

)

IDS

sourcedraingate


34/46


A MOSFET as a Sw i t c h

Three terminal device

source, drain

two ends of conductive path gate

controls conductive path

operation

conducts when gate is high open circuit when gate is low

caveat

passes 0s well, not 1s

source

gate

drain

This description is for nMOS transistors. For pMOS everything is reversed. Thesource is the higher voltage terminal, and the transistor is on when the gate ismuch lower than the source. More on pMOS later

Layout : The Fabr ic at ion


35/46


Layout : The Fabr ic a t ion

Spec i f i ca t ion

The end of the design process must create a set of drawings, one for eachlayer needed in the manufacturing process

Layout drawings are complicated

There are many rules about the geometry to make sure thecircuits can be reliably manufactured

Minimum width of wire, minimum spacing between wires,alignment rules

The layers represent transistors and wires, and need to createthe correct function

Many rectangles for each transistor and wire, and there aremillions of transistors and wires.

Different layers are represented by different colors People used to draw the layout on mylar (10s of transistors)

But not any more, now use CAD tools (to help with abstraction,visualization, and constrain to design rules), and pre-madecells (for partitioning, hierarchy)

Sim ple Layout Ex am ple of a


36/46


Sim ple Layout Ex am ple of a

Sim ple Proc essor

Simple examples

Use hierarchy to hide

complexity Pads around chip

Major blocks are

shown Design is broken

into a controller thatcontrols dataflow.

Colored regions arereally many wires


37/46


Layout

This picture is anexpanded view of aportion of the layoutof the other page.

The next two slides:

Controller layout

Handleinstructioninputs

Datapath layout

Moving dataaround


38/46


Cont ro l ler Layout Right half

shows cells inthe design

Left half hasthe cellsexpanded to

show thelayout layers

This designstyle has

random wires


39/46


Dat apat h Layout

Wires here are more

regular. Words are 16bits

wide.

Each path is

repeated 16x Again

Cells on right

Expanded cells on

left Transistor density is

higher

A Sl ight ly More Pow er fu l


40/46


g y

Processor

By convertingrectangles intotransistors,transistors intogates, gates intofunctions, andfunctions into anarchitecture, weresult in somethingquite remarkable.

Pentium 4

2.2cm

Abst rac t ions and Disc ip l ines


41/46


p

How t o Dea l w i t h 10 8 Trans is tors

Digital abstraction

signals are 1 or 0

Switch abstraction

MOSFETs as simpleswitches

Gate abstraction

Unidirectional elements Separable timing

Synchronous abstraction

Race free logic Function does not depend

on timing

Constrain the design space tosimplify the design process

strike a balance between

design complexity andabsolute performance

Partition the problem

(Use hierarchy) Module is a box with pins

apply recursively

D i L l


42/46


Design Levels

Specification

what the system (orcomponent) is supposed to

do

Architecture

high-level design ofcomponent

state defined

logic partitioned intomajor blocks

Logic

gates, flip-flops, and theconnections between them

Circuit

transistor circuits to realizelogic elements

Device

behavior of individualcircuit elements

Layout

geometry used to defineand connect circuitelements

Process

steps used to define circuitelements

Design Proc edure and Tools


43/46


Design Proc edure and Tools

1. Concept

divider

2. Architecture

subtract/compare

3. Logical Implementation

ab+bc+ac

xor

4. Physical layout + Verify

mask layers (rectangles)

1. C-modeling (algorithms)

2. Behavior modeling

Verilog or VHDL

3. Logic Synthesis

Design Analyzer

(Synopsys) Verify Synthesis

Static Timing

4. Place and Route Silicon Ensemble

(Cadence)

Verify P&R

Dynamic Timing

A More Real is t ic Design Flow


44/46


A More Real is t ic Design Flow

SchematicEntry Cell

CharacterizationLayoutEntry

Standard Cell Library

3-D RLCModeling

Tool

Wire ModelDevice model

Layout rules

,,

Layers

Synthesis Library (Timing/Power/Area)

C-Model VerilogBehavioral

ModelVerilog

StructuralRTL

StructuralModel

Parasitic Extraction LibraryPlace & Route Library (Ports)

Floorplan

GlobalLayout

BlockLayout

Floorplan

P & R

Functional

DRC/ERC/LVS

Static/Dynamic Timing w/ extractFunctional

Static TimingPower/Area Scan/Testability

Synthesis P & R

Clock Routing/Analysis


45/46

N t L t


46/46


Nex t Lec t ure

IC Fabrication

Readings

Text 1.3, 1.5.1-2

Intro to VLSI System Design

Documents

Transcript of Intro to VLSI System Design