Intel 80486 Introduction - Engineering Class Home Pages · EE454L_Lab26_80486_intro.fm 2/5/07 80486...
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EE454L_Lab26_80486_intro.fm 2/5/07 80486 Introduction 1 / 12 Intel 80486 Introduction Prelude to lab 26
Transcript of Intel 80486 Introduction - Engineering Class Home Pages · EE454L_Lab26_80486_intro.fm 2/5/07 80486...
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Intel 80486 Introduction
Prelude to lab 26
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Intel 80486 pinout
32-bit data, 32-bit address, Byte-Addressable Processor
Does not preform micromanagement.
Declares its intent and waits for RDY.
Needs a bus controller.
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486 has on chip cacheCache line size (Cache Block size) = 4 words ( 4 32-bit words)Example: Words 40, 44, 48, 4C make up a cache block.
Forwarding: The cache control unit fetches the word needed by the processor first and then the rest of the three.
Two burst orders: Linear and Interleaved Intel
Linear Burst order
FirstData
SecondData
ThirdData
Fourth Data
A3 A2 A3 A2 A3 A2 A3 A2 0 0 0 1 1 0 1 1 0 1 1 0 1 1
Linear Burst order
FirstData
SecondData
ThirdData
Fourth Data
4044 48 4C
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Intel Interleaved Burst Order
Intel Interleaved Burst order
FirstData
SecondData
ThirdData
Fourth Data
A3 A2 A3 A2 A3 A2 A3 A2 0 0 0 1 1 0 1 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 1 1 1 0 0 1 0 0
Linear Burst Order4-way Interleaved MM 2-way Interleaved MM
Intel Interleaved Burst order
FirstData
SecondData
ThirdData
Fourth Data
4044 48 4C
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74L
S373
Lat
ch
Intel Interleaved Burst order
FirstData
SecondData
ThirdData
Fourth Data
A3 A2 A3 A2 A3 A2 A3 A2 0 0 0 1 1 0 1 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 1 1 1 0 0 1 0 0
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Intel 80486 Burst Bus cycles
To support bursting, it has two special signals (pins):
BLASTBRDY 486
MemoryController
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NON-BURST Bus Cycle No Wait States
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NON-BURST Bus Cycle With 1 Wait State
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BURST READ Cycle No Wait States
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BURST READ Cycle With 1 Wait State
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M/IO# W/R#
4Bus Cycles
