Intel Itanium Architecture(64-bit)â€

download Intel Itanium Architecture(64-bit)â€

of 53

  • date post

    28-Nov-2014
  • Category

    Technology

  • view

    2.173
  • download

    11

Embed Size (px)

description

 

Transcript of Intel Itanium Architecture(64-bit)â€

  • 1. Intel Itanium Architecture(64-bit)
  • 2.
      • Overview
  • 3. Overview
    • Why develop?
      • RISC processing limit of one instruction per cycle predicted 1989 by HP
      • Led to HP development of EPIC(Explicitly Parallel Instruction Computing)
        • Uses a form of VLIW(Very Long Instruction Word)
      • HP decides to partner with Intel to develop new Architecture based off EPIC in 1994
      • IA-64 is born
  • 4. Versions
    • Merced
      • Codename of the first Intel/HP joint IA-64 chip
      • Development problems
        • Transistor numbers
        • Teams had different priorities
        • Unanticipated research
    • Itanium
      • Official name of Merced
      • Released 2001
      • Due to development delays was lacking
        • Called the Itanic
        • RISC and CISC performance increases due to superscaler architectures
  • 5. Versions
    • Itanium 2
      • Released 2002
      • Codenamed McKinley
      • Improved on Itanium design
      • Outperformed comparable RISC and CISC processors
    • Madison
      • Released 2003
      • Basis for all future versions until 2006
  • 6. Versions
    • Montecito
      • Released 2006
      • Dual Core implementation of Itanium 2
      • Performance Doubled
      • Power Consumption cut by 20%
      • New Features also added
        • multi-threading(two per core)
        • Expanded cache
        • Silicon level support for virtualization
    • Montvale
      • Released 2007
      • Fastest IA-64 chip to date
  • 7. Competing Chips
    • UltraSPARC(Scalable Processor Architecture)
      • Developed by Sun Microsystems
      • RISC Architecture
    • SPARC64
      • Developed by Fujitsu
      • RISC Architecture
    • POWER6(Performance Optimization With Enhanced RISC)
      • Developed by IBM
      • RISC Architecture
  • 8. Competing Chips
    • Opteron
      • Developed by AMD
      • X86 Architecture
    • Xeon
      • Developed by Intel
      • X86 Architecture
  • 9. Intel Itanium Architecture
      • Chip Layout
  • 10. Chip Layout
    • Itanium Architecture Diagram
  • 11. Chip Layout
  • 12. Itanium Specs
    • 4 Integer ALU's
    • 4 multimedia ALU's
    • 2 Extended Precision FP Units
    • 2 Single Precision FP units
    • 2 Load or Store Units
    • 3 Branch Units
    • 10 Stage 6 Wide Pipeline
    • 32k L1 Cache
    • 96K L2 Cache
    • 4MB L3 Cache(extern)
    • 800Mhz Clock
  • 13. Itanium Specs
    • Process 180nm
    • System Bus Speed 2.1GB/s
      • 266Mhz
      • 64 bit Wide
  • 14. Itanium2 Specs
    • 6 Integer ALU's
    • 6 multimedia ALU's
    • 2 Extended Precision FP Units
    • 2 Single Precision FP units
    • 2 Load and Store Units
    • 3 Branch Units
    • 8 Stage 6 Wide Pipeline
    • 32k L1 Cache
    • 256K L2 Cache
    • 3MB L3 Cache(on die)
    • 1Ghz Clock initially
      • Up to 1.66Ghz on Montvale
  • 15. Itanium2 Specs
    • 180nm Process
      • Increased to 130nm in 2003
      • Further increased to 90nm in 2007
    • System Bus Speed 6.4GB/s
      • 400Mhz
      • 128 bit Wide
  • 16. Itanium2 Improvements
    • Initially a 180nm process
      • Increased to 130nm in 2003
      • Further increased to 90nm in 2007
    • Improved Thermal Management
    • Clock Speed increased to 1.0Ghz
    • Bus Speed Increase from 266Mhz to 400Mhz
    • L3 cache moved on die
      • Faster access rate
  • 17. IA-64 Pipeline Features
    • Branch Prediction
      • Predicate Registers allow branches to be turned on or off
      • Compiler can provide branch prediction hints
    • Register Rotation
      • Allows faster loop execution in parallel
    • Predication Controls Pipeline Stages
  • 18. Cache Features
    • L1 Cache
      • 4 way associative
      • 16Kb Instruction
      • 16Kb Data
    • L2 Cache
      • Itanium
        • 6 way associative
        • 96 Kb
      • Itanium2
        • 8 way associative
        • 256 Kb Initially
          • 256Kb Data and 1Mb Instruction on Montvale!
  • 19. Cache Features
    • L3 Cache
      • Itanium
        • 4 way associative
        • Accessible through FSB
        • 2-4Mb
      • Itanium2
        • 2 4 way associative
        • On Die
        • 3Mb
          • Up to 24Mb on Montvale chips(12Mb/core)!
  • 20. Instruction Set Architecture
  • 21. Registers
      • 128 Integer Registers