IHI0014Q Etm Architecture Spec

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Transcript of IHI0014Q Etm Architecture Spec

Embedded Trace Macrocell

ETMv1.0 to ETMv3.5

Architecture Specification

Copyright 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved. ARM IHI 0014Q (ID101211)

Embedded Trace MacrocellArchitecture SpecificationCopyright 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved.Release Information The following changes have been made to this book.Change history Date 30 March 1999 12 July 1999 03 December 1999 18 May 2000 06 September 2000 15 January 2001 08 May 2001 25 July 2001 17 December 2002 16 July 2004 17 March 2005 04 November 2005 14 December 2005 08 February 2006 20 July 2007 Issue A B C D E F G H I J K L M N O Confidentiality Limited Confidential Limited Confidential Non-Confidential Confidential Non-Confidential Confidential Non-Confidential Non-Confidential Non-Confidential Non-Confidential Non-Confidential Confidential Confidential Non-Confidential Non-Confidential Change First release for ETMv1.0 and ETMv1.1. Errata 01 corrections incorporated for ETMv1.1 and ETMv1.0. Protocol enhancements and modified trace port connector pinout added. ETMv1.0 and ETMv1.1 release. Protocol version 2 enhancements added. ETMv1.2 release. Minor corrections to Issue D incorporated. ETMv1.2 release. Protocol version 3 enhancements added to support the tracing of Java instructions. ETMv1.3 release. Description of protocol versions and variants included. Released in conjunction with fixes to errata in ETMv1.2 and ETMv1.3. Description of ETMv2.0 enhancements included. Incorporation of ETMv2.1, ETMv3.0, and ETMv3.1 architectures. Incorporation of ETMv3.2 architecture. Minor corrections and updates. Incorporates ETMv3.3 architecture, re-organizes descriptions of address comparators, and has minor enhancements elsewhere. Final draft of ETMv3.4 issue. Non-confidential release of ETMv3.4 issue. No change to content. Various enhancements, updates and corrections, incorporating all errata to Issue N. Updated Implementer codes list. Added summary of IMPLEMENTATION DEFINED ETM features to Appendix A. First release for ETMv3.5. Minor corrections and updates.

18 December 2009 23 September 2011

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Confidential Non-Confidential

Proprietary Notice This Embedded Trace Macrocell Architecture Specification is protected by copyright and the practice or implementation of the information herein may be protected by one or more patents or pending applications. No part of this Embedded Trace Macrocell Architecture Specification may be reproduced in any form by any means without the express prior written permission of ARM. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this Embedded Trace Macrocell Architecture Specification. Your access to the information in this Embedded Trace Macrocell Architecture Specification is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations of the ARM architecture infringe any third party patents. This Embedded Trace Macrocell Architecture Specification is provided as is. ARM makes no representations or warranties, either express or implied, included but not limited to, warranties of merchantability, fitness for a particular purpose, or non-infringement, that the content of this Embedded Trace Macrocell Architecture Specification is suitable for any particular purpose or that any practice or implementation of the contents of the Embedded Trace Macrocell Architecture Specification will not infringe any third party patents, copyrights, trade secrets, or other rights. This Embedded Trace Macrocell Architecture Specification may include technical inaccuracies or typographical errors.

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Copyright 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved. Non-Confidential

ARM IHI 0014Q ID101211

To the extent not prohibited by law, in no event will ARM be liable for any damages, including without limitation any direct loss, lost revenue, lost profits or data, special, indirect, consequential, incidental or punitive damages, however caused and regardless of the theory of liability, arising out of or related to any furnishing, practicing, modifying or any use of this Embedded Trace Macrocell Architecture Specification, even if ARM has been advised of the possibility of such damages. Words and logos marked with or TM are registered trademarks or trademarks of ARM Limited, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners. Copyright 1999-2002, 2004-2009, 2011 ARM Limited 110 Fulbourn Road, Cambridge, England CB1 9NJ Restricted Rights Legend: Use, duplication or disclosure by the United States Government is subject to the restrictions set forth in DFARS 252.227-7013 (c)(1)(ii) and FAR 52.227-19. This document is Non-Confidential but any disclosure by you is subject to you providing notice to and the acceptance by the recipient of, the conditions set out above.

In this document, where the term ARM is used to refer to the company it means ARM or any of its subsidiaries as appropriate.

NoteThe term ARM is also used to refer to versions of the ARM architecture, for example ARMv6 refers to version 6 of the ARM architecture. The context makes it clear when the term is used in this way.

ARM IHI 0014Q ID101211

Copyright 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved. Non-Confidential

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Copyright 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved. Non-Confidential

ARM IHI 0014Q ID101211

Contents Embedded Trace Macrocell Architecture Specification

PrefaceAbout this specification ................................................................................................ x Using this specification ............................................................................................... xi Conventions ............................................................................................................... xii Additional reading ..................................................................................................... xiii Feedback .................................................................................................................. xiv

Chapter 1

Introduction1.1 1.2 About Embedded Trace Macrocells ....................................................................... 1-16 ETM versions and variants .................................................................................... 1-20

Chapter 2

Controlling Tracing2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 About controlling tracing ........................................................................................ ETM event resources ............................................................................................. ETM event logic ..................................................................................................... Triggering a trace run ............................................................................................. External outputs ..................................................................................................... Trace filtering ......................................................................................................... Address comparators ............................................................................................. Operation of data value comparators ..................................................................... Instrumentation resources, from ETMv3.3 ............................................................. Trace port clocking modes ..................................................................................... Considerations for advanced processors, ETMv2 and later only ........................... Supported standard configurations in ETMv1 ........................................................ Supported configurations from ETMv2 .................................................................. Behavior when non-invasive debug is disabled ..................................................... 2-22 2-23 2-33 2-34 2-35 2-36 2-49 2-64 2-69 2-72 2-74 2-77 2-79 2-80

ARM IHI 0014Q ID101211

Copyright 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved. Non-Confidential

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Contents

Chapter 3

Programmers Model3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 About the programmers model .............................................................................. 3-82 Programming and reading ETM registers .............................................................. 3-83 CoreSight support .................................................................................................. 3-89 The ETM registers .................................................................................................. 3-90 Detailed register descriptions ................................................................................. 3-99 Using ETM event resources ................................................................................. 3-194 Example ViewData and TraceEnable configurations ........................................... 3-199 Power Down support ............................................................................................ 3-203 About the access permissions for ETM registers ................................................. 3-210 Access permissions for ETMv3.3 and ETMv3.4, SinglePower ............................. 3-213 Access permissions for ETMv3.3 and ETMv3.4, multiple power domains ........... 3-216 Access permissions for ETMv3.5, SinglePower ................................................... 3-220 Access permissions for ETMv3.5, mul