IEEE TRANSACTIONS ON ADVANCED PACKAGING...

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IEEE TRANSACTIONS ON ADVANCED PACKAGING 1

Nonlinear Thermal Stress/Strain Analyses of CopperFilled TSV (Through Silicon Via) and

Their Flip-Chip MicrobumpsCheryl S. Selvanayagam, John H. Lau, Fellow, IEEE, Xiaowu Zhang, S. K. W. Seah, Kripesh Vaidyanathan, and

T. C. Chai

Abstract—Most TSVs are filled with copper; siliconpoly andtungsten are the alternatives. The coefficient of thermal expansion(CTE) of copper ( ��

� C) is a few times higher thanthat of silicon ( � � ��

� C). Thus, when the copper filledthrough silicon via (TSV) is subjected to temperature loadings,there is a very large local thermal expansion mismatch between thecopper and the silicon/dielectric (e.g., SiO�), which will createvery large stresses and strains at the interfaces between the copperand the silicon and between the copper and the dielectric. Thesestresses/strains can be high enough to introduce delaminationbetween the interfaces. In this paper, the nonlinear thermalstresses and strains at the interfaces between the copper, silicon,and dielectric have been determined for a wide-range of aspectratios (of the silicon thickness and the TSV diameter). One of themajor applications of TSV is as an interposer. Because of Moore’s(scaling/integration) law, the silicon chip is getting bigger, thepin-out is getting higher, and the pitch is getting finer. Thus, theconventional substrates, e.g., BT (bismaleimide triazine) cannotsupport these kinds of silicon chips anymore and a silicon in-terposer (substrate) is needed to redistribute the very fine-pitchand high pin-count pads on the chip to much larger pitch andless pin-count through the silicon vias on the silicon substrate.Depending on the via-size and pitch of the copper filled TSV, theeffective CTE of the copper filled TSV interposer could be as highas ��

� C. Consequently, the global thermal expansionmismatch between the silicon chip and the copper filled TSVsubstrate can be very large and the bumps (usually very small,e.g., microbumps) between them may not be able to survive underthermal conditions. In this study, the nonlinear stresses and strainsin the microbumps between the silicon chip and copper filled TSVinterposer (with and without underfills) have been determined fora wide-range of via sizes and pitches, and various temperatureconditions. These results should be useful for 1) making a decisionif underfill is necessary for the reliability of microbumps and 2)selecting underfill materials to minimize the stresses and strainsin the microbumps.

Index Terms—Copper, modeling, strain, stress.

Manuscript received April 02, 2008; revised March 18, 2009. This paper wasrecommended for publication by Associate Editor A. Chandra upon evaluationof the reviewers comments.

The authors are with the Institute of Microelectronics, Agency for Sci-ence, Technology, and Research (A*STAR), Singapore 117685 (e-mail:[email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TADVP.2009.2021661

Fig. 1. Package incorporating TSV interposer. Inset shows details of TSV.

I. INTRODUCTION

A S MOORE predicted in 1965, silicon chips are gettinglarger while incorporating a higher pin count and smaller

bump pitch. Unfortunately, conventional substrates, e.g., BT(bismaleimide triazine) cannot support these fine-pitched sil-icon chips. Hence, there is a need for an intermediate substrateto redistribute the large array of fine-pitched pads on the chipto fewer, relatively large-pitched pads on the BT substrate. Oneof the major applications of the through silicon vias on siliconsubstrate is to serve as this intermediate substrate. One suchpackage structure with a detailed schematic of the through sil-icon via (TSV) is shown in Fig. 1. The fabrication steps whichsubject it to various temperature cycles coupled with the largedifference in coefficients of thermal expansion of copper andsilicon results in a TSV which is susceptible to ring crackingand delamination. The other application for the TSV is for usein chip stacking as the interconnect length is reduced comparedto perimeter wire bonding.

Several authors have turned to finite element modeling forinsight on the stress state in a filled TSV. While some authorswere concerned with the stresses induced by the different pro-cesses involved in making a TSV, (i.e., etching, coating, plating,etc.) [1], [2], others focused on the materials [1], [3] or designaspects [4] of the TSV. By far, the most comprehensive studyon the stress state in a TSV was carried out by Takana et al. [5]who investigated not only the effect of via size on thermal mis-match, but also possible cracking due to loading force duringthe stacking process and bump reliability under thermal fatigue.Unfortunately, these papers focus on the mechanical reliabilityof specific designs and do not provide any design guidelines forthe design of reliable TSVs. This paper will provide these de-sign guidelines by first assessing and analyzing the stress state

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2 IEEE TRANSACTIONS ON ADVANCED PACKAGING

of a single TSV to determine the main contributor of failure at aregion localized around the via. Subsequently, the accumulatedeffect of the localized thermal strains around each TSV (i.e., theglobal effect), which results in mismatch, on a larger scale, be-tween the interposer and chip, will be analyzed. The softwareABAQUS version 6.7-1 was used for all the simulations carriedout in this paper.

II. LOCAL THERMAL EXPANSION MISMATCH

Mechanical modeling of any structure for the electronics in-dustry requires knowledge of the final service conditions and ac-curate material properties. Certain aspects of the structure suchas complex geometry and thin compliant layers can be simpli-fied or assumed negligible to reduce computational time withoutsignificantly affecting the results.

In the TSV, the presence of materials with different coef-ficients of thermal expansion (CTE) will induce thermal mis-match stresses and strains during temperature cycling. In orderto assess the possibility of failure, the following models wereanalyzed. First, a simple axi-symmetric model of silicon witha core filled with copper was considered. This was followedby a model of silicon with a core plated with a thin layer ofcopper instead of completely filled. The effect of the redistri-bution layer (RDL) was then taken into account for both theabove-mentioned cases to assess its reliability. Finally, a diag-onal slice model of a chip mounted onto a silicon interposer withTSV was used to determine the effect of the presence of TSV tothe reliability of the corner microbump during temperature cy-cling.

A. Modeling of Copper-Filled TSV

For determining thermal stress in a TSV, the following as-sumptions were made.

1) Since the layer of tantalum (1 k ) is much thinner than thedielectric layer (1 m), its effect is negligible.

2) The redistribution layer is very thin and therefore negli-gible.

3) Silicon and silicon oxide are not strained beyond theirelastic zone.

4) Copper undergoes elastic deformation, followed by plasticdeformation.

5) The silicon interposer with TSV is stress-free at 125 C.The simplified diagram of the TSV based on the above as-

sumptions is shown in Fig. 2(a). One quarter of this was modeledin an axi-symmetric simulation. The boundary conditions usedand the mesh at the critical interfaces are shown in Fig. 2(b) and(c), respectively. Note that directions 1 and 2 the radial and axialdirections, respectively. A static temperature ramp down anal-ysis from 125 C to C was carried out to simulate the max-imum strained state. The modeling matrix and material proper-ties used are shown in Tables I and II.

During the temperature cycling of the TSV, each tempera-ture ramp up results in copper expanding more than 5 times asmuch as silicon and more than 10 times as much as silicon oxide.The deformation resulting from heating from C to 125 Cand cooling from 125 C to C exaggerated 100 times isshown in Fig. 3(a) and (b) for better visualization of what hap-pens. From Fig. 3(a), it is clear that the silicon oxide layer is

Fig. 2. (a) Diagram of simplified TSV. (b) Quarter model of TSV with appliedboundary conditions. (c) Mesh of critical region.

TABLE IMODELING MATRIX

TABLE IIMATERIAL PROPERTIES

highly strained as it is dragged along by the axial expansion ofthe copper and compressed by the radial expansion of copper.This strain however is largely not transferred to the bulk of thesilicon, as silicon is much stiffer than copper and silicon oxide.Conversely, during temperature ramping down also a high strainis induced on the material near the interface indicated by pointsA and B.

There are two critical points where failure may occur. Firstly,failure could occur due to the tearing action during contraction,at the interface between copper and silicon oxide [points A andB in Fig. 2(c)]. Secondly, cracking of copper or silicon oxidecould occur at the midplane of the TSV [points C and D inFig. 2(c)]. For the simulations carried out, the radial stress at



SELVANAYAGAM et al.: NONLINEAR THERMAL STRESS/STRAIN ANALYSES OF COPPER FILLED TSV 3

Fig. 3. Deformation in TSV exaggerated 100�.

points A and B, and the axial strains at C and D were monitoredto give an indication of the stress and strains causing delamina-tion and cracking in those regions.

The radial stresses in the copper and silicon oxide at the crit-ical corner plotted against the diameter of the via for different as-pect ratios are shown in Fig. 4. It is observed that the radial stressincreases linearly with the diameter of the via, with a steeper in-crease in vias with larger aspect ratios. This is indicated by theslopes of the graphs marked on Fig. 4. Though a larger diameterof copper via induces a similar thermal strain, the deformationin copper is increased, resulting in a larger strain and thereforelarger stresses. The stress in silicon oxide is greater than that incopper for all cases due to its higher elastic modulus. In addi-tion, the change in stress due to varying of aspect ratio effectis most evident in vias with smaller diameters—approximately15% increase in radial stress is observed in a via of mcompared to 2% increase for m.

The axial strains at points C and D in copper and silicon oxideare plotted on the graphs in Fig. 5. As expected due to their closeproximity, the strains in copper and silicon oxide are identicalfor all aspect ratios and diameters. At an aspect ratio of 1, theaxial strains are largest. As the aspect ratio increases, the straindecays. Beyond an aspect ratio of 5, axial strain is no longerdependant on aspect ratio. As the axial strain values are belowthe elongation values of copper and silicon oxide obtained fromliterature to be 2% [6] and 30% [7], respectively, cracking onthe mid-plane is not expected.

The widened range of radial stress in the case of aspect ratioof 1 (Fig. 4) and the convergence of axial strain beyond an as-

Fig. 4. Radial stress �� at critical corner for (a) copper (point A) and (b)silicon oxide (point B) in filled vias.

Fig. 5. Axial strain �� at mid-plane for (a) copper and (b) silicon oxide infilled vias.

pect ratio of 5 (Fig. 5) are caused by the proximity of the freeedge on top of the via to the fixed edges (the axis and the mid-plane) which constraints the deformation. Fig. 6 shows the axialstrain contours of vias of various aspect ratios. Vias with an as-pect ratio larger than 7 experience large strains at the top of thevia, instead of more distributed strains seen in vias with smalleraspect ratios.

B. Modeling of Unfilled TSV

In addition, the case of an unfilled TSV was also modeledin order to assess its mechanical behavior in comparison with




Fig. 6. Axial strain �� contours of filled TSV of � � �� at various aspectratios.

a filled via. The diagram, finite element model and mesh forthis unfilled via is shown in Fig. 7(a), (b), and (c), respectively.The modeling matrix and material properties used are shownin Tables I and II. Note that the thickness of the copper layermodeled is 3 m for all cases.

In the case of the unfilled via, the relationship between thediameter and the radial stress is no longer linear as shown inFig. 8. It is observed that radial stress is highly dependant onvia diameter. The little difference in radial stress between theextreme aspect ratios at the smaller diameter (5%) is reduced toalmost 0% in the case of the larger diameters in both copper andsilicon oxide.

Radial stress increases linearly with increasing diameter infilled vias (Fig. 4). In unfilled vias, however, an opposite trendis observed. This is because in the filled via, as copper contractsit pulls the silicon oxide and silicon, which contract less, in-wards. A larger via diameter with its larger volume of copperresults a larger thermal mismatch and hence a higher state ofstress. In the unfilled via, the copper is unconstrained on theinner surface of the via. As a result, the copper is free to moveinward to release the normal stress. In the unfilled via, there aretwo mechanisms at work to decrease the stress state—decreasedvolume of copper and unconstrained surface area. It was foundthat the ratio of these parameters has a linear

Fig. 7. (a) Diagram of TSV not filled with copper. (b) Quarter model of TSVwith applied boundary conditions. (c) Mesh of critical region.

Fig. 8. Radial stress �� at critical corner for (a) copper (point A) and (b) sil-icon oxide (point B) in unfilled vias. (c) Linear relationship with �� .

relationship with the radial stress in the unfilled via as shown inFig. 8(c).

A large reduction in stress results when replacing a filled viawith an unfilled one. For the same aspect ratio and diameter,




Fig. 9. Axial strain �� at mid-plane for (a) copper (point C) and (b) siliconoxide (point D) in unfilled vias.

substituting the filled via with the unfilled one can reduce theradial stress by 1.8 to 4.4 times in copper and by 1.8 to 2.4 timesin silicon oxide. The largest reductions in stress were found tooccur in larger vias of smaller aspect ratios.

The reduction in axial strain in the unfilled vias comparedto the filled ones is most pronounced at smaller aspect ratios(shown in Fig. 9). At these aspect ratios, smaller diameters havelarger strains. The axial strain contours shown in Fig. 10 indi-cate that the larger diameters have larger length of silicon toconstrain the copper contraction.

C. Modeling Details of TSV With Redistribution Layer

In TSV fabrication, once the via is made by deep reactiveion etching (DRIE), a thin passivation layer of silicon oxide isdeposited on the silicon at high temperature. This is followedby via filling through electroplating. Next the wafer undergoeschemical mechanical polishing (CMP) and another thin passiva-tion layer of silicon oxide is then deposited at high temperature.The copper in the RDL is then sputtered at room temperature.Finally, the entire structure undergoes annealing to remove anyresidual stress induced by the deposition processes. As a result,residual stress is assumed negligible in this modeling work.

The redistribution layer in the model would simulate the realsituation to a larger extent as it would include the possibility ofcracking of the RDL. Hence, its effect in both the filled and un-filled via was studied. A schematic drawing of the cross-sectionof the filled via, the one-quarter finite element model and themesh at the critical location in shown in Fig. 11. The unfilledvia with RDL model is simply the model in Fig. 7 with an RDLlayer.

For the model including the RDL layer, failure is expected tooccur in the RDL layer at a 45 from the surface of the coppervia. Hence, the strain along directions 1 and 2 have been re-solved to determine the diagonal strain denoted by along the

Fig. 10. Axial strain (� � contours showing undeformed and deformed statesin copper of unfilled TSV for �� .

Fig. 11. (a) Diagram of simplified TSV with RDL. (b) Quarter model of TSVwith applied boundary conditions. (c) Mesh of critical region.




Fig. 12. Diagonal strain �� at critical location for (a) copper (pointA) and (b) silicon oxide (point B) in filled vias with RDL.

-direction (indicated in Fig. 11) was calculated using (1). At, there is no cosine term

(1)

The diagonal strain at point A and B are plotted in Fig. 12 forthe filled via and Fig. 13 for the unfilled via. As shown in thefigure, there is a linear relationship between the diagonal strainand the diameter of the via. As expected, the strain in the copperis lower than that in the silicon oxide. In the unfilled via with theRDL, diagonal strains decrease with diameter. This is becausethe ratio of t/D is smaller resulting in relatively less expansionin copper.

The axial strain at point C for the filled and unfilled vias isshown in Fig. 14 for the model with RDL. The axial strain curvesat point D are not shown as they had identical axial strains asthe copper. Note that these curves are very similar to those inFig. 5(a) and Fig. 9(a), which show the axial strains in copperin the model without the RDL. Hence, for the purpose of deter-mining axial strain, the RDL may be ignored.

III. GLOBAL THERMAL EXPANSION MISMATCH

A. Modeling Solder Ball Fatigue due to Global ThermalMismatch

The effective CTE of the silicon interposer is higher whenit contains copper in the form of filled TSVs. As a result, ontemperature cycling, the interposer will expand and contractmore than the chip, resulting in a fatigue loading on the solderjoint. The effect of this global mismatch on the reliability ofthe solder bump was investigated in the following simulations.

Fig. 13. Diagonal strain �� at critical location for (a) copper (pointA) and (b) silicon oxide (point B) in unfilled vias with RDL.

Fig. 14. Axial strain �� at mid-plane for copper (point C) in (a) filled and(b) unfilled models with RDL.

The global model consisting of a chip assembled onto a siliconinterposer containing TSVs was made to undergo three cyclesof temperature cycling between C to 125 C. A diagonal




Fig. 15. (a) Diagram of global model. (b) Diagonal slice model with appliedboundary conditions. (c) Mesh of critical region.

TABLE IIIMODELING MATRIX

TABLE IVMATERIAL PROPERTIES

slice of this model was considered for computational efficiency.A schematic diagram of the model, the applied boundary con-ditions and the mesh of the critical region are shown in Fig. 15.The modeling matrix, material properties of copper and solderare shown in Tables III and IV, respectively.

Fig. 16. Creep strain energy density per cycle variation with interposer height(H).

Fig. 17. Creep strain energy densities for three interposer heights.

The creep properties of 95.5Sn3.8Ag0.7Cu solder were as-signed using the Garofalo-Arrhenius creep law shown belowwhere the material constant A was 32 000 s , B was 0.037E-6Pa , n was 5.1 and Q was 54.3 kJ/mol [8]

(2)

Results of the analysis indicate that as the height of the inter-poser increases, the creep strain energy density in the solder in-crease as shown in Fig. 16. For interposer heights of 50–200, themaximum strain energy density occurs at the top of the solderjoint. On the other hand, for interposer heights of 300–500,the maximum strain energy occurs at the bottom surface of thesolder joint. Maximum strain energy position is transferred tothe bottom when the expansion of the interposer begins to exerta shearing load on the solder. This effect can be seen in Fig. 17where the solder joint on the shortest interposer has much re-duced strain energy density at its bottom surface. The use ofunderfill reduces the inelastic strain energy density by 4 times.

Increasing the pitch results in a decreasing of the creep strainenergy density as shown in Fig. 18. This is a result of the de-creased copper content and hence decreased mismatch betweenthe silicon chip and the silicon interposer with TSVs. Fig. 19shows the creep strain energy for two different pitches decreasesto almost the similar values when used with underfill.




Fig. 18. Creep strain energy density per cycle variation with via pitch (P).

Fig. 19. Creep strain energy density per cycle variation with aspect ratio (H/D).

IV. CONCLUSION AND RECOMMENDATIONS

Nonlinear stress/strain analyses of the local and globalthermal mismatches have been presented. The local stress/strainanalyses considered the effect of not only the aspect ratio butalso the unfilled via as opposed to the one completely filledwith copper. The global model was used to quantify the life (viathe creep strain energy density per cycle) of the micro-solderjoints which interconnect the TSV interposer and the chip.Some important results and recommendations are summarizedin the following.

A. Local Thermal Expansion Mismatch

1) For all the TSVs considered, in general, above an aspectratio (thickness/diameter) of 5, there is little dependenceof stress and strain on the aspect ratio of the via.

2) For the perfect TSV structures modeled, failures at the in-terfaces of the TSV (due to the local thermal expansionmismatch among the Si, SiO , and Cu) are unlikely as thestrains in these elements are not large enough to cause fail-ures.

3) The imperfections that could arise during fabrication (suchas the poor bonding between interfaces and the presenceof asperities which act as points of stress concentration)compounded with the stresses due to the local thermal ex-pansion mismatch could result in failure. Thus, it is recom-mended that the TSV structures be fabricated as perfectlyas possible.

4) Silicon oxide dielectric layer is in a higher state of stresscompared to copper as a results of its lower CTE comparedto copper. Hence extra care should be taken during thedielectric-layer fabrication to ensure a high quality TSV.

B. Global Thermal Expansion Mismatch

1) The increased content of copper in the TSV interposerincreased its effective CTE. Hence, the global thermalmismatch between the Si-chip and the Cu-filled TSV-in-terposer could be very large and the micro-solder jointsconnecting them are subjected to very large stresses andstrains, especially the corner ones.

2) For a given TSV pitch and diameter, the thickness of theCu-filled Si-interposer plays a very important role. Thelarger the thickness, the larger the creep strain energy den-sity per cycle, and thus the shorter the thermal-fatigue lifeof the micro-solder joints.

3) For a given TSV thickness and diameter, the pitch of theCu-filled Si-interposer also plays an important role. Thelarger the pitch, the smaller the creep strain energy densityper cycle, and thus the longer the thermal-fatigue life of themicro-solder joints.

4) Underfill prolongs the life of the micro-solder joints bycementing the Si-chip to TSV-interposer. This reducesthe global thermal expansion mismatch and decreases thestresses and strains in the micro-solder joints. It has beenfound that with the presence of underfill, the maximumcreep strain energy density per cycle acting at the cornermicro-solder joint can be reduced as much as 4 times.

5) Based on the cases considered, underfill is recommended,especially for thick and fine-pitch Cu-filled Si-interposer.

REFERENCES

[1] B. Wunderle, R. Mrossko, O. Wittler, E. Kaulfersch, P. Ramm, B.Michel, and H. Reichl, “Thermo-mechanical reliability of 3D-inte-grated microstructures in stacked silicon,” in Mater. Res. Soc. Symp.Proc., 2007, p. 970.

[2] J. U. Knickerbocker et al., “Development of next generationsystem-on-package (SOP) technology based on silicon carrierswith fine-pitch chip interconnection,” IBM J. Res. Develop., vol. 49,no. 4/5, pp. 725–753, 2005.

[3] P. A. Miranda and A. J. Moll, “Thermo-mechanical characterizationof copper through-wafer interconnects,” presented at the Electron.Compon. Technol. Conf., San Diego, CA, 2006.

[4] S. Burkett, L. Schaper, T. Rowbotham, J. Patel, T. Lam, U. Abhulimen,D. D. Boyt, M. Gordon, and T. Cai, “Material aspects to consider in thefabrication of through-silicon vias,” in Mater. Res. Soc. Symp. Proc.,2007, pp. 970–.

[5] N. Takana, T. Sato, Y. Yamaji, T. Morifuji, M. Umemoto, and K. Taka-hashi, “Mechanical effects of copper through-vias in a 3D die-stackedmodule,” in Electron. Compon. Technol. Conf., San Diego, CA, 2002,pp. 473–479.

[6] D. T. Read, Y. W. Cheng, and R. Geiss, “Morphology, microstructure,and mechanical properties of a copper electrodeposit,” Microelectron.Eng., vol. 75, pp. 63–70, 2004.

[7] Z. Cao and X. Zhang, “Measurement of stress-strain curves of PECVDsilicon oxide thin films by means of nanoindentation,” in Mater. Res.Soc. Symp. Proc., 2007, vol. 977.

[8] H. L. J. Pang, B. S. Xiong, C. C. Neo, X. R. Mang, and T. H. Low, “Bulksolder and solder joint properties for lead free 95.5Sn-3.8Ag-0.7Cusolder alloy,” in Electron. Compon. Technol. Conf., New Orleans, LA,2003, pp. 673–679.

[9] H. L. J. Pang, B. S. Xiong, and T. H. Low, “Creep and fatigue charater-isation of lead fress 95.5Sn3.8Ag-0.7Cu solder,” in Electron. Compon.Technol. Conf., Las Vegas, NV, 2004, pp. 1333–1337.




Cheryl S. Selvanayagam received the degree in me-chanical engineering from the National University ofSingapore.

She has been with the Institute of Microelectronicssince 2006. Her research interests include materialcharacterization and mechanical modeling.

John H. Lau (F’94) received three M.S. degreesin structural engineering, engineering physics, andmanagement science. He received the Ph.D. degreein theoretical and applied mechanics from theUniversity of Illinois, Urbana-Champaign.

After more than 20 years as a Senior Scientistand MTS at Hewlett-Packard (HP) and Agilent inCalifornia, he became Director of the Microsystems,Modules, and Components Laboratory, Instituteof Microelectronics, Singapore, for two years, andhas been a Visiting Professor with Hong Kong

University Science and Technology since 2009. With more than 30 years ofR&D and manufacturing experience, he has authored or coauthored more than300 peer-reviewed technical publications and more than 100 book chapters,and given more than 250 presentations. He has authored and coauthored16 textbooks on advanced packaging, solder joint reliability, and lead-freesoldering and manufacturing.

Dr. Lau is an elected ASME Fellow.

Xiaowu Zhang received the Ph.D. degree in mechan-ical engineering from Hong Kong University of Sci-ence and Technology (HKUST).

Currently, he is a Principal Investigator (PI) withInstitute of Microelectronics (IME), A*STAR, Sin-gapore. His research activities cover advanced pack-aging development and 3-D IC integration. He hasauthored or co-authored more than 80 technical pa-pers in refereed journals and conference proceedings.

Dr. Zhang is the recipient of the 2001 JEP BestPaper Award conferred by ASME Transactions:

Journal of Electronic Packaging, and the 2004 Best Industry Support TeamAward conferred by IME. He is listed in Who’s Who in the World (2006).

Kripesh Vaidyanathan received the M.S. degree inphysics from University of Madras, India, in 1987,and the Ph.D. degree in the area of thick and thinfilm passives for microelectronics modules from theMax-Planck Institute for Metalforschung, Stuttgart,Germany, in 1995.

He has 20 years research experience in the area ofadvanced packaging. He was a Visiting Scientist atInfineon Technologies, Corporate Research, Munich,Germany, in the area of 3-D-integrated circuits. SinceMarch 2000, he has been with the Institute of Micro-

electronics, Singapore, heading a group of researchers in area of 3-D TSV inte-gration and wafer level packaging process. He has authored more than 60 journaland conference publications and holds 18 patents to his credit. His research in-terests are 3-D-silicon stacked modules, Cu/Low-k packaging, and wafer levelpackaging.

T. C. Chai is a Member of Technical Staff in theMicrosystems, Modules, and Components Lab,Institute of Microelectronics, Singapore. He hasworked on area of packaging development, relia-bility, and failure analysis for 18 years. Recently hisfocus has been flip chip packaging for Cu low K chipand TSV technology.


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