Via First Approach Optimization for Through Silicon Via...

Via First Approach Optimisation for Through Silicon Via Applications

Cyrille Laviron1 ; Brendan Dunne2 ; Valérie Lapras1 ; Paola Galbiati2 ; David Henry1 ; Fabrizio Toia2 ; Stéphane Moreau1; Romain Anciant1 ; Cahty Brunet-Manquat1 ; Nicolas Sillon1

1 CEA, LETI, MINATEC, F38054 Grenoble, France 2 STMicroelectronics, Via C.Olivetti 2, 20041 Agrate Brianza (MI), Italy

Abstract Through Silicon Via (TSV) is a very attractive solution for

3D stacking. Currently the main technique in industrial TSV processes is the via-last approach. But the via-first approach has also many advantages and in particular allows the use of high thermal budget materials for high voltage applications.

In this work, we will show results on process development and integration of 100µm deep annular TSVs in thick Silicon On Insulator (SOI) or on bulk substrate, with final validation through electrical characterizations. First the complete process will be presented for both approaches. Then, process development work and issues will be addressed. A special focus will be done on etching in the SOI case. A 3-step Deep Reactive Ion Etch (DRIE) was developed, as the BOX etch profile can induce some undercut leading to voids during the via filling step. The via sidewall isolation is discussed, with comparisons of different materials, including thermal oxide and High Temperature Oxide (HTO) or even a mix of these oxides. Results will be presented including breakdown field and thickness conformity on via side walls.

Filling with highly doped poly silicon is compared to tungsten. Chemical Mechanical Polishing (CMP) is then used to planarize the surface to optimize the surface topology for the subsequent semiconductor process. The backside process is also discussed, from the point of view of the optimization of the thinning, stress release and surface finishing techniques to facilitate the backside contact and metallization processes.

All the process steps are optimized to achieve a TSV with the best shape to minimize weak points for leakage and breakdown voltage to be able to handle high voltages in the region of 200V. Simulation is also used to study the relative impact of different local TSV profiles on the final electric field and then optimize the process.

Then electrical characterizations will be presented. A specific test vehicle was designed to study the TSV density and proximity impact, number of rings and ring width. Daisy chains, specific structures to measure TSV resistance similar to Kelvin structures, interdigitated chains to measure via leakage, and special structures to stress at very high voltage (up to 1000V), were designed. The electrical results from those specific structures will be discussed.

Finally, future developments will be discussed, in particular the integration of these TSVs in a real high-voltage semiconductor process.

Introduction Miniaturization has been the driving force in

microelectronics for years, but mainly focused in the transistor area and integration of heterogeneous components

on the same chip (SoC). Stacking devices is another method to improve the density, simplify heterogeneous integration and reduce costs. Through Silicon Vias (TSV) or through wafer interconnection is most likely the solution to go to 3D device stacking [1]. Many integration schemes have been proposed, but no single solution has emerged as yet. The choice of via-first or via-last, the filling material (polysilicon, tungsten or copper), etc., will depend on the constraints of the final product [1-3]. The first applications to reach this milestone were CMOS Image Sensor (CIS) and memories with copper via-last technology.

In the via-first approach, the TSV is formed on the device side of the wafer before the bonding and thinning processes. The TSV brick can be introduced in the device flow either at the beginning, implying no limitation on the thermal budget but with Front End of the Line (FEOL) compatible material only; or during the Back End of the Line (BEOL) operations but with thermal budget limitation mainly due to dopant previously implanted which are very sensitive to annealing diffusion.

Via first highly doped polysilicon offers the ability to integrate the TSV at the very beginning of the device fabrication, the polysilicon allowing the use of high thermal budgets. This can be a major advantage in the case of high voltage application since it allows the use of thermal oxide as isolating material. As low resistivity for the material used for TSV filling is one of the key points, other materials are of interest such as tungsten which can also be used for via first approach, but at the BEOL operation.

To allow compatibility with semiconductor fab process, the size of the via has to be reduced as much as possible for a shorter filling process. The annular shape of the vias has already been shown to be a good compromise to achieve low resistance while remaining compatible with FEOL process [4]. Therefore the aspect ratio (AR) of the TSV is strongly increased from values of 1/2 to up to 30/40 to keep 50 to 100µm deep vias. Bosch etch process on Deep Reactive Ion Etching (DRIE) is commonly used for years. In this work, we show special development of this kind of process on thick SOI used for high voltage.

One other benefit of the via-first approach is that the TSV brick does not impact the post process flow as the via is fully filled and planarised. Using classic processes like Chemical Mechanical Polishing (CMP) allows finalizing of the TSV brick and results in a planar surface.

Via first TSV process In previous work [5] the annular TSV was demonstrated

as an interesting compromise between electrical conductivity, high aspect ratio (AR) and complete filling. Here we used a

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specially designed test vehicle with annular TSV of different features; 2 rings and 3 rings with varying ring thickness. Since one of the main objectives of this work is high voltage compatibility we also investigated the use of the external ring as a sacrificial one to improve the isolation..

This via first TSV process is introduced near the beginning of the High voltage device process flow. That can be done at the beginning of the process, or alternatively after the trench isolation and planarisation steps.

Silicon On Insulator (SOI) substrate has been used to realise a TSV process using substrate thinning stopping in the Buried Oxide (BOX) [6]. But in some high voltage applications, the use of SOI is mandatory and so the continuation of the TSV etch through the BOX and into the substrate is necessary.

The first specificity was the DRIE in SOI. Hard mask, sacrificial oxide, nitride or ONO layer can be present on top of SOI depending on where the TSV block is integrated in the process. Following this top layer etching, there are three successive etch processes. Each process was independently optimized to achieve the best overall via profile (see figure 1). The requirement is to have a regular tapered profile allowing a good filling in the next stages and to minimize indents or undercuts leading to reduced breakdown.

Figure 1: SEM cross section of TSVs 2 rings 5µm

The first etch step is the top 7µm SOI layer. A classic Bosch etch process was initially used on a STS DRIE equipment. However, as the aspect ratio was not too high for this first etch step, a non Bosch process was then investigated to avoid scalloping.

The second step is to etch the 1µm thick buried oxide (BOX). Optimization was done to obtain a slight slope and to minimize as much as possible the undercut.

The main DRIE step is to etch silicon about 60µm to 90µm under the BOX. Here an optimized Bosch process was used. Very good uniformity was achieved within a wafer with less than 2% depth variation between wafer centre and wafer edge. The effect of the TSV density was also studied. The test mask used contains areas where the TSVs are completely isolated as well as very dense arrays where the open area can

be as high as 20%. The optimized Bosch process gives the same result in depth and shape in dense or isolated areas.

The via slope can be tuned with etching parameters. The compromise is to have a minimal slope for easier polysilicon filling but at the same time to maintain a good CD at the via bottom so as to optimize the TSV resistance.. A good value of 0.5° was achieved (see figure 2.a).

b) Unoptimized overetch under the BOX

a) 0.5° slope c) Optimized etch around the BOX Figure 2: SEM cross section details

Another issue is the shape of the via at the interface

between the BOX and the silicon substrate. An undercut can appear in this area leading to a void in the polysilicon filling and so a potential reliability issue. In figure 2.b to figure 2.c we show that optimizing the first passivation steps of the Bosch process can strongly improve the final shape and we can obtain a profile without undercut.

Scalloping on the sidewall of the via is also of importance and should be reduced as much as possible, while at the same time keeping a reasonable etch time. The scalloping size diminishes with the depth of the TSV, therefore it is at the top of the via where it is most consequent.

An axi-symmetric structure simulation with ANSYS code was used to analyze the relative impact of BOX undercut depth and scalloping influence (figure 3.a) on the electric field in the case of high voltage. The undercut is the result of TSV etch, post etch cleaning and insulator layer deposition (figure 3.b). It can lead to a void in post polysilicon filing but also it increases locally the electrical field when a voltage is applied. This electric field increases due to the local reduction in insulating layer thickness and also to the electric field

SOI

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15 2009 Electronic Components and Technology Conference


concentration effect at the corner of the SOI or the silicon substrate (figure 3.c).

a) Model b) SEM of indent in BOX

c) Electric field simulated with a strong undercut

Figure 3: Simulation model and result in the TSV

Breakdown voltage of thermal oxide currently used in the literature is about 6 to 10MV/cm [7]. The undercut of 0.8µm in the BOX leads to an electric field of 10MV/cm at 200V and will then reach the breakdown as it can be seen in figure 4.a. Reducing this indent is mandatory for high voltage application and was done changing the TSV etch process and also the post etch cleaning.

Scalloping shape was also simulated: from ideal case of smooth sidewall to a realistic circular-shaped scalloping of 80nm depth, and even a worst-case elliptical-shaped scalloping where this footprint is doubled. The impact is less pronounced than the undercut but can however have a significant influence on the local electric field (figure 4.b).

1µm steam thermal oxide was then grown in a LPCVD furnace tool as the insulating material. Very good conformity was obtained with more than 90% of the top thickness measured at the TSV bottom, even with high AR up to 40. Nevertheless, one potential difficulty is the coverage on BOX profile which tends to be indented with the use of thermal oxide. In order to achieve a smoother profile a deposited oxide can be envisaged, such as High Temperature Oxide (HTO) but with lower conformity. The compromise is between the low growth of thermal oxide in BOX region for the first and inferior insulating properties and conformity for the second. Full sheet characterization of HTO gives a breakdown voltage field of about 7.5MV/cm which is 25% less than thermal oxide. The breakdown field depends on the kind of HTO and can be also improved with a DCS HTO [8].

y = 330 e1.3954x

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Figure 4: Simulation of the undercut and scalloping impact on electric field in the TSV

Phosphorus highly-doped polysilicon was then deposited

in LPCVD equipment. The previously developed multi step filling was applied and no void was achieved when the indent in the BOX was minimized. In this case doped polysilicon is used for the via fill due to the very high subsequent thermal budget of the high-voltage SOI processes. Final planarisation was done with a Chemical Mechanical Polishing (CMP) step leaving a relatively good surface topography (figure 4.b) with less than 50nm height range in the TSV. This allows us to fabricate the high voltage device flow without any impact due to surface topography.

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a) SEM cross section b) Profilometry Figure 5: Post TSV planarisation

Another possibility is to implement the TSV block at the

end of the FEOL device process and then to replace polysilicon conductive material with tungsten (W). This can be done for normal bulk silicon in the case of another application than high voltage, but also for high voltage with HTO or SACVD isolation. Tungsten has the advantage of

V/µm

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strongly reducing the resistance of the TSV as the conductivity is about one order of magnitude smaller. The main issue is the filling process due to the very high stress of CVD W deposition when a conformal layer is needed.

Following these TSV-specific process steps, classical integration processes can be done for the complete device fabrication. In the results shown here, only metal interconnections were realized on front side.

Then, bonding and back lapping was done to thin the wafer to uncover the TSVs (figure 6).

a) top view in dense area b) Phase Shift Interferometry

Figure 6: Back side views after thinning and TSV opening

Wafer grinding followed by CMP finishing results in a

surface topology of less than 100nm (figure 6.b) Alignment marks used during back side post process from

contact to Redistribution Layer (RdL) level, were realized with TSV process and are therefore transferred from front side to back side at the same time as the TSVs.

Electrical Results A specific test vehicle was designed to characterize all the

different process steps and to allow the choice of the optimum TSV design.

Kelvin structures were used to measure precisely the final TSV resistance. Daisy chains give an overview of the number of functional TSVs. Chains from 8 to 400 TSVs were measured without any failure whatever; the design used can be seen on figure 7.a.

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Increasing the number of rings and the ring width

significantly reduces the TSV resistance (figure 7.b) without

impacting the pitch which was kept identical for all the different TSV design.

Interdigitated chains with more than 250 TSVs per chain were also designed to check the leakage (figure 8). This structure amplifies the leakage between TSVs.

TSVs were designed with or without sacrificial external ring. In the case of the use of this sacrificial ring, no leakage between the 2 TSVs chains was measurable whatever the TSV design.

Figure 8: Interdigitated structure The high insulation capability is a key point for these

TSVs as they should be used in high voltage applications. Therefore a special structure allowing application of very high voltages, up to 1MV, were used to check I(V) characteristics to look at breakdown voltage capability and fine leakage analysis.

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Série48 Figure 9: I(V) between 2 TSV 3rings/5µm measured on several dies with thermal oxide as insulator without sacrificial ring.

I(V) characteristics of all the die of a wafer are very

similar with a dispersion in breakdown voltage value determined for a current higher than 10µA. As it can be seen in figure 9, the breakdown voltage between 2 TSVs of 3 rings and 5µm without sacrificial ring has a mean value of 755V but with a minimal value of 550V.The insulating material in this case is a 1µm thick thermal oxide. The mean leakage is about 1nA at 400V and 10nA for 530V. This quite good result is showing that the pre-process TSV filled with doped polysilicon is compatible with high voltage applications. Very good alignment between back side contact and TSV is



mandatory to avoid overlap of the contact with the bulk substrate leading to TSV leakage. This is more pronounced if there is no sacrificial ring used for this back side contact.

This insulation can be improved with different process or design optimization. The TSV design with the number of rings or the width of the ring will not change the insulation characteristics (figure 10).

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Figure 10: I(V) for different design TSV without sacrificial ring with thermal and HTO mixed oxides

But using the external ring as a sacrificial one will

strongly improves the leakage and breakdown voltage results. The insulation is then an accumulation of the 2 oxide layers on the side wall of the external ring. In the case of 2 TSV of 2 rings and 5 µm on figure 11, and whatever the insulating material used, the breakdown voltage is higher than 1000V. A leakage of less than 5nA is reached at 1000V.

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Figure 11: I(V) comparison between 2 TSVs 2rings / 5µm with different insulator and with or without sacrificial ring

Further improvements can be also made with process

optimization by varying isolation thickness or material. Three different combinations are compared here with the same total thickness of 1µm. The thermal oxide already discussed is compared with HTO or a mix of 500nm thermal oxide and 500nm HTO (figure 12).

From thermal oxide to HTO the leakage at low voltage below 500V is improved of about a factor of 5 due to a better interface charge trapping effect [9]. But the breakdown voltage is lower probably due to a poorer conformity of the

HTO compared to the thermal oxide, and so a thinner oxide at the bottom of the TSV.

Taking advantage of both oxides, a mix of 500nm thermal oxide followed by a 500nm HTO deposition was tested. Very good results of leakage of 1nA at 400V and 10nA at 680V were achieved between TSV and substrate. The leakage slope is similar to the one with thermal oxide but half a decade below. Thermal oxide and HTO have different composition and the breakdown occurs for voltage even higher than 800V in that case.

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Figure 12: I(V) comparison between different insulator material measured between TSV (3 rings of 5 µm with sacrificial) and substrate. Thickness is 1µm for all of them.

Other ways are also possible to improve the insulation capability in both directions of breakdown value but also for leakage at medium voltage. Increasing thicknesses of the material is one of these possibilities. On another hand, it is possible to work on the material replacing thermal oxide or mixing thermal oxide with another oxide or a nitride layer. Nitride film like ONO used currently in memory applications has already proven of some interest [10] and can be easily envisaged in this case.

Conclusions TSVs with high aspect ratio in thick SOI with doped poly-

silicon filling were demonstrated. Some development of the Bosch etch process was necessary to achieve a good shape of the vias. This optimization is mandatory as the high voltage application in the 200V range leads to potential high local electric field. Very good polysilicon filling was achieved without any voids, and final planrisation leads to less than 50nm topography, showing very good compatibility with FEOL high voltage device process. Electrical characterizations at high voltage showed that higher than 600V breakdown voltage is achieved with thermal oxide insulating material. and up to 800V is reached with a combination of oxide types. Other combination possibilities are to be envisaged, including the use of a nitride layer.

References 1. Knickerbocker J. et al, “3D Silicon Integration”, Proc 58th

Electronic Components and Technology Conf, Lake Buena Vista, FL, May 2008, pp. 538 - 543.



2. Henry D. et al, “High aspect ratio via first for advanced packaging”, Proc 9th Electronics Packaging Technology Con,f, Singapore, Dec. 2007, pp. 215 - 221.

3. Kikuchi H. et al, “Tungsten through silicon via technology for Three-Dimensional LSIs”, Jpn. J. Appl. Phys. Vol. 47, No. 4 (2008), pp. 2801 - 2806.

4. Pozder S. et al, “Progress of 3D Integration Technologies and 3D Interconnects”, Proc.10th International Interconnect Technology Conf, Burlingame, CA, Jun. 2007, pp. 213 - 215.

5. Henry D. et al, “Via First Technology Development Based on High Aspect Ratio Trenches Filled with Doped Polysilicon”, Proc 57th Electronic Components and Technology Conf , Reno, NV, May 2007, pp. 830 – 835.

6. Guarini K. et al, “Electrical integrity of State of the Art 0.13µm SOI CMOS devices and circuits transferred for 3D IC”, Electron Devices Meeting IEDM '02. Digest. International, San Francisco, CA, Dec. 2002, pp. 943 -945.

7. Sze S. et al, Physics of Semiconductor Devices, Wiley Interscience (2006), pp. 230 - 238.

8. Clavelier et al, “Deep trench isolation for 600V SOI power devices”, Proc.33th European Solid-State Device Research Conf , Estoril, Portugal, Sept. 2003, pp. 497 - 500.

9. Raskin Y. et al, “Reliability of HTO based high-voltage gate stacks for flash memories”, Microelec. Reliab. Vol 47 (2007), pp.615 – 618.

10. Ohji Y. et al, “Reliability of nano-meter thick multi-layer dielectric films on poly-crystalline silicon”, Proc. 25th Reliability Phys. Symp., San Diego, CA, April 1987, pp. 55 – 59.



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