IBM Systems and Technology Group © 2010 IBM Corporation Challenges in Robust Optimization of...

IBM Systems and Technology Group

© 2010 IBM Corporation

Challenges in RobustOptimization of DigitalIntegrated Circuits

Chandu VisweswariahSystems and Technology GroupIBM


© 2010 IBM Corporation2 of 41 Chandu Visweswariah Challenges in Robust Optimization of Digital Integrated Circuits

Outline

The scourge of manufacturing variability!

Two ways of dealing with variability in timing

– Multi-corner static timing analysis

– Statistical static timing analysis

Continuous robust optimization: the state-of-the-art

Discrete robust optimization: the state-of-the-art

Open challenges

Ana

lysi

sO

ptim

izat

ion



Increasing and inevitable parametric variability

*D. J. Frank et al, Symp. VLSI Tech., 1999

Litho-induced variability Random dopant effects* Oxide thickness

Interconnect CMP and RIE effects



What variability does to performanceP

erfo

rman

ce

Technology generation

Unacceptable!

Shrink by- Statistical timing- Stochastic optimization- Design-for-manufacturing (DFM) techniques- Post-silicon tuning

Best Case

Worst Case



Classification of variability

Variability

Chip-to-chip,wafer-to-wafer,

lot-to-lot,fab.-to-fab.

Within chip

RandomSystematic Systematic Random

“Best case” / “Worst case” “Early” / “Late”



Modeling of variability

Mean Ring Oscillator Delay

Indi

vidu

al R

ing

Osc

illat

or D

elay

Chip-to-chip variation

Within-chip “systematic” variationWC early

BC late

WC late

BC early



Outline

The scourge of variability!






Open challenges



(Deterministic) static timing analysis in its simplest form*

Simple one-pass traversal helps us find the longest and shortest paths in the timing graph

One backward traversal is used to compute Required Arrival Times (RATs)

a

b

z

*R. B. Hitchcock Sr., G. L. Smith, D. D. Cheng, “Timing analysis of computer hardware,” IBM J. R&D, January 1982, pp. 100—105.

a

b

z

Node forevery pin

Arc for every

pin-to-pin transition



Verifying timing of setup tests

LF1 LF2 CFLF3 Comb.

Comb.

Comb.

late data

early clock

Robustness = Correlated variability in launch and capture paths



Verifying timing of hold tests

LF1 LF2 CFLF3 Comb.

Comb.

Comb.

early data

late clock



Multi-corner timing

Chip-to-chip variation covered with multiple corners + margins

Within chip systematic covered by early/late split

ProcessVoltage

Tem

pera

ture



Outline







Open challenges



Quick introduction to statistical timing

Deterministic

Statistical

a

b

c+

+ MAX

b

a

c+

+ MAX



Parameterized timing quantities*

All timing quantities are parameterized by the sources of variation

Correlation can be judged on-demand by inspection

*C. Visweswariah, K. Ravindran, K. Kalafala, “First-order parameterized block-based statistical timing analysis,”TAU, February 2004, pp. 17—24

*C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, S. Narayan, “First-order incremental block-based statisticaltiming analysis,” DAC, June 2004, pp. 331—336.

annn RaXaXaXaa 122110

Constant(nominal

value)

Independentlyrandom

uncertainty

Sensitivities Deviation ofglobal sources

of variation fromnominal values



Statistical timing basics

Model all arc delays in “canonical” parameterized form

Represent all timing quantities in parameterized form

– Delays, slews, guard times, ATs, RATs, slacks, PLL adjusts, constraints, CPPR adjusts

Propagate ATs through the timing graph in canonical form

Final timing results are available in canonical form

– Automatically obtain sensitivity to sources of variation; taming these sensitivities improves robustness

– Can project to single values (see next page)

– Can plot as PDFs, CDFs, yield curves



Sample projections



Comparing multi-corner and statistical timing

Multi-corner Statistical

Chip-to-chip variation Multiple single corner timing runs

Single parameterized timing run

Within-chip systematic variation

Early/late split Early/late split + independently random component

Independently random variation

Alphabet OCV algorithms

Straightforward handling

Margins/pessimism More Less

Robustness checking Not possible Natural – see next page

Optimization Whack-a-mole? Subject of the rest of the talk



Robustness checking

Timing tests in this blue cube are fails

Sensitivity threshold

Slack threshold



Outline







Open challenges



Deterministic transistor sizing problem “Analysis is done by devils, optimization by angels”

Typically applied to custom-designed circuits

1AT

2AT

15d

25d

3AT

4AT

36d

46d

57d

68d

58d 67d

5AT

6AT

7AT

8AT

Note that z and the ATs are variables of the optimization problem

are computed by adjoint sensitivity analysis in the time-domain



Statistical transistor sizing problem

The problem formulation is cleaner and easier (eliminates redundancies and degeneracies)!

This is because the (approximate) statistical max function is differentiable!

The big question is how to compute

1AT

2AT

15d

25d

3AT

4AT

36d

46d

57d

68d

58d 67d

5AT

6AT

7AT

8AT

By adjoints, as before



Gradient computation*

jiijd

Imaginary cutset

*J. Xiong, V. Zolotov, C. Visweswariah, “Incremental criticality and yield gradients,” Design Automation and Test in Europe (DATE),

Messe Munich, Germany, pages 1130--1135, March 2008.



Results (maximize minimum of 4 slacks)*

*D. K. Beece, J. Xiong, C. Visweswariah, V. Zolotov, Y. Liu, “Transistor sizing of custom high-performance digital circuits with parametric yield considerations,” Design Automation Conference (DAC), Anaheim, CA, June 2010.



Outline







Open challenges



The discrete optimization problem

Physical synthesis is used to construct most macros/units

– Made up of library cells of various logic types and sizes (unlike in custom design)

– Can handle large chunks of logic

– Fully automated

– Highly productive way of designing

Physical synthesis operates in a huge discrete space and carries the design from logic to shapes

– “Changes” or “transforms” are applied on a list of gates/wires that have poor timing

– The changes are evaluated by invoking the timer in an incremental manner



Synthesis transforms

Buffering or repeater insertion

Layer assignment

Gate sizing or repowering

Vt swapping

Cell movement

Inverter absorption / inverter decomposition

Cloning

Inverter / buffer deletion

Composition / decomposition

Courtesy: Chuck Alpert



Buffering long nets




Buffering a net to reduce fanout (before)




Buffering a net to reduce fanout (after)




Layer assignment

b f

eca d

b f

eca d




Gate sizing or repowering

b f

eca d

b f

eca d




Vt swapping

b f

eca d

b f

eca d

High vt

Regular vt

Low vt




Cell movement

b f

eca d

b f

eca d




Inverter absorption / decomposition

b f

eca d

bf

ea g




Cloning

S1D1

D2 S2

D1

D2

S1

S2

P P

P’

Courtesy: Zhuo Li / David Papa



Composition / decomposition

nd2 A

nd2 C

nd2 B

D

Outx

y

z

w

nd2 C

D

y

z

x

w

Out

AOI

Courtesy: Louise Trevillyan



Variability-related challenges

Variability is handled by

– A multi-corner static timer, or

– A statistical static timer

This makes sign-off timing expensive!

Physical synthesis methods are not equipped to handle statistics

Of all the “changes” tried, only ~10% get accepted

Either

– Use a fast/approximate timing mode and periodically update with sign-off timing

– Work with sign-off timing but invoke incremental timing less often



Food for thought

This is an important optimization problem where heuristics rule and mathematical techniques have failed!

Heuristics are used to decide

– Which parts of the design to optimize

– Which optimizations to apply

– In what order to apply these optimizations

– When to accept uphill moves (if at all)

– When to undo previously accepted moves (if at all)

– When to stop or try something else



Some thoughts

Diagnostics that can be used to reduce the number of failed tries and/or “tune” heuristics

– Process sensitivities• Try different changes depending on the ordering of sensitivities, the

way a human would, for example:

– Slew (rise/fall time) information

– Fanout information

– Logic complexity information

Sensitivity Action

Metal Buffering

Single metal layer Layer assignment

Npskew Logic re-optimization



Outline







Open challenges



Open challenge

Plenty of progress on analysis with uncertainty

Recent work on continuous optimization in the face of variability

– Could also be formulated as a 2-stage optimization to take into account post-manufacturing tuning

Challenge: How do we optimize large integrated circuits in a HUGE, discrete, multi-dimensional, highly constrained optimization space while triggering the incremental (statistical or multi-corner) timer as little as possible

IBM Systems and Technology Group © 2010 IBM Corporation Challenges in Robust Optimization of...

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