Microelectronics Reliability 54 (2014) 374–380

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Microelectronics Reliability

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High temperature bias-stress-induced instability in power trench-gatedMOSFETs

0026-2714/$ - see front matter � 2013 Elsevier Ltd. All rights reserved.http://dx.doi.org/10.1016/j.microrel.2013.10.004

⇑ Corresponding author at: Department of Engineering Science and Mechanics,The Pennsylvania State University, University Park, PA 16802, United States. Tel.: +18148631773.

E-mail address: ooaesm@engr.psu.edu (O.O. Awadelkarim).

J. Hao a, M. Rioux a, S.A. Suliman b, O.O. Awadelkarim b,c,d,⇑a Fairchild Semiconductor, Inc., 82 Running Hill Road, South Portland, ME 04106, United Statesb Department of Engineering Science and Mechanics, The Pennsylvania State University, University Park, PA 16802, United Statesc The Center for Nanotechnology Education and Utilization (CNEU), The Pennsylvania State University, University Park, PA 16802, United Statesd The NSF Nanotechnology Applications and Career Knowledge (NACK) Network, The Pennsylvania State University, University Park, PA 16802, United States

a r t i c l e i n f o a b s t r a c t

Article history:Received 13 August 2013Received in revised form 2 October 2013Accepted 3 October 2013Available online 6 November 2013

We report on the high-temperature reverse-bias (HTRB) stress reliability of trench-gated n-channelmetal-oxide-silicon field-effect transistors (n-UMOSFETs). The degradation induced by the HTRB isexamined using changes in transistor parameters, optical microscopy, and scanning electron microscopy.The HTRB causes degradations in the threshold voltage and drain leakage of the n-UMOSFET and thesedegradations are particularly large when the stress is applied in a humid ambient. The observations wereinterpreted in terms of water molecule diffusion into the gate oxide through passivation cracks in theedge termination of the n-UMOSFET during HTRB in a humid ambient. The water molecules catalyzeproton (H+) generation through electric-field assisted interactions and hole injection into the gate oxideat the bottom of the trench. Also, H+ is observed to be very stable in the gate oxide and to migratebetween the gate-oxide and oxide–Si interfaces driven by an applied gate-voltage. It is proposed thatthe employed HTRB configuration and level give rise to negative-bias temperature instability (NBTI) ina parasitic p-channel MOSFET structure occurring in the trench base of the n-UMOSFET, and that NBTIis a serious reliability concern in power UMOSFETs subjected to stress in a moist ambient.

� 2013 Elsevier Ltd. All rights reserved.

1. Introduction

With the rapid growth of portable computing and automotiveelectronics industry [1], the demand for high efficiency powerswitches for power management has increased many fold. For suchswitching power applications, metal-oxide-silicon field-effect tran-sistors (MOSFETs) are attractive since, in unipolar devices, there isless storage and recombination of minority carriers and a highswitching speed may be obtained [2]. Excellent thermal stabilityand high input impedance have also contributed to powerMOSFET’s popularity. With the emphasis on low power dissipation,it is imperative to achieve a low specific on-resistance, defined asthe on-resistance multiplied by the active area, to minimize con-duction power losses. In recent years, significant progress has beenmade in power MOSFET technology. Using trench gate technologythe most advanced low-voltage power devices, namely U-shapedtrench-gated MOSFETs (UMOSFETs), are realized. The introductionof trench-etch and the employment of side-wall channel toincrease channel area for an overall silicon area have produceddrastic reduction in the specific on-resistance of UMOSFETs [3,4].

Also, the UMOSFET structure results in elimination of the junctionfield-effect transistor resistance in power MOSFETs [2].

While a number of papers have been published in the literature,reporting UMOSFETs with low specific on-resistance, the aspect ofreliability of UMOSFETs is often overlooked. As the UMOSFET’sdimensions shrink and its applications are diversified, studies ofUMOSFET’s reliability are becoming increasingly important. High-temperature reverse-bias (HTRB) stress is often used in reliabilityassessment of planar discrete power MOSFETs [5,6] and is cur-rently used in studying degradation effects in UMOSFETs.

In this report, we address the effects of accelerated aging in-duced in n-channel UMOSFETs (n-UMOSFETs) by HTRB stress.The HTRB is applied at elevated temperatures in a dry ambientor a humid ambient and configured in a way that enables theassessment of stress-induced increases in the drain side junctionleakage and leakage in the die edge termination. The stress is ob-served to increase interface trap density when applied in dry or hu-mid ambient. However humid HTRB stress is observed to furtherintroduce mobile positive charge in the gate oxide of the UMOSFET.This positive charge is argued to comprise protons (H+s). Themobility of these protons is observed to cause gate-voltage inducedmodulation in the threshold voltage and leakage current of theUMOSFET. It is concluded that we are observing negative-biastemperature instabilities (NBTI) in a parasitic p-channel MOSFET(p-MOSFET) occurring in the n-UMOSFET during HTRB. This work

J. Hao et al. / Microelectronics Reliability 54 (2014) 374–380 375

demonstrates that NBTI is a reliability concern in powerUMOSFETs, especially when stressed in a humid ambient.

2. Experimental procedure

The studies reported in this article were performed on espe-cially designed n- UMOSFETs schematically shown in Fig. 1.Fig. 1a is a schematic diagram of the n-UMOSFET. The n-UMOSFETfabrication sequence was based on approaches for the fabricationof low on-state resistance vertical trench MOSFET devicespreviously reported in the literature [7,8]. First, an n-type layerwas epitaxially grown on a heavily doped (>1019 cm�3) n-type sub-strate. Boron implantation and drive in were performed to producea p-well with an average acceptor concentration of approximately1017 cm�3 appropriate for the channel. 0.5-lm wide U trencheswere subsequently anisotropically plasma etched in a commer-cially available reactive-ion-etching (RIE) tool. Following thetrench etch a nominally 160-Å gate oxide was thermally grownin dry O2 on the trench sidewalls and bottom. Polycrystallinesilicon (poly) was then deposited and in situ-doped with phospho-rus to fill the trenches, then etched back to remove the poly on thetop surface leaving it only in the trenches. The source regions werethen formed using phosphorus implantation and drive-in resultingin a nominal channel length of �1 lm. The devices were packagedby using state-of-the-art ‘‘low pitch’’ wafer-level-chip-scale pack-age (WLCSP) process, without the use of mold compound or leadsframe. Fig. 1b shows a schematic of the Sn3.8Ag1.0Cu solder ball, a

(a)

(b)

Fig. 1. (a) Cross section of the n-UMOSFET test structure used in this study (not toscale) and (b) a schematic of the solder ball and the different material layers used inthe WLCSP process.

1 lm-thick passivation layer (comprising a 0.5 lm-thick SiO2 and0.5 lm-thick SiOxN layers), a 5 lm-thick Fuji AP2210A polyimide(PI) layer, a 5.0 lm-thick E-Nickel/Au layer (ENIG), and a 2.5–5.0 lm-thick Al layer.

Following device fabrication, accelerated aging by HTRB stresswas carried out and device properties were measured before andafter the application of the HTRB stress. The HTRB stress was ap-plied in either a dry-ambient at 150 �C for a duration of 168 h, ora humid-ambient at 130 �C for a duration of 96 h. The HTRB wasapplied in the blocking (cut-off) mode with the source, body andgate all grounded and a voltage of +20 V applied to the drain ofthe n-UMOSFET. This drain voltage is below the breakdown voltage(BV) for the UMOSFET, which is determined to be 24 V at the nAcurrent levels. This type of HTRB applied voltage configuration isusually employed to study the drain pn-junction leakage in theUMOSFET. The threshold voltage Vth, drain-to-source leakage cur-rent, IDSS, drain-to-source blocking voltage or BV, and the gateoxide leakage were measured at room temperature before andafter stress. The measured sample sizes for the humid HTRB andthe dry HTRB stresses were 45 and 77 devices, respectively. Allmeasurements were carried out in the dark at room temperaturein a micromanipulator and using a HP4156A setup.

3. Results and discussion

3.1. Effects of HTRB on UMOSFET’s parameters

Fig. 2 shows the effect of the wet HTRB on the drain current (Ids)as a function of the gate-to-source voltage (Vgs) taken at room tem-perature and at a drain-to-source voltage (Vds) of 0.1 V. Vth in theUMOSFET is observed to decrease from �0.6 V to �0.2 V uponthe application of the wet HTRB. Fig. 3 shows that this decreasein Vth is accompanied by more than a three orders increase in thedrain-to-source leakage current (IDSS) measured at room tempera-ture as a function of Vds for a Vgs = 0 V. However the interestingobservation shown in Fig. 2 is the recovery of Vth by a negative gatebias of Vg = �1 V applied at room temperature to the n-UMOSFETwith grounded drain, source, and body: Vth increases with negativebias approaching its pre-HTRB value. This is seen in Fig. 2 as Vth

recovery is enhanced by the duration of the negative bias over timeperiods between 100 s and 1000 s. Moreover Vth recovery is re-versed as the polarity of the gate voltage is reversed to Vg = +1 Vapplied at room temperature with grounded drain, source, andbody. This is seen in Fig. 4, which shows Ids versus Vgs forVds = 0.1 V, where Vth decreases with increased duration of the

Fig. 2. The effects of the wet HTRB on the drain current (Ids) as function of the gate-to-source voltage (Vgs) taken at room temperature and at a drain-to-source voltage(Vds) of 0.1 V. The figure shows shifts in Vth after humid HTRB and a �1 V appliedgate bias (cycle voltage) for the time interval indicated.

Fig. 3. The effects of the wet HTRB on the drain leakage current (IDSS) as function ofthe drain voltage (Vds) taken at room temperature and at a gate-to-source voltage(Vgs) of 0 V. The figure shows the IDSS shifts after humid HTRB and �1 V and +1 V(cycle voltage) applied to the gate for the indicated time interval.

Fig. 4. The figure shows Vth measured on a fresh UMOSFET prior to the applicationof HTRB and after the application of humid HTRBT followed by a +1 V (cycle voltage)applied to the gate for the time interval indicated.

Fig. 5. The solid diamond symbols show shifts in Vth, DVth, with time after a 2000-spositive-polarity (Vgs = +1 V) cycle voltage is applied to the humid-HTRB-stressedUMOSFET. The solid triangle symbols show the recovery (positive shift or increasein Vth), in the absence of any applied gate voltage, as a function of time in theUMOSFET following Vth degradation by the negative-polarity (Vgs = �1 V) cyclevoltage. The vertical axis in the figure shows the absolute values of DVth.

376 J. Hao et al. / Microelectronics Reliability 54 (2014) 374–380

applied positive gate voltage. These same recovery and degrada-tion effects on Vth occur in IDSS as shown in Fig. 3, where IDSS de-creases with a negative-polarity applied gate voltage andincreases with positive-polarity applied gate voltage.

In summary the humid HTRB degrades the n-UMOSFETs and thepost-HTRB device performance is ‘‘cycled’’ between degradationand recovery by the application of a room-temperature small volt-age gate-bias, Vg, which we will hereafter refer to as the ‘‘cycle volt-age’’. The polarity of the cycle voltage determines the direction ofVth shift in the n-UMOSFET, which recovers for a negative cyclevoltage and degrades (Vth decreases) for a positive cycle voltage.In contrast, most of the n-UMOSFETs that were HTRB stressed ina dry ambient showed no degradation and only a small numberof these devices exhibited very little degradation and no cycle volt-age induced change in performance.

The shift in Vth resulting from the humid HTRB is negative (a de-crease in Vth): this implies that HTRB generates a net positivecharge in the gate oxide. The concentration of the positive ionsgenerated by the HTRB stress is estimated from the shift in Vth tobe �3–4 � 1011 cm�2. Moreover, the changing direction of the Vth

shift with a subsequent cycle voltage is an indication that thisHTRB-induced positive charge is mobile in the gate oxide. In thecase of negative cycle voltage, the overall charge centroid of mobilepositive ions moves away from the gate oxide/Si interface towardsthe metal gate. In this case Vth of the n-UMOSFET is observed to

recover and increase towards the pre-stress value. The oppositeis true for a positive cycle voltage. These positive ions are observedto be induced by the humid HTRB and are not generated during thedry HTRB.

The observation that these positive ions are only introduced byhumid HTRB favors the identification of these positive ions as theprotons (H+s). Several experiments reported in the literature havedemonstrated proton diffusion in SiO2 induced by electric fieldapplication [9–11]. Our identification is consistent with the abilityof H+ to move in the oxide at room temperature since all othercommon positive ions in the oxide, such as metallic ions, are notmobile at room temperature and they require a higher tempera-ture for them to move in the gate oxide. Indeed the HTRB inducedpositive charge exhibited room-temperature mobility even in theabsence of an applied cycle voltage. The results of concentrationdriven room temperature diffusion of H+ in the absence of electricfield are shown in Fig. 5. An n-UMOSFET degraded by humid HTRBis given a 2000-s negative-polarity (Vg = �1 V) cycle voltage, whichcauses the migration of H+s away from the oxide/Si interface to-wards the gate and, hence, produces recovery on Vth. The solid dia-mond symbols in Fig. 5 give the absolute values of the shift in Vth

(DVth) as a function of time in the recovered n-UMOSFET and in theabsence of any gate voltage. The plot shows the concentration gra-dient driven diffusion of H+ back towards the oxide/Si interfacemonitored as a shift in Vth; i.e., n-UMOSFET degradation in theform of a decrease in Vth. After �3000 s DVth saturates indicatingthat H+ diffusion stops and a uniform distribution of H+ over theoxide is attained.

After the uniform distribution of the protons in the oxide isreached in the n-UMOSFET (the solid diamond symbols in Fig. 5),a 2000-s positive-polarity (Vg = +1 V) cycle voltage is applied tothe n-UMOSFET to induce the migration of the H+ ions towardthe oxide/Si interface and, hence, causes a negative shift in thethreshold voltage of the n-UMOSFET. The solid triangle symbolsin Fig. 5 show the time dependent recovery (positive shift or in-crease in Vth), in the absence of any applied gate voltage, as a func-tion of time in the n-UMOSFET following Vth degradation by thepositive-polarity cycle voltage. The observed Vth recovery is dueto concentration driven diffusion of the protons from the oxide/Siinterface side towards the gate. Again, this diffusion stops whena uniform H+ distribution in the oxide is reached after �3000 s aswitnessed by the saturation in DVth in the line fit of the solid trian-gle symbols.

Fig. 6. Computer simulation results of the gate voltage on the parasitic p-MOSFETas a function of the voltage applied to the n-UMOSFET’s drain during HTRB andinterface charge density.

J. Hao et al. / Microelectronics Reliability 54 (2014) 374–380 377

A more careful study of the results in Fig. 5 suggests that protondiffusion from the SiO2/Si interface towards the SiO2/poly interface(solid triangle symbols) tend to proceed faster than the proton dif-fusion in the opposite direction (solid diamond symbols). This isseen from the relatively faster saturation of the SiO2/Si to SiO2/polyproton diffusion with respect to the SiO2/poly to SiO2/Si proton dif-fusion. Moreover the slope of the initial linear region of the diffu-sion curve is 0.049 in the former diffusion compared to 0.047 inthe latter indicating a faster SiO2/Si to SiO2/poly proton diffusion.It is plausible to assume that the gate oxide near and at theSiO2/poly is more defective and, hence, able to trap H+ moreefficiently than the gate oxide near and at the SiO2/Si interface.Therefore H+ diffusion proceeds faster in the direction from theSiO2/Si interface to the SiO2/poly than in the opposite directionas protons are less trapped at the SiO2/Si interface and can diffusemore readily in the former direction. Also, one notes that after along diffusion time P5000 s DVth saturates to similar levels inthe two opposite diffusion directions as witnessed by the coincid-ing data points for the two longest diffusion times. Moreover, thefaster H+ diffusion away from the SiO2/Si is observed to occur inthe presence of an applied gate bias as can be clearly seen fromthe results in Figs. 2 and 4. In these figures changes in Vth appearto occur at a faster rate when a negative cycle voltage is appliedto the gate and H+ diffusion is from the SiO2/Si interface towardsthe SiO2/poly interface (Fig. 2). Faster H+ diffusion from the SiO2/Si interface towards the SiO2/poly interface may also be causedby local electric fields in the oxide, especially the local electricfields arising from stress-induced interface hole traps if occupied.Generation of interface traps in our devices by the stress isobserved to occur as discussed later in Section 3.2.

The results in Fig. 5 were used to estimate the diffusion coeffi-cient D for H+ in the oxide at room temperature and it is found tobe �10�18 cm2/s. We could not find reports in the literature forestimates of D for H+ in the gate oxide of MOSFETs fabricated onSi substrates. However the numbers we obtained for the diffusioncoefficient are of the same order of magnitude as D �1.6 � 10�19 -cm2/s reported for proton diffusion in the gate oxide of organicfield-effect transistors [12] and D �3 � 10�17 cm2/s for proton dif-fusion in amorphous Si [13]. Therefore our estimation of the diffu-sion coefficient of the mobile ion supports the identification of theion as the proton.

Given the biasing configuration one notes that the gate oxide onthe trench sidewalls and along the channel of the n-UMOSFET isnot subjected to any voltage stress during the application of theHTRB stress. Nonetheless a shift in Vth and an increase in IDSS areobserved following the humid HTRB. These degradation effectsare attributed to the generation of mobile protons in the gate oxideby the humid HTRB. We now attempt to understand the processesand mechanisms by which the n-UMOSFET is degraded during theHTRB stress.

3.2. HTRB stress implications: bias instability in the UMOSFET

In the n-UMOSFET structure the oxide extends over the trenchbase above the lightly doped n-type diffusion region, which makesthe drain side of the n-UMOSFET (Fig. 1a). This oxide with then+-polycrystalline Si on top as a gate stack, the lightly doped n-typeSi as a substrate, and the p-well regions on each side of the trenchas the source and drain form a parasitic p-channel MOSFET(p-MOSFET). Therefore, the HTRB applied as a positive voltage onthe drain of the n-UMOSFET can be viewed as a negative voltagestress on the gate of the parasitic p-MOSFET. The magnitude ofthe negative voltage stress on this part of the gate oxide of theparasitic p-MOSFET may be found by subtracting the voltage dropacross the lightly doped n-type Si drift region in the drain of then-UMOSFET. Fig. 6 gives the simulation plots of the gate voltage

on the parasitic p-MOSFET versus the HTRB drain voltage on then-UMOSFET extracted as functions of the interface charge density.The simulation plots also take into account the geometry anddimensions of the drain diffusion region as well as its n-type dop-ing profile. It is seen from these simulations for a drain voltage of�+20 V during the HTRB of the n-UMOSFET a negative gate voltagestress of up to �4 V (��2 to �4 MV/cm) develops on the gate oxidein the parasitic p-MOSFET. This negative bias stress on the gate ofthe parasitic p-MOSFET occurs at the elevated temperature of theHTRB of �130 �C. The outcome of the stress on the parasitic p-MOSFET is the observed degradation in the n-UMOSFET’s charac-teristics presented above. These experimental and simulation re-sults together with the preceding discussion lead us to proposethat we are observing negative-bias temperature instability (NBTI)[14,15] in the parasitic p-MOSFET structure occurring at the bot-tom of the trench in an n-UMOSFET.

NBTI is commonly observed to result in positive charge buildupin the gate dielectric in p-MOSFETs when stressed with a negativegate bias. This positive charge causes an increase in the absolutevalue of the threshold voltage, a decrease in the linear and satura-tion drain currents, and a decrease in the transconductance ofp-MOSFET. The positive charge generation comes from threesources: (1) interface traps [14–17]; (2) hole trapping in pre-exist-ing defects, which is mainly an issue in high-k gate dielectrics[18,19]; and (3) bulk oxide traps [20]. The interface traps (danglingSi-bonds) are passivated by hydrogen (Si–H) in forming gas anneal-ing processes. However, the Si–H bond is weak and it can break atnormal operating conditions in the presence of cold hole near theinterface and regenerate the dangling Si-bonds [14,15]. We havemeasured the interface trap density (Nit) in the n-UMOSFET beforeand after the HTRB stress using capacitance–conductance–voltage–frequency (CCVF) methods and we observed a three-foldincrease in Nit from �7 � 1010 cm�2 eV�1 before the HTRB stressto �2 to 4 � 1011 cm�2 eV�1 after the stress. The increase in theinterface trap density observed by CCVF is confirmed by thesubthreshold slope results in Fig. 7, where the logarithmic draincurrent is plotted as a function of the gate-to-source voltage inthe subthreshold operating regime of the UMOSFET. It can be seenfrom Fig. 7 that the slope of the Ids versus Vgs plots is steeper in theunstressed UMOSFET and decreases significantly following thehumid stress. The results in Fig. 7 give a subthreshold swing, S,of 107 mV/dec in the fresh device, which increases to 180 mV/dec after the humid stress. It is noted from Fig. 7 that S recoversto its value in the unstressed device upon the application of anegative cycle-voltage for 1000 s to the stressed UMOSFET. Thisis clearly seen in Fig. 7 where the results on these UMOSFETs lie

Fig. 7. The figure shows the logarithmic Ids versus Vgs in the subthreshold operatingregime measured on a fresh UMOSFET prior to the application of HTRB and after theapplication of humid HTRBT followed by a �1 V (cycle-voltage) applied to the gatefor 1000 s.

Fig. 8. (a) Optical image of the die after solder ball removal, (b) optical imageshowing anomaly along the perimeter of the device and (c) SEM image of a crack inthe passivation region over the Al metal.

378 J. Hao et al. / Microelectronics Reliability 54 (2014) 374–380

on two parallel straight lines. Furthermore the recovery observedin S with the 1000-s negative cycle-voltage agrees with the Ids ver-sus Vgs results in Fig. 2.

The increase in Nit occurred following both humid and dry HTRBstresses. The observation of the interface trap generation by thestress, irrespective of whether the stress ambient is dry or humid,is consistent with our suggestion of the occurrence of NBTI. This in-crease in Nit presumably occurs mostly at the interface at the bot-tom of the trench. Hence Nit at the interface in the bottom of thetrench (the parasitic p-MOSFET interface) may be much larger thanthe number quoted above for Nit after the stress since it is derivedusing the entire gate-oxide/substrate interface surface area in then-UMOSFET.

While NBTI on the parasitic p-MOSFET occurred during theHTRB stress in both dry ambient and humid ambient and resultedin interface trap generation, the proton generation in the gateoxide of the UMOSFET needed the humid ambient during theHTRB. We could not measure the threshold shift in the parasiticp-MOSFET since the p-type substrate regions on the opposite sidesof the n-UMOSFET’s trench, and which act as the drain and sourcein the parasitic p-MOSFET, are short-circuited in our test structure.However, it is inferred from the negative shift in Vth of then-UMOSFET and, hence, the positive sign of the charge (H+s)accumulated in the gate oxide that the shift in Vth of the parasiticp-MOSFET would also be negative as often observed in NBTIexperiments in the presence of water vapor [14,15].

There are two features of NBTI that are relevant to this study.The first feature of NBTI is its observation in p-MOSFETs, subjectedto a negative gate bias stress, and the need for energetic holes forNBTI to occur [14,21]. The applicability of this feature to our de-vices is addressed by the proposition that the NBTI takes place ina parasitic p-MOSFET structure occurring at the trench bottom inthe n-UMOSFET. We note that a sister effect is observed in n-chan-nel MOSFETs upon the application of positive bias to the gate and,hence, referred to the effect as positive-bias temperature instability(PBTI) [22]. The second feature is the observation that NBTI isenhanced by the presence of water in the oxide [14,21,23]. Thisis the case with the degradations in Vth and IDSS observed in ourdevices (Figs. 2–4): a large degradation is observed in our devicesfollowing humid HTRB. The hypothesis is that water vapor getsinto the gate oxide during the humid HTRB and protons aregenerated upon water molecule dissociation and hole injectionand trapping. The latter two processes, molecule dissociation andhole injection and trapping, are energized by electrical stress andelevated temperatures [14].

3.3. Sources of protons and possible reaction paths

To determine the causes for water molecules introduction in thegate oxide during humid HTRB, failure analysis were performed onthe devices that were significantly affected by the stress. The de-vices were removed from the coupon boards by placing the boardson a hot plate to reflow the solder for 20–30 min. The devices werepulled from each board and subsequently inspected using a NikonEclipse L200 optical microscope. There were no anomalies ob-served at this stage of the inspection. The devices were thenmounted on a wafer piece using epoxy. The solder balls (Fig. 1b)were then removed by dissolving it in Aqua Regia (HCl:HNO3 inthe ratio 3:1) for �10 min. No anomalies were observed at thisstage either and a typical optical image after the solder bump

J. Hao et al. / Microelectronics Reliability 54 (2014) 374–380 379

removal off the device is shown in Fig. 8a. Each die in the image ofFig. 8a comprises several trenches. The polyimide layer in the de-vice (Fig. 1b) was then removed using the Trion Sirus T2 RIE systemfor 20 min using oxygen only. At this stage of the inspection opticalmicroscopy reveals anomalies in the devices as shown in the opti-cal image of Fig. 8b. Further SEM inspection of the anomalies wasperformed using a JEOL JSM-7600F tool. SEM pictures showed thepresence of passivation cracks in the edge termination as shown inFig. 8c. These anomalies and cracks are not observed in n-UMOSFETsthat were able to resist degradation by the humid HTRB stressing.Therefore during humid HTRB water molecules may diffusethrough these cracks at the edge of the n-UMOSFET [24,25].

Our results indicate that the water molecule is the catalyst forproton generation in the oxide presumably through dissociationand subsequent interactions in the gate oxide and interface. Watermolecule dissociation is hole-assisted, promoted by an intenseelectric field �2–4 MV/cm occurring at the trench bottom, andenergized by an elevated stress temperature of �130 �C [24,25].Also, the stress field and polarity generate holes in the invertedchannel of the parasitic p-MOSFET and accelerate these holes to-wards the interface. Using reaction–diffusion models NBTI hasbeen described by interactions involving the following electro-chemical paths [26]:

Si3 � Si�Hþ pþ () Si3 � Siþ þHHþH() H2

Hþ Si3 � Si�Hþ pþ () Si3 � Siþ þH2

ð1Þ

In these reactions Nit is enhanced as well as atomic hydrogen orhydrogen molecules are created. Presumably, the reactions in (1)occur during both dry and humid HTRB stresses as we observedcomparable increases in Nit arising from the two types of stresses.However we observed shifts in Vth only following humid HTRBstress. This suggests that much large concentrations of protonsare produced by humid HTRB stress.

Early experimental studies on the electrolysis of water in SiO2

have shown that protons can be produced electrolytically in SiO2

[27]. Subsequently density functional calculations have revealedwater at the Si–SiO2 interface can undergo oxidation and yieldsprotons in the presence of energetic holes [28]. More recentlyand based on studies of proton generation in MOSFETs, it is pro-posed that hole-assisted production of protons in the accumulationlayer of a n-channel MOSFET and their subsequent migration intothe gate oxide is the mechanism responsible for the large protonconcentrations observed in the gate oxide of the MOSFET [12].According to this mechanism the proton generation results fromthe reaction [12]

2H2Oþ 4pþ ������������!hole-assisteddissociation 4Hþ þ O2 ð2Þ

We tentatively attribute the production of the large proton con-centrations in the gate oxide of our UMOSFET to the electrolyticwater dissociation in reaction (2) above. However in our case thewater dissociation reaction occurs during the HTRB in the inver-sion layer of the parasitic p-MOSFET at the trench bottom of then-UMOSFET. We believe that the HTRB field promotes the catalyticrole of the hole in the water molecule dissociation. This is evidentfrom our observation that no shifts in the threshold voltage occurin n-UMOSFETs that were stored, with no stress voltage applied, inhumid ambient for durations and at temperatures similar to thoseused in the HTRBs.

Protons from their source at the bottom of the trench migrate toother regions of the gate oxide in the n-UMOSFET including theoxide on the trench sidewalls as witnessed by the observed H+-in-duced DVth in the n-UMOSFET as argued above. These large con-

centrations of H+s resulting from water molecule dissociationsare responsible for our observations of shifts induced by humidHTRB in Vth and its subsequent modulation by cycle voltage. Thefact that we are able to move the protons between the gate andthe oxide/Si interface with the application of a cycle voltage sug-gests that the protons are not immobilized by getting trapped atdefect sites in the gate oxide, oxide/Si interface, or the gate/oxideinterface. In spite of the HTRB stress transformed into a stress onthe oxide and interface at the bottom of the trench it seems thatthe protons are able to migrate across the entire gate oxide includ-ing its parts on the trench sidewalls.

4. Conclusion

Utilizing transistor parameter measurements and SEM we havestudied the effects of HTRB on n-UMOSFETs of �0.5 lm trenchwidth, �1 lm channel length, and 160-Å-thick gate oxide. TheHTRB was applied to the n-UMOSFET with an applied drain voltageof +20 V while the gate, source and body were all grounded. HTRBwas applied in either a dry ambient for 168 h at 150 �C or a 85%-relative-humidity ambient for 96 h at 130 �C. It is argued that theHTRB on the n-UMOSFET translates into a NBTI in a parasiticp-MOSFET structure occurring at the bottom of the trench andincorporating the gate oxide on the trench bottom, the n-UMOS-FET’s drain diffusion region and the p-type body regions on eitherside of the trench as the p-MOSFET’s body, and drain/sourcerespectively. The manifestation of the HTRB/NBTI degradation ofthe n-UMOSFET is the generation of interface traps. In additionto interface trap increase the humid stress is observed to generatemobile positive ions in the gate oxide. These ions can be moved be-tween the oxide/Si interface and the oxide/gate interface by theapplication of a relatively small gate voltage at room temperature.The polarity of the gate voltage determines the direction of ionsmotion towards or away from the interface. These ions were iden-tified as mobile protons (H+), which are generated as a result ofelectric-field assisted interactions at the oxide/silicon interface inthe presence of holes. The proton generation during the humidHTRB is catalyzed by water molecules that diffuse into then-UMOSFET through passivation cracks at the edge of the device.We reiterate that for the UMOSFET degradation reported in thiswork to occur, the electrical stress on the gate oxide must be high(P2 MV/cm) and applied in a moist environment.

Acknowledgments

The authors would like to thank Fairchild reliability departmentfor performing the HTRB stress, and Fairchild FA and WLR Labora-tories for their experimental support. Also the authors would liketo thank Mark Rinehimer for providing the simulation data andBarry O’Connell for helpful discussions.

References

[1] Owyang K, Bulucea C, Hshieh F, Yilmaz H. Advances in power MOSFETtechnologies for automotive applications. Automot Power Electron 1989:9–14.

[2] Jayant Baliga B. Power semiconductor devices. Boston PWS Pub Co; 1996.[3] Narazaki A, Hisamoto Y, Tadokoro C, Takeda M, Hagino H. A novel 30 V

p-channel trench gate power MOSFET with ultra low on-state-resistance atlow-gate-voltage. In: IEEE international symposium on power semiconductordevices and IC’s, ISPSD, vol. 97. 1997. p. 285–88.

[4] Williams RK, Grabowski W, Darwish M, Chang M, Yilmaz H, Owyang K. A 1million-cell 2.0-m/spl Omega/ 30-V TrenchFET utilizing 32 Mcell/in/sup2/ density with distributed voltage clamping. International electron devicesmeeting, IEDM technical digest, 1997. p. 363–66.

[5] JEDEC. Temperature, bias, and operating life. IESD22-A108D, November 2010.[6] JEDEC. Stress-test-driven qualification of integrated circuits. JESD47, February

2011.

380 J. Hao et al. / Microelectronics Reliability 54 (2014) 374–380

[7] Suliman SA, Gollagunta N, Trabzon L, Hao J, Ridley RS, Knoedler CM, et al. Thedependence of UMOSFET reliability on geometry and processing. Semicond SciTechnol 2001;16(6):447.

[8] Suliman SA, Awadelkarim OO, Ridley RS, Dolny GM. Gate-oxide grown on thesidewalls and base of a U-shaped Si trench: effects of the oxide and oxide/Siinterface condition on the properties of vertical MOS devices. Microelectronic2003;72:247.

[9] Vanheusden K, Warren WI, Devine RAB, Fleetwood DM, Schwank JR, ShaneyfeltMR, et al. Non-volatile memory device based on mobile protons in SiO2 thinfilms. Nature 1997;386:587–9.

[10] Rashkeev SN, Fleetwood DM, Schrimpf RD, Pantelides ST. Defect generation byhydrogen at the Si–SiO2 interface. Phys Rev Lett 2001;87(16):165506.

[11] Godet J, Pasquarello A. Proton diffusion mechanism in amorphous SiO2. PhysRev Lett 2006;97(15):155901.

[12] Sharma A, Mathijssen SGJ, Kemerink M, de Leeuw DM, Bobbert PA. Protonmigration mechanism for the instability of organic field-effect transistors.Appl Phys Lett 2009;95:253305.

[13] Yu GC. Hydrogen ion diffusion coefficient in a hydrogenated amorphoussilicon thin film. J Mater Chem 2003;13:841.

[14] Schroder DK, Babcock JA. Negative bias temperature instability: road to tocross in deep submicron silicon semiconductor manufacturing. J Appl Phys2003;94:1.

[15] Alam M, Kufluoglu H, Varghese D, Mahapatra S. A comprehensive model ofPMOS NBTI degradation: recent progress. Microelectron Reliab 2005;45:71.

[16] Grasser T, Kaczer B, Goes W. An energy-level perspective of bias temperatureinstability. In: Proc Int Rel Phys Symp, 2008. p. 28–8.

[17] Mahapatra S, Kumar PB, Alam MA. Investigation and modeling of interface andbulk trap generation during negative bias temperature instability ofp-MOSFETs. IEEE Trans Electron Dev 2004;51:1371–9.

[18] Liu WJ, Liu ZY, Huang ID, Liao CC, Zhang LF, Gan ZH, Wong W, Shen C, Li MF.On-the-fly interface trap measurement and its impact on the understanding of

NBTI mechanism for p-MOSFETs with SiON gate dielectric. In: Proc. IEDM,2007. p. 813–16.

[19] Ang DS, Wang S. Recovery of the NBTI-stressed ultrathin gate p-MOSFET: therole of deep-level hole traps. IEEE Electron Dev Lett 2006;27(11):914–6.

[20] Joshi K, Mukhopadhyay S, Goel N, Mahapatra S. A consistent physicalframework for N and P BTI in HKMG MOSFETs. In: Proc Int Rel Phys Symp,2012. p. 5A.3.1–5A.3.10.

[21] Blat CE, Nicollian EH, Poindexter EH. Mechanism of negative-bias-temperatureinstability. J Appl Phys 1991;69:1712.

[22] Zhang JF, Zhao CZ, Groesenken G, Degraeve R, Ellis JN, Beech CD. Hydrogeninduced positive charge generation in gate oxides. J Appl Phys2001;90(4):1911.

[23] Sasada K, Arimoto M, Nagasawa H. Nishida A, Aoe H, Dan T, Fujiwara S,Matsushita Y, Yodoshi K. The influence of SiN films on negative biastemperature instability and characteristics in MOSFETs. In: ICMTS 1998:proceedings of the 1998 international conference on microelectronic teststructures, 1998. 207–10.

[24] Zhang QM, Tang SP, Wallace RM. Proton trapping and diffusion in SiO2 thinfilms: a first principles study. Appl Surf Sci 2001;172:41.

[25] Tsetseris L, Pantelides ST. Migration, incorporation, and passivation reactionsof molecular hydrogen at the Si–SiO2 interface. Phys Rev B 2004;70:245320.

[26] Islam AE, Kufluoghu H, Varghese D, Mahapatra S, Alam MA. Recent issues innegative-bias temperature instability: initial degradation, field-dependence ofinterface trap generation, hole trapping effects, and relaxation. IEEE TransElectron Dev 2007;54(9):2143–54.

[27] Stoffer A, Folman M. Surface conductivity and conduction mechanisms onadsorption of vapors on silica. Trans Faraday Soc 1966;62:3559–69.

[28] Tsetseris L, Zhou X, Fleetwood DM, Shrimpf RD, Pantelides ST. Hole-enhancedreactions of water at the Si–SiO2 interface. Mater Res Soc Symp Proc2004;786:171.