Fabrication of MOSFETs

8/13/2019 Fabrication of MOSFETs

1/49

Fabrication of MOSFETs


2/49

INTRODUCTION

Metal Oxide Semiconductor Field EffectTransistors nMOS and pMOS MOSFETS

Voltage applied to insulated gate controls currentbetween source and drain


3/49

nMOS Transistor

Four terminals: gate, source, drain, body

Gateoxidebody stack looks like a capacitor

Gate and body are conductors

SiO2(oxide) is a very good insulator Called metaloxidesemiconductor (MOS) capacitor

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+


4/49

nMOS Operation

Body is commonly tied to ground (0 V)

When the gate is at a low voltage:

P-type body is at low voltage

Source-body and drain-body diodes are OFF No current flows, transistor is OFF

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

0

S


5/49

nMOS Operation Cont.

When the gate is at a high voltage:

Positive charge on gate of MOS capacitor

Negative charge attracted to body

Inverts a channel under gate to n-type Now current can flow through n-type silicon from source

through channel to drain, transistor is ON

0: Introduction Slide 5

n+

p

GateSource Drain

bulk Si

SiO

2

Polysilicon

n+

D

1

S


6/49

pMOS Transistor

Similarly

Body tied to high voltage (VDD)

Gate low: transistor ON

Gate high: transistor OFF Bubble indicates inverted behavior

SiO2

n

GateSource Drain

bulk Si

Polysilicon

p+ p+


7/49

Transistors as Switches

We can view MOS transistors as electrically controlledswitches

Voltage at gate controls path from source to drain

g

s

d

g = 0

s

d

g = 1

s

d

g

s

d

s

d

s

d

nMOS

pMOS

OFFON

ONOFF


8/49

N-MOS Fabrication Process

Fig. (1) Pure Si single crystal

Si-substrate

Fig. (2) P-type impurity is lightly doped

- - - - - - - - - - - - - - - - - - - - - - - - - - -- - - -- - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

- - - - - - - - - - - - - -


9/49


Fig. (3) SiO2Deposited over si surface

Fig. (4) Photoresist is deposited overSiO2layer

Thick SiO2

(1 m)

Photoresist

Thick SiO2

(1 m)

- - - - - - - - - - - - - - - - - - - - - - - - - - -- - - -- - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - -- - - -- - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - -


10/49


Fig. (5) Photoresist layer is exposed toUV Light through a mask

Photoresist

Thick SiO2

(1 m)

UV Light

Mask-1

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -Mask-1 is used to expose the SiO2 where

S, D and G is to be formed.


11/49


Fig. (6) Developer removes unpolymerised photoresist. It willcause no effect on Si surface

PolymerisedPhotoresist

Thick SiO2

(1 m)

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -


12/49


Fig. (7) Etching [HF acid is used] will remove SiO2 layer which is indirect contact with etching solution

Thick SiO2

(1 m)- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -


13/49


Fig. (7) unpolymerised photoresist is also etched away [usingH2SO4]

Thick SiO2

(1 m)- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -


14/49


Fig. (8) A thin layer of SiO2grown over the entire chip surface

Thick SiO2

(1 m)

Thin SiO2

(0.1 m)

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -


15/49


Fig. (9) A thin layer of polysilicon is grown over the entire chip surface toform GATE

Thick SiO2

(1 m)

Thin SiO2

(0.1 m)

Polysilicon layer

(12 m)

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -


16/49


Fig. (10) A layer of photoresist is grown over polysilicon layer

Thick SiO2

(1 m)

Thin SiO2

(0.1 m)

Polysilicon

layer

Photoresist

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -


17/49


Fig. (11) Photoresist is exposed to UV Light

UV Light

Mask-2

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Mask-2 is used to deposit Polysilicon toform gate.


18/49


Fig. (12) Etching will remove that portion of Thin SiO2 which is notexposed to UV light

Thick SiO2

(1 m)

Thin SiO2

(0.1 m)

Polysilicon

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -


19/49


Fig. (13) Polymerised photoresist is also stripped away

Thick SiO2

(1 m)

Thin SiO2

(0.1 m)

Polysilicon used as GATE

(12 m)

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -


20/49


Fig. (14) n+Doping to form SOURCE and DRAIN

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Thick SiO2

(1 m)

Thin SiO2

(0.1 m)

GATE

-- -- - -

n+

-- - -- -

n+

SOURCE DRAIN


21/49


Step - Metallization

Fig. (15) A thick layer of SiO2 (1 m) is again grown.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Thick SiO2

(1 m)

-- -- - -

n+

-- - -- -

n+ Thick SiO2(1 m)


22/49



Fig. (16) Photoresist is grown over thick SiO2. Selected areas of the poly GATE and SOURCE and DRAIN are

exposed where contact cuts are to be made

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Thick SiO2

(1 m)

-- -- - -

n+

-- - -- -

n+ Thick SiO2(1 m)

Photoresist

Mask-3

UV Light

Mask-3 is used to make contact cuts for S, D and G.


23/49



Fig. (17) The region of photoresist which is not exposed by UV light will become soft. This unpolymerised

photoresist and SiO2below it are etched away.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Thick SiO2

(1 m)

-- -- - -

n+

-- - -- -

n+ Thick SiO2(1 m)

Photoresist

Mask-3


24/49



Fig. (18) The contact cuts are formed for S, D and G (hardened photoresist is stripped away).

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Thick SiO2

(1 m)

-- -- - -

n+

-- - -- -

n+ Thick SiO2(1 m)

Photoresist

Mask-3


25/49



Fig. (19) Metal (aluminium) is deposited over the surface of whole chip (1 m thickness).

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Thick SiO2

(1 m)

-- -- - -

n+

-- - -- -

n+ Thick SiO2(1 m)

Metal (1m)


26/49



Fig. (20) Photoresist is deposited over the metal.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Thick SiO2

(1 m)

-- -- - -

n+

-- - -- -

n+ Thick SiO2(1 m)

Metal (1m)

Photoresist


27/49



Fig. (21) UV Light is passed through Mask-4 (with a aim of removing all metal other than metal in contact-cuts).

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Thick SiO2

(1 m)

-- -- - -

n+

-- - -- -

n+ Thick SiO2(1 m)

Metal (1m)Photoresist

UV Light

Mask-4

Mask-4 is used to deposit metal in contact cuts of S, D and G.


28/49



Fig. (22) Photoresist and metal which is not exposed to UV light are etched away.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Thick SiO2

(1 m)

-- -- - -

n+

-- - -- -

n+ Thick SiO2(1 m)

Metal (1m)Photoresist

Mask-4


29/49



Fig. (23) Final n-MOS Transistor

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- -- - -

n+

-- - -- -

n+

SOURCE DRAIN

GATE


30/49

Fabrication Steps-CMOS

Start with blank wafer

First step will be to form the n-well

Cover wafer with protective layer of SiO2(oxide)

Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer

Strip off SiO2

p substrate


31/49

Oxidation

Grow SiO2on top of Si wafer

9001200 C with H2O or O2in oxidation furnace

p substrate

SiO2


32/49

Photolithography

Exposure Processes


33/49

Photoresist

Used for lithography .

Lithography is a process used to transfer a pattern to layer on the chip.Similar to Printng Process

Spin on photoresist (about 1 mm thickness)

Photoresist is a light-sensitive organic polymer

p substrate

SiO2

Photoresist


34/49

Lithography

Expose photoresist through n-well mask

Strip off exposed photoresist

p substrate

SiO2

Photoresist


35/49

Etch

Etch

Chambers

Cluster Tool

Configuration

Transfer

Chamber

Loadlock

Wafers

RIE Chamber

Transfer

Chamber

Gas Inlet

Exhaust

RF Power

Wafer

Die-electric Etch

Plasma Etch


36/49

Etch

Etch oxide with hydrofluoric acid (HF)

Only attacks oxide where resist has beenexposed

p substrate

SiO2

Photoresist


37/49

Strip Photoresist

Strip off remaining photoresist

p substrate

SiO2


38/49

n-well

n-well is formed with diffusion or ion implantation

Diffusion

Place wafer in furnace with arsenic gas

Heat until As atoms diffuse into exposed Si Ion Implanatation

Blast wafer with beam of As ions

Ions blocked by SiO2, only enter exposed Si

n well

SiO2


39/49

Strip Oxide

Strip off the remaining oxide using HF

Back to bare wafer with n-well

Subsequent steps involve similar series of steps

p substrate

n well


40/49

Polysilicon

Deposit very thin layer of gate oxide

< 20 (6-7 atomic layers)

Chemical Vapor Deposition (CVD) of silicon layer

Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon

Heavily doped to be good conductor

Thin gate oxidePolysilicon

p substraten well


41/49

Polysilicon Patterning

Use same lithography process to pattern polysilicon

Polysilicon

p substrate

Thin gate oxidePolysilicon

n well


42/49

Self-Aligned Process

Use oxide and masking to expose where n+ dopants should bediffused or implanted

N-diffusion forms nMOS source, drain, and n-well contact

p substraten well


43/49

N-diffusion

Pattern oxide and form n+ regions

Self-aligned processwhere gate blocks diffusion

Polysilicon is better than metal for self-aligned gates becauseit doesnt melt during later processing

p substraten well

n+ Diffusion


44/49

N-diffusion cont.

Historically dopants were diffused

Usually ion implantation today

But regions are still called diffusion

n wellp substrate

n+n+ n+


45/49

N-diffusion cont.

Strip off oxide to complete patterning step

n wellp substrate

n+n+ n+


46/49


47/49

Contacts

Now we need to wire together the devices

Cover chip with thick field oxide

Etch oxide where contact cuts are needed

p substrate

Thick field oxide

n well

n+n+ n+p+p+p+

Contact


48/49

Metalization

Sputter on aluminum over whole wafer

Pattern to remove excess metal, leaving wires

p substrate

Metal

Thick field oxide

n well

n+n+ n+p+p+p+

Metal


49/49

THANK YOU

Fabrication of MOSFETs

Documents

Transcript of Fabrication of MOSFETs