NOTE TO USERS · resistance and in the gate charge on-resistance figure of ment (~~.&,=0.23n.n~)...

NOTE TO USERS

This reproduction is the best copy available.

Lateral Superjunction Power MOSFETs

Mathew Atekwana Amberetu

A thesis submitted in confirmity with the requirements for the degree of Master of Applied Science

Edward S. Rogers Sr. Department of Electrical and Cornputer Engineering University of Toronto

2001

O Copyright by Mathew Atekwana Amberetu 2001

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Abstract

Lateral Superjunction Power MOSFETs

Master of Applied Science. 200 1 1 Mathew Atekwana Amberetu

Edward S. Rogers Sr. Department of Electrical and Cornputer Engineering University of Toronto

Abstract

Power serniconductor devices play a crucial role in the efficient control of power used in

electronic systems. There is a great need for the reduction of the power losses during switching

and on-state conduction of such devices.

In this thesis a novel lateral power MOSFET compatible with CMOS on SOI technology

and using the supe junction concept is proposed.

The supe junction (SJ) concept, requires the use of a drain drift region consisting of alter-

nate n- and p-type, highly doped regions. These regions are fully depleted in the current blocking

mode of operation to ensure a high breakdown voltage. The implementation of the SJ concept in

lateral power MOSFETs in silicon-on-insulator (SOI) technology combines the reduction in on-

state power losses with complete suppression of substrate currents and latchup, easy integration of

a wide range of power and small signal analog and dense CMOS active devices on the same chip,

increased packing densities, fast switching speed and low leakage cuments.

A method of fabrication of the device is proposed, using selective area growth (SAG) to

irnplement the SI structure in the drift region of the SOI LDMOS transistor. Process and device

simulations are carried out. The novel SJ Power LDMOST exhibits a specific on-resistance of

1.65rnncrn2 for a 150V-class and breaks the silicon limit. By cornparison to conventional

LDMOST SOI devices, the proposed structure offers an improvement of over 60% in specific on-

resistance and in the gate charge on-resistance figure of ment (~~ .&,=0 .23n .n~) thus reducing

power losses during device switching and on-state conduction.

. -- . . Lateral Superjunction Power MOSFETs II University of Toronto

In memory of my father Isaiah Ambe Atugon and my mother Lydia Abo.

Ac knowledgments

Acknowledgments

1 would like to express my sincere gratitude and deep appreciation to Prof. C.A.T. Salama

for his insightful guidance, encouragement and invaluable assistance throughout the course of this

work.

Thanks also goes to Dr. K. Yano of Yamanashi University in Japan and Sameh N. Khalil for

the invaluable orientation they gave me. 1 would like to thank Jaro Pristupa for his help with van-

ous CAD tools, Dana Reem and Richard Barber for their technical and moral support. Useful dis-

cussions with and advice from Dr. Hungfei Lu and Shahla Honahrkha are highly appreciated.

My appreciation also goes to Mehrdad Ramezani for his help and friendship, and to al1 the

staff and students in the VRG Laboratory, especially Anthoula Kampouris, Sotoudeh H. Hagh,

Song Ye, Zhixian Jiao, Yucai Zhang, Farhang Vessal, Dusan Suvakovic, Namdar Saniei and Shuo

Chen for their friendship.

Most of atl, 1 wouId like to thank my spouse Rose, and my sons Ajesama, Abia-Mbu and

Ewa-Mbu, as well as my sisters Elizabeth, Anna and Emilia and the entire Atugon family, for

their love and support and for enduring my absence during the course of this work.

Above all, 1 would like to express my most sincere gratitude to the International Council for

Canadian Studies (ICCS) for providing the finacial support under the Canadian Commonwealth

Scholarship and Felowship Program (CCSFP), without which canying out this work would not

have been possible.

The support of NSERC, Micronet, Gennum, Nortel and Zarlink is gratefully acknowledged.

S . .

Lateral Superjunction Power MOSFETs 111 University of Toronto

Table of Contents

Table of Contents

Page

CHAPTER 1 Introduction 8O8OOOOO8O888OOOOOOO88OOOOOaOO8OO8OOOO8OOO8O888OOOOOOOOOO8O8OOOm888O88888O8OOO8O88O8O~

.................................................................................... . 1 1 The LDMOS Transistor (LDMOST) 2

....................................................................................................... 1.2 The RESURF LDMOST 4

.................................................................................................... 1.3 RESURF LDMOS on SOI 7

1.4 Superjunction Devices .......................................................................................................... 8

................................................................................ 1.5 Previous Work on Lateral SJ Devices 1 0

........................................................................................ 1.6 Objectives and Outline of Thesis I l

................................................................................................................................ References 12

CHAPTER 2 Novel SJ Power LDMOSTs: Device Structure and Fabrication Process ooommmoomoomomomoomeoooommomoomoooommoooooomoooomoooomomoomooooooeooomeomooommemooomooooooomommmmmmoommmommommmmommml5

....................................................................................................................... 2.1 Introduction 1 5

2.2 Device Structure ................................................................................................................. 16

................................................................................................................... 2.3 Process Design -20

........................................................................................................... 2.4 Process Description -20

.............................................................................................................. 2.5 Process Simulation 32

2.6 Summary ............................................................................................................................. 35

............................................................................................................................... References -36

................... CHAPTER 3 Novel S J Power LDMOSTs: Device Simulation mm0m88037 ........................................................................................................................ 3.1 Introduction 37

3.2 Mask Layout ....................................................................................................................... 37

............................................................................................................... 3.3 Device Simulation 39

............................................................................................ 3.3.1 Device Simulation Setup -39

................................................................................ 3.3.2 Simulated Device Characteristics 42

.................................................. 3.4 Cornparison with Conventional SOI RESURF LDMOST 52

............................................................................................................................. 3.5 Summary 53

................................................................................................................................ References -54

Lateral Supe junction Power MOSFETs iv University of Toronto

Table of Contents

Page

Lateral Superjunction Power MOSFETs v University of Toronto

List of Figures

List of Figures

Page

Chapter 1

Fig . 1.1

Fig . 1.2

Fig . 1.3

Fig . 1.4

Fig . 1.5

Fig . 1.6

Fig . 1.7

Fig . 1.8

Fig . 1.9

Fig . 1.10

Chapter 2

Fig.2.1

Fig.2.2

Fig . 2.3

Fig.2.4

Fig.2.5

Fig.2.6

Fig.2.7

Block diagram of a PIC .............................................................................................. 1

Applications of f ICs .................................................................................................. 2

Cross section of the LDMOST ................................................................................... 3

............................................. Cross section of the conventional RESURF LDMOST 4

Depletion in the conventional RESURF LDMOST with thick n drift layer ............... 5

................ Depletion in the conventional RESURF LDMOST with thin n drift layer 6

...................................................................................... Double RESURF LDMOST 7

Conventional SOI RESURF LDMOST .................................................................... -8

............................... a) The conventional VDMOST and b) The vertical SJ DMOST 9

Trench-Gated SJ NMOSFET ................................................................................. I O

................................................................. 3-D structure of the SJ Power LDMOST 16

(a) Top view of the SJ Power LDMOST (b) cross section through the n layer

............................ (line A.A'). and (c) cross section through the p layer (line B-B') 17

(a) Structure of the n and p dnft layers in the SJ structure. (b) Direction of

depletion of the layers ............................................................................................. 1 9

............................................. Process Flow for the fabrication of the SJ LDMOSTs 25

3-D Structure of the SJ LDMOST ............................................................................ 32

TSUPREM-4 structures of the SJ LDMOST: a) across the n layer. b) across

the p layer ................................................................................................................. 33

Doping Profiles of the SJ LDMOST: a) Channel Region. b) Source/Drain

Region. c) Across Device through n Layer. d) Across Device through

p Layer. e) Vertically through the n Layer. and f) Vertically through the

p Layer ..................................................................................................................... 34

Lateral Superjunction Power MOSFETs v i University of Toronto

List of Figures

Chapter 3

.......................... Top view of the SJ Power LDMOST with interdigitated geometry 38

SJ Power LDMOST Single Ce11 Layout .................................................................. 38

Cross section of the conventional SOI LDMOST .................................................... 40

(a) 3-D structure of the SJ Power LDMOST, (b) Cross section through

...................................................................... A-A'. (c) Cross section through B-B' 40

........................................... A 3-D ISE MESH structure of the SJ Power LDMOST 41

Transfer Characteristics of (a) and (c) the SJ Power LDMOST and (b) and (d)

Conventional SOI LDMOST ................................................................................... 43

Output characteristics of (a) the SJ Power LDMOST and (b)

Conventionai SOI LDMOST .................................................................................... 44

Equipotential lines in the SJ Power LDMOST at breakdown during off-state

................................................................................................................ simulation 45

Off-state blocking characteristics of (a) the SJ Power LDMOST and

(b) Conventional SOI LDMOST .............................................................................. 46

On-state blocking characteristics of (a) the SJ Power LDMOST and

.............................................................................. (b) Conventional SOI LDMOST 46

........................ Simulation circuit for the switching performance of the LDMOST 47

Charge Transfer Characteristics for (a) the SJ Power LDMOST

......................................................................... and (b) the conventional LDMOST 48

Tum-on Characteristics: Voltage Waveforms of (a) the SJ Power LDMOST

and (b) the Conventional LDMOST ......................................................................... -50

Tum-on Characteristics: Current Waveforms of (a) the SJ Power LDMOST

and (b) the Conventional LDMOST ....................................................................... -30 Tum-off Characteristics: Voltage Waveforms of (a) the SJ Power LDMOST

and (b) the Conventional LDMOST .......................................................................... 51

Turn-off Characteristics: Current Waveforms of (a) the SJ Power LDMOST

.......................................................................... and (b) the Conventional LDMOST 51

Cornparison of trade-off between VB and Ron.sp for the SJ and conventional

devices ..................................................................................................................... -52

.. -- -. - - - - - . .

Lateral Superjunction Power MOSFETs vii University of Toronto

List of Figures

Appendices Fig.Al Illustration of Layout Design Rules ........................................................................... 56

Fig.AZ Test Chip Layout ........................................................................................................ 58

Fi@ Dependence of Breakdown Voltage VB on n and p layer doping ............................... 60

Fi@, Trade-off relationships fer the conventional SOI LDMOST (Conv). and for

the SJ Power LDMOSTs ............................................................................................ 61

Fig.B3 Plots of Specific On-resistance (a) and Breakdown Voltage (b) versus the SJ layer depth .................................................................................................................. -61

Lateral Supe junction Power MOSFETs viii of Toronto

List of Tables

List of Tables

Page

Chapter 2 Table 2.1 Specified Process Parameters for the SJ Power LDMOST ................................... 2 1

Table 2.2 Major Processing Steps for the Conventional and SJ LDMOSTs ......................... 22

Table 2.3 Process Summary for the SJ LDMOST ................................................................ 30

Chapter 3 Table 3.1 Device Simulation Parameters .. . ....... . . ....... . . . . . ... . . . . . . .. .... .. .. . . . ....... . . . ... . .... ... .. . . ... . . ..39

Table 3.2 Cornparison of simulation results for the SJ and conventional devices ................ 53

Appedix A Table Al Summary of Layout Design Rules ......................................................................... 57

Lateral Supe junction Power MOSFETs i x University of Toronto

Introduction 1

CHAPTER 1

Introduction

Power Integrated Circuits (PICs) involve high voltage (HV) power devices with low voltage

(LV) analog andor digital circuits on the same chip. A block diagram of a PIC is shown in

Fig. 1.1 [l]. The circuit includes in addition to the power device driver, over-temperature, voltage,

and over-current protection, thus improving the performance, reliability, and longevi ty of the sys-

tem. PICs cover a great variety of applications such as automotive circuits, motor and solenoid

drives, inverters in electronic ballast, telecommunications, plasma displays, switching power sup-

pliers, factory automation, etc. as illustrated in Fig. 1.2 121.

Sensors 4 1 1 I I

Power Power + Device Device

Driver

PIC / r i I

Fig.l.1 Block diagram of a PIC [ 1 ]

Lateral Superjunction Power MOSFETs University of Toronto

Introduction

Automotive Electronics

Traction

Motor Control

Fac tory Automation

Ballast r Telecommunication

circuits

Display Drivers

100 Io00

Blocking Voltage Rating, V

Fig.l.2 Applications of PICS [2]

1.1 The LDMOS Wansistor (LDMOST)

The power lateral double diffused metal-oxide-semiconductor transistor (LDMOST) is the

most comrnonly used device for the implementation of PICS because of its cornpatibility with

conventional CMOS processes. The device offers high input impedance, fast switching time with

no minority carrier storage effects and immunity from second breakdown.


Introduction 3

Fig.l.3 shows the cross section of the LDMOS transistor. The device consists of four

regions: 1) a source region of length L,, 2) a channel region of length Lch. 3) the drift region of

length Ld, and 4) the drain region of length Ld. The length and doping concentration of the drift

region is chosen in such a way as to obtain the required breakdown voltage VB. The Ionger the

n- su bstrate

Fig.l.3 Cross section of the LDMOST

drift region, the higher VB and the higher the on-resistance R,,. There is a trade-off between VB

and R,,, which is described by the relationship called the silicon limit [3], given by the expression

where A is the device effective area. However, the maximum value of the breakdown voltage does

not increase infinitely with increase in drift region length, but is limited by the concentration gra-

dient at the p-well/drift junction where breakdown takes place.

The device pitch, which is the sum of L, + Lch + Ldr + Ld. determines the packing density

and the device specific on-resistance which is the product of its on-resistance and area. The

dimensions of L,, L,,,, and Ld are dictated by the process design rules. The on-resistance of the

device is given by

where R,, Rch, Rdr and % are the resistances of the source, the channel, the drift and drain regions


Introduction 4

respectively. Rd, dominates the on-resistance.

An integrable version of the device, shown in Fig. 1.3, was implemented as early as 1972 [4].

However, in such devices electric fields always crowd at the chameudrift junction and at the drain

region because of curvature effects, resulting in relatively lower breakdown voltages compared to

the ideal case of parallel plane junction.

1.2 The RESURF LDMOST

To improve the performance of the LDMOST, the REduced SURface Field (RESURF) con-

cept was introduced in 1979 [SI. The basic structure of the conventional RESURF LDMOST is

shown in Fig. 1.4 [6-81. Instead of using an n- substrate, the device is fabricated on a p- epitaxial

layer, with

S

in n- epitaxial layer serving as the drift region to block high voltages.

p well n' drift

9 p- substrate

=? 7

Fig.l.4 Cross section of the conventional RESURF LDMOST [8]

The RESURF technique can be explained by considering the structure of the RESURF

device shown in Fig. 1.4. This structure includes a vertical pn- junction and a horizontal p-n- junc-

tion. For a thick n- drift layer, the depletion of the vertical pn- junction is not influenced by the

horizontal p-n- junction and the breakdown voltage is determined solely by the vertical pn- junc-

--- -

Lateral Superjunction Power MOSFETs - --

University of Toronto

Introduction 5

tion. The space-charge region and the electric field along the surface and the mis of symmetry for

this case are shown in Fig. 1.5 [83. The maximum electric field and breakdown in this case occur at

the surface 151.

For a thinner n drift layer, some of the field lines originating in the space-charge of the p-

region terminate at the surface of the n- drift region and deplete out the surface thus creating a lat-

eral depletion layer which reinforces the depletion of the vertical pn- junction leading to a reduc-

tion in the surface field. The space-charge region and the electric field along the surface and the

axis of symmetry for this case are shown in Fig. 1.6 [8] In this case the breakdown occurs at the

parallel n- p- junction.

1 p- substrate

Fig.l.5 Depletion in the conventional RESURF LDMOST with thick n drift layer [8]

In the conventional RESURF LDMOST, the required breakdown voltage and on-resistance

can be obtained by adjusting the drift region length, the p- substrate doping concentration, and n-

drift thickness and doping concentration. The relationship between the breakdown voltage and the

on-resistance in this case is [9]

Lateral Superj unction Power MOSFETs University of Toronto

Introduction 6

5 p- su bstrate

Fig.l.6 Depletion in the conventional RESURF LDMOST with thin n drift layer [SI

where d is the n- drift thickness. For an ideal bulk breakdown there must be a symmetncal field

distribution at the surface. Two-dimensional calculations show that this can be achieved when [5]

where Nw is the doping concentration of the drift region. This equation is called the RESURF

condition. The numerical value on the right hand side of equation (1.4) actually varies depending

on the type of device in question.

Ideally, higher breakdown voltages are therefore obtained with RESURF devices with thin

n drift layers. However, since the drift region of such devices is fully depleted, a new effect arises

whereby the electric field strongly increases at the n+ drain contact to peak values greater than the

field in the bulk and so the ideal bulk breakdown can not €x reached. In an effort to enhance deple-


Introduction 7

tion at the source and drain sides and further improve the on-resistance without degrading the

breakdown voltage and vise versa, Iateral gradation in the doping in the drift region, and stepping

field plates techniques are applied[lO-1 I l . Vertically profiled layers are also employed leading to

double RESUW stmctures[I 1-1 31, with a p layer on top of the RESURF n- layer, for a lower on-

resistance and for high-side operation in ICs. A double RESURF LDMOST is shown in Fig. 1.7

r 143.

p well n' drift

1 7- p' substrate

Fig. 1.7 Double RESURF LDMOST [ 1 41

Further efforts to improve the performance of the RESURF LDMOST have resulted in the

implementation of multi-RESURF structures called superjunction (SJ) devices discussed in Sec-

tion 1.4.

1.3 RESURF LDMOST on SOI

The 2-D effects observed in the RESURF structures also exist through an intermediate oxide

layer in a silicon on insulator (SOI) LDMOST shown in Fig. 1.8 [ 15- 171 as was demonstrated in

1981 Hartman 1151. Although the buried oxide (BOX) reduces the coupling between charges in

the top silicon layer and the underlying substrate, it is capable of withstanding very high electric

.-


Introduction 8 - - - -- - - - - - - -

fields. Furthemore, the BOX serves as a dielectric isolation on which device islands are located,

isolated from each other and the underlying substrate. This completely suppresses substrate cur-

rents, eliminating latchup problems and improving ruggedness. In SOI technology, packing den-

sity is greatly increased due to srnaller isolation widths. The dielectric isolation in SOI technology

results in low leakage currents enabling both positive and negative voltages on the same chip. SOI

technology also allows integration of a wide range of power, small signal analog and dense

CMOS active devices on the same chip.

n+ substrate

Fig.l.8 Conventional SOI RESURF LDMOST [ 1 5- 171

1.4 Superjunction Devices

Multi-RESURF structures were proposed to overcome the limit of the ideal specific on-

resistance in RESURF devicesIl8-211. Such structures use alternating n and p type layers in the

drift region of the transistor. The concept was initially applied to vertical DMOSTs (VDMOSTs)

122-251. The device is obtained by replacing the drift region of the conventional VDMOST shown

in Fig. 1.9a, with the structure shown in Fig. l.9b. The alternating pillars have been referred to as

superjunctions (SJs) [9].


Introduction 9

n' drift

Fig.l.9 a) The conventional VDMOST and b) The vertical SJ DMOST [9]

Full depletion in the drift region of the SJ devices is realized by controlling the doping con-

centrations of the p and n type SJ layers, similar to controlling the doping of the n- drift region of

the conventional double RESURF devices. The RESURF condition for SJ devices for the CooL-

MOSFET is given by [26]

where Nnep and dnVp are the n or p layer doping concentration and width respectively. In addition,

charge balance must be maintained between the doping in adjacent p and n layers. This condition,

together with the RESURF condition are expressed as

where N,, Np, and d,, d,, are the doping concentrations and widths of the n and p layers respec-

tively. As such, the column widths can be made so thin so as to increase the number of SJ layers

integrated per unit area, while the doping in the columns can be made to be more than an order of

magnitude higher than that in the n drift of the conventional VDMOST. Al1 these measures lead to

- . . . . - - - - - - - - . - -


Introduction 10

a great reduction (up to two orders of magnitude) in the specific on-resistance without degrading

the breakdown voltage. This is seen by comparing the estimated trade-off relationship for the con-

ventional VDMOST which is given by the expression [9]

with that for the vertical SJ structures[9] given by

where d = dn = d P.

Much work has already been done in the application of the SJ concept to vertical devices

[22-25). So far only simulated results have ken reported on lateral devices. Simulations on the 3-

D RESURF junction 1271, and on the multi-RESURF junction field effect transistor (JFET) [28-

301, indicate a remarkable improvement in the device performance, going beyond the silicon

limit. The superjunction (multi-RESUW concept has not been applied to SOI LDMOSTs,

despite the great potential such devices possess, and the impact they could have on the power

electronics industry.

1.5. Previous Work on Lateral S J Devices

Fig.l.10 Trench-Gated S J NMOSFET [26]


Introduction 11 - - ~~~~~

The Trench-Gated SJ NMOSFET shown in Fig. 1.10 was proposed by T. Fuijihira in 1997

[9] but not implemented. He suggested the fabrication of the device by variable- or multiple-

energy ion implantation followed by annealing. Due to lateral diffusion, it is very difficult to

achieve thin n and p layers using this method. In addition, the high electnc field crowding around

the channeIldrift junction and the drain end would result in low breakdown voltages. The device

also faces isolation problems and requires the use of many epitaxial layers, thus making its imple-

mentation very difficult.

1.6. Objective and Outline of Thesis

The objectives of this thesis are to investigate the implementation of a novel power

LDMOST compatible with SOI CMOS technology and using the SJ concept, with the aim of min-

imizing the specific on-resistance while meeting breakdown voltage specifications. Target appli-

cations include DC-DC converters, and in subscriber line interface circuits (SLICs) used in

telecommunication systems.

In Chapter 2, structural design considerations of the novel SJ power LDMOST are pre-

sented. The multi-RESURF principle, as implemented in the SJ concept, is used to maintain a

required breakdown voltage while significantly reducing the specific on-resistance. Field plates

and low-doped-drain (LDD) techniques are employed to aven breakdown voltage degradation.

The process design and simulation results, as obtained from a 2-D simulator (TSUPREM4), are

presen ted.

Chapter 3 covers layout issues and presents the results of the device simulations using a 3-D

simulator (DESSIS). The major device parameters are optimized and the DC characteristics, tran-

sient response, and temperature performance are presented. The results are compared with those

of a conventional SOI RESURF LDMOST.

The results obtained are summarized and conclusions are drawn in Chapter 4. A brief dis-

cussion of future work is also given.


Re fcrences 12

References

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- - - - - - - - -

Lateral Supe rjunction Power MOSFETs -- - --


References 13

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[ 151 A. Hartman, J.E. Berthold, T.J. Riley, J.E. Kohl, Y.H. Wong, H.T. Weston, and R.S. Scott.,

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1191 D.J. Coe, U.S Patent 47543 10, 1988.

[20] X. Chen, U.S Patent 5216275, 1993.

[2 11 J. Tihanyi, U.S Patent 54382 15, 1995.

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Lateral Supe junction Power MOSFETs University of Toronto

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1261 0. Spulber, M.M. De Souza, E.M.S. Narayanan, S. Krishnan, bbAnalysis of a COOL-MOS-

FET", IEEE international Semiconductor Conference Proceedings, Vol. 1 pp. 13 1 - 134, 1999.

1271 F. Udrea, A. Popescu, R. Ng, and G.A.J. Amaratunga, "Minority Carrier injection across the

3D RESURF junction", International Symposium on Power Semiconductor Devices and

ICs (ISPSD) Proceedings, pp. 20 1-204,2000.

[28] EUdrea, A. Popescu, and W. Milne, "The 3D RESURF junction," IEEE International

Semiconductor Conference Proceedings, Vol. 1, pp. 14 1 - 144, 1998.

1291 F. Udrea, A. Popescu, and W.I. Milne, "A new class of lateral power devices for HVICs based

on the 3D RESURF concept," IEEE Bipolar/BiCMOS Circuits and Technology Meeting

(BCTM) Proceedings, pp. 1 87- 190, 1998.

[30] S. Xu, K.P.Gan, G.S. Samudra, Y.C. Liang, and J.K.O. Sin, " 120V Interdigitated-Drain

LDMOS (IDLDMOS) on SOI Substrate Break Power LDMOS Limit," IEEE Transaction on

Electron Devices, Vol. 47, pp. 1980- 1985, 2000.


Novel Supe rjunction Power LDMOSTs: Device Structure and Fabrication Process 15

CHAPTER 2

Novel Superjunction Power LDMOSTs: Device Structure

and Fabrication Process

2.1 Introduction

Previous endeavors towards the improvement of the LDMOS transistor were outlined in

Chapter 1. In order to further improve the performance of the LDMOST, a novel structure of the

device is proposed in this thesis, based on the application of the superjunction concept to the

LDMOST. A 15OV-Class device is designed to be implemented in standard SOI technology and to

be used in a variety of applications. Such applications include DUDC converters and SLICs used

in telecommunication switching systems [ I l . This device is given the name Superjunction Power

LDMOS Transistor and embodies al1 the advantages of the SOI structures outlined in Section 1.3

and of multi-RESURF devices, thus serving as a solution for high density, high switching speed

applications.

The proposed device is much simpler in structure than the one proposed by T. Fujihira (see

Section 1.5). A full fabrication process is developed and the problem of high electric field and

device isolation is considered.

The device structure, operation, and specific requirements of the proposed SJ Power

LDMOST are presented in this chapter. This is followed by the fabrication process description

and simulation resul ts. Process and device parameters are carefuH y selected to simplify the fabri-

Latenl Superjunction Power MOSFETs University of Toronto

Novel Superjunction Power LDMOSTs: Device Structure and Fabrication Process 16

cation procedure while at the same time achieving high packing density, low specific on-resis-

tance and high switching speed.

2.2. Device Structure

The novel SJ power LDMOS transistor is a 3-D structure as shown in Fig.2.l with the field

oxide, metal and polysilicon removed. Its top view is shown in Fig.2.2, alongside with the cross

n drift / / /%---- /*

+ n+ substrate

Fig.2.1 3-D structure of the SJ Power LDMOST

sectional views of the device through the n (line A-A') and p (line B-B') drift regions respectively.

The device ceIl pitch is the sum L, + L,h + Ld, + Ld, and its width comprises half the width of the

n and p drift layers as shown in Fig.2.1. Only one vertical SJ layer is used here unlike in the lattice

pattern which is made up of atternating n and p layers in both y and z directions, thus requiring

more than one vertical layer [2]. The number of altemately stacked n and p layers increases with

channel width, hence providing more current paths in the drift region.

As shown in Fig.2.2, a stepping gate oxide structure is used starting with a thickness of t,,,,


Novel Supe junction Power LDMOSTs: Device Structure and Fabrication Process 17

n+ substrate

tg& p drift tmi n' SOI

(cl

1 7

n+ substrate

Fig.2.2 (a) Top view of the SJ Power LDMOST (b) cross section through the n layer (line A-A'), and (c) cross section through the p layer (line B-B')

Lateral Supe rjunction Power MOSFETs University of Toronto

NoveI Supe junction Power LDMOSTs: Device Structure and Fabrication Process 18 - --

and ending with an oxide of thickness of tg,d, on which the gate polysilicon overlaps in the drift

region to form the gate field plate of length La. The drain field plate which is of length Ld*, is

formed by the overlap of the drain metal over a field oxide of thickness rf, Both gate and drain

field plates help to reduce electric field crowding in the gate/drift and drain regions which contrib-

ute to breakdown voltage degradation. In order to further avoid breakdown voltage degradation

resulting from high electric fields at the drainlp-drift junction due to a steep concentration gradi-

ent, a region of low doping (n-epi) is left between the p drift and the n+ drain implant. As such the

n and p drift layers of the SJ structure are of different lengths but of equal width d and thickness

tq Following from equation (1.5). they will also have the sarne doping concentrations.

When a positive potential, higher than the threshold voltage, is applied to the gate electrode

(G), an inversion layer is created in the p-well just under the gate providing a channel for electrons

to move from the source region (S) into the n drift layer towards the drain electrode (D) where

they are collected. Only the n drift layers serve as paths for the current conduction in the on-state.

The role of the p drift layers is to provide the RESURF effect during the blocking operation of the

device. The presence of these p drift layers enables the lateral depletion of the n strips from either

side as shown in Fig.2.3, where the arrows in Fig.2.3(b) indicate the direction of depletion. Opti-

mum breakdown is achieved when the depletion regions in the n and p drift layers meet, in which

case the layers are said to be fully depleted. Full depletion is achieved when the RESUFW condi-

tion given in equation (1.5) is satisfied resulting in an appreciable reduction in the surface electric

field thus enabling the drift region to be able to support higher voltages. As such, for a required

breakdown voltage, the doping in the n and p drift layers can be increased and the thickness

reduced to achieve very low on-resistance.

For the device in Fig.2.2, the SJ structure length is I=Ldr-LIdd. Using the following relation-

ship between the breakdown voltage and the on-resistance for lateral SJ devices [3]

Lateral Supe junction Power MOSFETs - - -



Fig. 2.3 (a) Structure of the n and p drift layers in the SJ structure, (b) Direction of depletion of the layers.

the specific on-resistance Ro,,.sP=Ron.A for a SJ device for a given breakdown voltage VB can be

estimated. The actual values for VB and Rm.sp are determined by the actual physical parameters of

the device, such as the effective area (deterrnined by the ceIl pitch), SJ layer doping, thickness and

depth, gate and drain field plate lengths, field oxide height, etc. In the present work these parame-

ters and others were optimized to minimize Ron-,p while keeping VB at 150V. This was achieved

by reducing the n and p drift layer width and increasing the doping according to the RESURF

principle, thus reducing the effective device area resulting in a lower Ron-sp.

2.3 Process Design

The process was designed to be compatible with conventional SOI CMOS processes. The

starting material is an SOI wafer with n type top silicon layer 4pm thick, with (100) orientation

and a resistivity 2 Rcm. The resistivity is chosen to allow roorn for the integration of other



devices such as low voltage NMOSFETs and PMOSFETs.

A gate oxide thickness of 50nm was chosen and with a channel length of 0.8pm, the channel

doping was adjusted to yield a threshold voltage of 2SV, and ensure the elimination of any possi-

bilities of punchthrough. The minimum feature size in the process is 0.5pm. Specified process

parameters are summarized in Table 2.1. In order to achieve the required 150V breakdown volt-

age, a dnft region length of 8pm was used giving an effective SJ structure of length 7.5ym.

The n and p layer width, depth and doping were optimized (Appendix A) for minimum specific

on-resistance, and the layer width and thickness of 0.5pm and 3pm, respectively were chosen.

2.4 Process Description

The major process steps for the novel SJ Power LDMOST are listed in Table 2.2. The pro-

cess flow will be described with reference to Fig.2.4, which shows the cross sections of the device

at each processing step. This will be followed by a process summary given in Table 2.3.

Since the starting material is an n type SOI as shown in Fig.2.4(a), Mask #1 is used to form

the p well. The initial oxide is first grown, followed by an LPCVD oxide deposition to mask the

implant. Photoresist is deposited and pattemed with Mask #l as shown in Fig.2.4(bl-bz). After

stripping the photoresist, a thin layer of sacrificial oxide is grown. Two successive implants are

used to create the p well and prevent punchthrough. The first king a high energy (300KeV), high

dose (7x1013ions/cm2) boron implant, and the second is a boron implant of lesser energy

(100KeV) and lesser dose (2x 10" ions/cm2).~his is followed by a high temperature (1 100°C)

drive-in to obtain a deep p well as shown in Fig.2.4(cl-c2).

The SJ structure in the drift region is obtained by selective area growth (SAG). This is the

most crucial processing step and involves two masking steps with a high aspect ratio silicon etch-

ing in order to fonn very thin (0.5pm) n and p type silicon layers in the dnft region as demon-

strated in Fig.2.4(dl-g4). Mask #2 is used to pattern an oxide layer to mask the etching of a 3-pm

Lateral Superjunction Power MOSFETs - - --


Novel Superjunction Power LDMOSTs: Device Structure and Fabrication Prwess 2 1

Table 2.1: Specifieà Process Parameters for the SJ Power LDMOST

1 Buried Oxide Thickness 1 tbox l 2 1 Pm 1

Parameter

Starting SOI Film Thickness

Starting SOI Film Resistivity

1 n+ Gate Poly Thickness 1 t ~ o b 1 1 nm 1

Symbol

tsoi

Value

4

Unit

Pm --

1 n and p Layer Width 1 d,,=dp=d 1 0.5 I Cirn I

n+ Gate Poly Doping Concentration

Channel Length

Gate Oxide Thickness

Threshold Voltage

1 n and p Layer Thickness 1 tsj I I

2 n c m

N~~~

Lch

tgox I

vt h

L

Drift Region Length

1 Length of Low Dopped Drain at p layer 1 Lldd 1 0.5 1 Clrn 1

1 x 1 0 ~ ~

0.8

50

2.5

SJ Layer Length

Field Oxide Thickness

---- - 1 Length of Gate Field Plate

cm-3

Pm

nm

V

Ldr

-- -

pength of Drain Field Plate 1 Lm 1 l

Lsj

t fox

trench in the drift region as shown in Fig.2.4 (d,e,f,g), where the n and p layers are fabricated. A

chlorine based plasma is used to etch the silicon, masked by an oxide. A p type epitaxial layer is

first grown to fiIl the trench as shown in Fig.2.4(el-ez), then using a chlorine based plasma a high

aspect ratio (width:depth=l:6) silicon etch is performed masked by an oxide layer (which is pat-

temed with Mask #3), to open up trenches as shown in Fig.2.4 (fl-f2). The trenches are then

refilled with an n type epitaxial silicon to form the n layers. The resulting SJ structure is shown in

Fig.2.4 (gl-g4). Etch rate and time must be chosen so as to ensure equal n and p layer depths.

8


Pm

7.5

1.5

Pm

Pm


Table 2.2: Major Pmessing Steps for the Conventional and SJ LDMOSTs

Process Step For Conventional

LOCOS Formation and Definition of Active Areas

1 Gate Formation

1 P+ Body Contact Implant

1 N+ Source/Drain Implant

1 Meta1 Definition

Process Step For SJ LDMOST

P weH formation I l I Silicon Etch :O Open Drift Region for SJ Formation High Aspect Silicon Etch for the n Layer Formation

Gate Formation l 5 1

2

3

LOCOS Formation for the Field Oxide and Device Isolation

P+ ~ o d y Contact Implant I I

4

Metal Definition

N+ SourceIDrain Implant

Contacts Opening

After the n layer growth chemical-mechanical polishing (CMP) is carried out to ensure surface

planarity of the SJ structure.

The selectivity in the SAG mentioned above is obtained because of the different surface

properties of dielectnc masks such as SiOz and SiN4 and Si [4]. On the Si surface, the growth is

facilitated by surface catalytic reactions, an effect which does not occur on dielectric films. The

growth conditions are therefore chosen such that surface catalytic reactions are decisive for

growth. This is achieved by lowering the reactor pressure and the reagent partial pressure, short-

ening the transit time in the reactor, increasing the growth temperature and decreasing the mask

dimensions [4]. Heavily As- and B-doped (>5~10'~ions/cm~) epitaxial layers with very abnipt

dopant transition profiles and relatively uniform carrier distributions are required in the SJ struc-

ture and can be grown at 800°C [5].

The SAG requires a layer of silicon on top of the buried oxide to act as the seed for the

growth. For an SOI film thickness tmi, after etching off tsj in the drift region, a silicon film of

7

8



thickness tseed remains as the seed for the epitaxial growth as illustrated in Fig.2.4(dl). The aspect

ratio here is lower, compared to that implemented recently by Nitta [6]. This is an indication that

the SJ structure can be implemented in lateral devices, although the layer width and the entire SJ

structure are limited by the minimum feature sizes permitted by the technology, as well as by the

effects of lateral diffusion that could always arise due to high processing temperatures. In order to

rnaintain the integrity of the SJ structure, the thermal budget for subsequent processing steps after

the SJ formation must be properly managed, avoiding prolonged exposure of the wafer to high

temperatures ' . The p layers in the SJ structure in the drift region are made to be shorter than the n layers

such that they do not reach the drain end thus avoiding the creation of an abrupt junction with

steep concentration gradient where high electric fields could crowd resulting in breakdown volt-

age degradation. To achieve this, an n- region of length LIdd + Ld is left on the n+ drain end when

etching the drift region for the formation of the p layers, as shown in Fig.2.5(dl). This structure

achieves the same objectives as the low doped drain (LDD) technique in conventional MOSFETs.

Next, a thin oxide pad is thermally grown for stress relief and a layer of silicon nitride is

deposited and patterned with Mask #4 as shown in Fig.2.4 (hl-h2). A 1 -pm thick LOCOS oxide is

then grown by wet oxidation, to provide isolation between devices and also to serve as the field

oxide for the SJ LDMOST. After growing the LOCOS oxide, the nitride and thin oxide are chem-

ically etched. A sacrificial oxide is grown and a BF2 blanket implantation is performed to adjust

the threshold voltage of the device. The sacrificial oxide is then semoved by wet etching.

The gate oxide is grown at 950°C in an HCI ambient. The quality of the gate oxide is very

crucial in determining the performance of the device. To enhance the quality of the oxide, a small

amount of HCI is introduced into the thermal growth cycle to reduce the amount of the mobile

ionic charge in the oxide, thus increasing the stability of the oxide under thermal and bias stress.

1 . The implementation of the SJ structure as discussed above, requires highly spccialized equipment with limited availability. Nevertheless, the prcsent pace in the evolution of the technology will cnable fabrication of the structures in the ncarest future.


Novel Superjunction Power LDMOSTs: Device Structure and Fabrication Process 24 - - -

The growth of the gate oxide is immediately followed by a 0.5-pm phosphorus doped gate

polysilicon deposition. In order to define the polysilicon, a masking oxide is fint deposited by a

low pressure chemical vapour deposition (LPCVD) and pattemed with Mask #5. After stripping

off the photoresist, the wafer is loaded in the reactive ion etcher (RE). pretreated in freon plasma

for a short time (15 seconds) to remove any native oxide film that could have been formed on the

polysilicon surface and that could render the etching nonuniform. The polysilicon is then etched

in a chlorine-based plasma with the oxide as the mask, as shown in Fig.2.5 (il 42). The chlorine

based plasma is used since chlorine atoms etch SiO2 very slowly compared to the high etching

rates of heavily doped n type polysilicon [7-81. This very high selectivity enables the etching of

the polysilicon without affecting the gate oxide. It also enables the use of the Si02 layer on top of

the polysilicon to mask the etching. To ensure a nearly-vertical etch profile, BC13 is used as the

source of chlorine plasma to generate sidewaI1 polymerization thus preventing lateral etching [8].

A screen oxide is then deposited for boron implantation to form the p+ body contact at the

source region.The implant is masked by photoresist patterned with Mask #6 as shown in Fig.2.5

(i ,-jî) The resist is stripped and another one deposited and pattemed with Mask #7 as shown in

Fig.2.5 (kl-k2) for the arsenic implant to form the n+ source/drain regions. The p+ and n+ implants

are then annealed.

An LPCVD oxide of thickness 500nm is deposited for passivation. After densification,

Mask #8 is used to open the contact windows for the gate and source/drain contacts, as shown in

Fig.2.5 (1,-12). An 800nm aluminum film is sputtered on the entire wafer and pattemed with Mask

#9 as shown in Fig.2.5 (ml-m2). Aluminum deposition is followed by sintering in forming gas to

minimize contact resistance and interface-trapped charges.


Novei Supe junction Power LDMOSTs: Device Structure and Fabrication Process 25

Si sub

(a) Starting material: SOI Wafer

Cross Section Along A-B Cross Section Along C-D

n' SOI n' SOI

1 'l

sub i 'f

sub I 'l (bl) Mask #1: p well (b2) Mask #l : p well

Fig.2.4 Process Flow for the fabrication of the SJ LDMOSTs




p well

n' SOI n' SOI 0 sub I

f sub J f

(cl) After p well drive-in

sub

(dl) Mask #2: 1st Silicon Etch

I / n- SOI I

(c2) After p well drive-in

Seed for SAG

B" I n- SOI I

L f

sub

(d2) Mask #2: 1st Silicon Etch

n- SOI 0 sub L

f sub

(el) After growth of p layer by SAG (eZ) After growth of p layer by SAG

Fig.2.4 Process Flow for the fabrication of the SJ LDMOSTs (Continued)

- - - - - -




n- SOI 1

b sub b (fl) Mask #3: 2nd Silicon Etch

p well

(g ,), After growth of n layer by SAG (n layer)

p well

n' SOI

I nd SOI I

(f2) Mask #3: 2nd Silicon Etch

I n- SOI I

(g2), After growth of n layer by SAG

I n- SOI I

sub sub

(g3) After growth of n layer by SAG (p layer) (g4) After growth of n layer by SAG


Lateral Superj unction Power MOSFETs University of Toronto


Along A-B: Through the n layer Along A-B: Through the p layer

p well n' SOI

sub . . - -- -

(h ) Mask #4: LOCOS

p well n' SOI

- - - - -

(h2) Mask #4: LOCOS

p well n' SOI

sub L .I ( i I ) Mask #5: Gate Poly (i2) Mask #5: Gate Poly

p well n' SOI

p well n' SOI

sub

(j ,) Mask #6: p+ Body Contact (i2) Mask #6: p+ Body Contact




Along A-B: Through the n layer

n p well

n' SOI

Along A-B: Through the p layer

p well

k SU^ b (kl ) Mask #7: n+ SourceDrain (k2) Mask #7: n+ SourceDrain

1 n' SOI 1 1 n' SOI

sub J-+ .(

(1 1) Mask #8: Contacts Aluminum

p well n' SOI

(12) Mask #8: Contacts Aluminum

I n- SOI I

t sub

(ml) Mask #9: Metal (m2) Mask #9: Met al




Table 2.3: m e s s Summary for the SJ LDMOST

Initial pad oxide growth II Dry 05 1 10O0C, 20min., Wet 0 2 : 1 100°C, 5min

S tep

S tarting Material

CVD Oxide Deposition

Process Description

SOI wafer: 2 n c m , n type, (100)

II 2pm LPCVD undoped oxide, 425OC. Gas: SiH4 + O2

P Well Definition II Photolithography: Mask #1 (p well) Wet Etching of LPCVD Oxide: Buffered HF

Sacrificial Oxide growth

P Well Implant Boron Implantation: Dose= 1 x 10'~crn-~, Energy=3ûûKeV Boron Implantation: Dose=Sx 10'~crn-~, Energy= I SOKeV

P Well Drive-in -- -

Oxide Stripping II Wet Etching. Buffered HF

Protective Oxide Deposition II 500nm LPCVD undoped Si02, 425OC. Gas: SiH4 + O2

1st Si-Etch Definition II Photolithography: Mask #2 (1 st Silicon Etch) Wet Etching of LPCVD Oxide: Buffered HF

1st Si Etching II 3pm Si Etching: TMAH (IO%), 7S°C

1 st Epitaxial Growth Il Selective Area Growth(SAG): p type Epitaxial Si, IIoping=5. 1 x 10%rn-~, 8 m

Protective Oxide Removal II Wet Etching: Buffered HF

Protective Oxide Deposition II 500nm LPCVD undoped Sioz, 425OC, Gas: SiH4 + O2

2nd Si-Etch Definition II - -

Photolithography : Mask #3 (2nd Silicon Etch) RE Oxide: Gas = C2F6 + CHF3

2nd Si Etching II 3pm High Aspect Si Etching: TMAH (10%). 75OC RE Silicon: Gas = Cl2+ BCI,

2nd Epitaxial Growth Il Selective Area Growth(SAG): n type Epitaxial Si, Doping=S. 1 x 1 oi6cm9, 8ûû°C

- --

Protective Oxide Removal ~ e t ~ t c h i n ~ : Buffered HF

Stress Relief Oxide Growth II Dry 05 950°C, 30nm


Novel Supe rjunction Power LDMOSTs: Device Structure and Fabrication Process 3 1

S tep

Ni tride Deposition

Process Description

50nm LPCVD SiN4: 800°C, Gas = NH3 + SiHzC12

Oxide Deposition lûûnm LPCVD Oxide: 425OC, Gas = SiH4 + 0 2

LOCOS Definition Photolithography: Mask #4 (LOCOS) Wet Etching of LPCVD Oxide: Buffered HF

Nitride Etching Wet Etching: Phosphoric Acid, 1 80°C

Oxide Stripping Wet Etching: Buffered HF - --

LOCOS Growth - -

Wet 0 2 : 950°C, 1 pm

Nitride Stripping Wet Etching: Phosphoric Acid, 1 80°C

Sacrificial Oxide Growth Dry 0 2 : 950°C, 30nm

Threshold Voltage Adjustment

Sacrificial Oxide Stripping Wet Etching: Buffered HF

Gate Oxide Growth Dry 02: lûûû°C, 50nm, Gas = O2 + N2 + HCI

Gate Polysilicon Deposition 500nm LPCVD Polysilicon: 6WC, Gas = PHs + SiH4

Protective Oxide Deposition 500nm LPCVD undoped Sioz, 425OC, Gas: SiH4 + 0 2

Gate Poly Definition Photolithography: Mask #5 (Gate Poly) RIE Oxide: Gas = c2F6 + CHF, RIE Polysilicon: Gas = CI2 + BC13

Protective Oxide Stripping Wet Etching: Buffered HF

Screen Oxide Deposition 30nm LPCVD undoped SiO2, 42S°C, Gas: SiH4 + O2

p+ Body Contact Implantation Photolithography: Mask #6 (Body Contact) Boron Implantation: Dose=2x 1 O' Energy=25KeV

n+ Source/Drain Implantation Photolithography : Mask #7 (SourceDrain) Arsenic Implantation: Dose=5x 10 Energy= 1 30KeV

SourceîDrain Annealing - --- - - -

Annealing: 950°C, IOmin., Gas = N2

Screen Oxide Removal Wet Etching: 5% HF - - - --

Passivation Oxide Deposition - - - - - -- - - - -

500nm LPCVD Si02,4250C, Gas: SiH4 + 0 2


Novel Superjunction Power LDMOSTs: Device Structure and Fabrication Process

Metal Deposition

S tep

Contact Definition

1) Alurninurn Sputtering: AlSi. 800nrn

Process Description

Photolithography: Mask #8 (Contacts) RIE Oxide: Gas = C2F6 + CHF3

Metal Definition II Photolithography : Mask #9 (Metal) Wet Etching: H2S04 + HN03

II 420°C, 20min., Gas = H2 + N2

2.5 Process Simulation

The proposed SJ LDMOST is a 3-D structure. Due to the absence of a 3-D Process Simula-

tor, only 2-D simulations using TSUPREM-4 [9] were carried out for the cross sections along the

n layer given by the line A-A', and along the p layer given by the iine B-B', as shown in Fig.2.5, to

detemine the initial process parameters. The simulated structure for the cross section through A-

A' is shown in Fig.2.6 (a), and that through B-B' is shown in Fig.2.6 (b).

n+ su ba trate -- - -

Fig.2.S 3-D Structure of the SJ LDMOST


NoveI Supe junction Power LDMOSTs: Device Structure and Fabrication Process 33 -- - -

The doping profile in the channel region is shown in Fig.2.7 (a), that in the sourcddrain

region is given in Fig.2.7 (b). This gives a sheet resistance of about 20 in the sourceldrain regions.

Fig.2.7 (c) shows the doping profile across the device through the n layer, at the surface, while

Fig.2.7 (d) shows the doping profile across the device through the p layer. These two profiles

reveal a channel of length of about 0.8um and with graded doping starting from 1 x 10-"crn-~ at

the source end to about 6xl0%m" at the p wellldrift junction. The p well/drift junction is not

abrupt and has no steep concentration gradient, which could contribute to high electric field

crowding and causing breakdown voltage degradation. The vertical doping profiles in the n and p

layers are shown in Fig.2.7 (e) and Fig.2.7 (0, respectively, and indicate a fairly uniform doping

concentration of 5.1~10'~cm" within the layers with some considerably low distortion at the

junctions due to lateral diffusion and at the surface due to charge segregation into the field oxide.

The resistivity of the layers can therefore be considered to be uniform, estimated at O. 12SZcm for

the n and O.3Rcm for the p layers. This yields a sheet resistance of about 400Nsquare for the n

and 1ûûûNsquare for the p layers. Following from the appreciable uniformity of the n and p layer

doping obtained, it can be concluded that the SJ structure can be implemented as simulated.

Fig.2.6 TSUPREM-4 structures of the SJ LDMOST: a) across the n layer, b) across the p layer



(el (0 Fig.2.7 Doping Profiles of the SJ LDMOST: a) Channel Region, b) Source/Drain Region,

c) Across Device through n Layer, d) Across Device through p Layer, e) Vertically through the n Layer, and f) Vertically through the p Layer.


Novel Superjunction Power LDMOSTs: Device Structure and Fabrication Fkccss 35

2.6 Summary

This chapter presented the device structure, the design and the simulation of the fabrication

process. A process flow was designed for the fabrication of the novel SJ Power LDMOSTs, and

venfied using TSUPREM-4, a 2-D process simulator. The proposed process is compatible with

SOI CMOS processes.


Re ferences 36

References

[Il Infineon Technologies, "ICs for Communications-ISDN DC Converter Circuit," Data Sheet

04.99, 1999.

[Z] X.B. Chen and J.K.O. Sin, "Optimization of the Specific On-Resistance of the COOLMOS,'*

IEEE Transaction on Electron Devices, Vol. 48, pp. 344-348,2001.

[3] T. Fujihira, "Theory of Semiconductor Supe junction Devices," Japan Journal of Applied

Physics, Vo1.36, pp. 6254-6262, 1997.

[4] 1. Moerrnan, T.V. Caenegem, P.V. Daele, and P. Demeester, "MOVPE-Based Loçalized

Epitaxial Growth Techniques and its Applications," International Conference on Indium

Phosphide and Related Materials Proceedings, pp6 10-6 13, 1997.

[5] T.Y. Hsieh, K.H. Jung, D.L. Kwong, C.J. Hitzman, and R. Brennan, "Role of Dopant

Incorporation in Low-Temperature Si Epitaxial Growth by Rapid Thermal Processing

Chernical Vapour Deposition," IEEE Transaction on Electron Devices, Vol. 39, pp. 203-205,

19%.

[6] T. Nitta, T. Minato, M. Yano, A. Uenisi, M. Harada, and S. Hine, "Experimental Results and

Simulation Analysis of 250V Super Trench Power MCSFET (STM)," International

Symposium on Power Semiconductor Devices and ICs (ISPSD) Proceedings, pp. 77-80,2000.

[7] C.Y. Chang and S.M. Sze, ULSI Technology, The Mcgraw-Hill Companies, Inc. 1996.

[8] S.A. Campbell, The Science and Engineering of Microelectronic Fabrication, Oxford

University Press, New York, 1996.

(91 TSUPREM-4 User's Manual: Version 6.5. Technology Modeling Associates, Inc.

-- -


Novel Supe junction Power LDMOSTs: Device Simulation 37

CHAPTER 3

Novel Superjunction Power LDMOSTs: Device Simulation

3.1 Introduction

This chapter discusses the layout of the device and the results of the device simulations from

a 3-D device simulator DESSIS [ I l . Both the novel SJ Power LDMOST and a conventional SOI

LDMOST are simulated to compare their electrical characteristics. The trade-off between the spe-

cific on-resistance and breakdown voltage is demonstrated and the results compared with the sili-

con limit.

3.2 Mask Layout

The device structure of the novel SJ Power LDMOST was shown in Section 2.2 for a gate

width d=dJ2+dd2, where d,and dp are the widths of the n and p drift layers respectively. The full

device utilizes an interdigitated geometry, as shown in Fig.3.1, in order to increase the channel

width and increase the current handling capability of the device. The minimum line width used in

the design is 0.5p.m. The full test chip for the SJ Power LDMOST is presented in Appendix A

together with the layout design rules. A device that yields a OSA on-state current has a gate width

of 72.8mm and active area 0.83mm2 (0.9 lmm x 0.91mm). The device consists of eighty interdig-

itated SJ cells, each with a channel width 0.9 Imm. For a conventional LDMOST of equal current

rating, the active area is 2.75mm2 (1.66mm x 1.66mm). Therefore, the implementation of the

novel SJ Power LDMOST results in a 66% reduction in chip area. Fig. 3.2 shows the typical lay-

out pattern for a single cell SJ Power LDMOST.


Novel Superjunction Power LDMOSTs: Device Simulation 38

Gate Con tact

Meta1

n' SOI n+ p Well

P+ p Layer

n Layer

Fig.3.1 Top view of the SJ Power LDMOST with interdigitated geornetry

Fig.3.2 SJ Power LDMOST Single Cell Layout

p Well Implant

1 st Si Etching

2nd Si Etching

LOCOS Definition

GATE

n+ Implant

p+ Implant

CON

MET



3.3 Device Simulation

3.3.1 Oevice Simulation Setup

Fig.3.3 shows the cross section of a conventional SOI LDMOST and Fig. 3.4 shows the 3-D

structure of the SJ Power LDMOST as well as the cross sections through the n and p drift layers.

The device mesh was generated in ISE MESH [1] based on the proçess parameters obtained, in

Chapter 2, from TSUPREM-4, since the structure obtained in TSUPREM-4 could not be read into

the DESSIS simulator. Some simplifications were therefore made. The doping concentrations in

the SOI, polysilicon gate, and the n and p drift layers were assumed to be uniform profiles, while

the p well, the p+ body contact and the n+ source/drain regions were Gaussian profiles obtained by

Table 3.1: Device Simulation Parameters

Conventional SOI SJ Power LDMOST LDMOST I Parameter Unit

SOI Layer Thickness (tWi)

I - - -

Gate Oxide Thickness (tgox l )

n+ Source/Drain Implant dose (Nsm)

p+ Body Contact Implant dose (Nbc)

Buried Oxide Thickness (tbox)

n and p drift Layer width (d)

n and p drift Layer depth (tsj)

n Drift Layer Doping (Phosp, N,)

1 p Drift Layer Doping (Boron, Np)

1 Drift Region Length (Ldr)

Device Cell Pitch

Minimum Line width

. . . .


Novel Supe junction Powet LDMOSTs: Devicc Simulation 40

Fig. 3.3 Cross section of the conventional SOI LDMOST

1 n+ substrate -r

Fig.3.4 (a) 3-D structure of the SJ Power LDMOST, (b) Cross section through A-A', (c) Cross section through B-B'


Novel Supe rjunction Power LDMOSTs: Device Simulation 4 1

boron and arsenic implants respectively. The LOCOS and field oxides were described as regular

polygons. The device structural parameters are given in Table 3.1, alongside those of the conven-

tional SOI LDMOST.

The device structure generated by ISE MESH is shown in Fig.3.5. In order to expose the n

and p drift regions, the field oxide was removed. However. in the simulations this field oxide

(LOCOS oxide) is included as an undoped oxide region. The device electricd characteristics, sim-

ulated using a 3-D simulator ISE DESSIS [l], are presented in the following sections.

Source

Fig.3.5 A 3-D ISE MESH structure of the SJ Power LDMOST



3.3.2 Simulated Device Characteristics

On-State Static Characteristics

The transfer characteristics of the devices were obtained in the on-state and are shown in

Figs.3.6 (a) and (b), for the SJ Power LDMOST and the conventional SOI LDMOST respectively.

These are plots of nonnalized drain current h, per pm of channel width versus gate voltage Vg,

(ranging from OV to 20V) at Vds=O. IV. The threshold voltage V*, which can be approximated as

the extrapolated intercept of the linear portion of the Ids(Vg,) curve with the Vg, axis [2], was

obtained from Figs.3.6 (c) and (d), which are the enlargement of the transfer characteristics near

the origin. The threshold voltage is seen to be 2 . W for both devices. Given that the devices have

same gate length, gate oxide thickness and channel doping concentration, it is expected for their

threshold voltages to be identical.

The specific on-resistance %n,p, which is one of the most vital parameters of the power

transistor, can be estimated using the formula

where A is the device active area, R,,, is the device on-resistance, and hs is the drain current at

Vgs=20V obtained from the uansfer characteristics in Fig.3.6. The specific on-resistance for the

SJ Power L D M O S T is 1.65mS2cm2 as compared to 4.55m!2crn2 for the conventional SOI

LDMOST. These results show over 60% improvement in the performance of the novel SJ Power

LDMOST relative to that of the conventional SOI LDMOST. Since Vth for both devices is identi-

cal, the improvement on ROn,,, is due to the implementation of the SJ structure in the drift region.

Further improvement in RonSsp may be obtained by increasing the SJ depth and reducing the n and

p drift region widths. However, as demonstrated in Appendix B, the ROnmsp tends to saturate as the

n and p layer depth is increased. Also, smaller layrr widths lead to a trade-off between Ron.sp and

fabrication complexity.



Gare Voltage (V)

(b)

Gate Vo1tage (V)

(dl

Fig.3.6 Transfer Characteristics of (a) and (c) the SJ Power LDMOST and (b) and (d) Conven- tional SOI LDMOST (L= 1 Spm, W=O.Spm).

The output characteristics of the SJ device and the conventional SOI LDMOS device are

shown in Figs.3.7(a) and (b), respectively. These are plots of the drain current Ids against the drain

voltage Vds for values of gate voltage between OV and 10V. As seen from the figures, the SJ

device does not suffer from the quasi-saturation effect at higher gate and drain voltages experi-

enced by the conventional device.



O 5 10 1s 2 0 O 5 1 O 15 20

Drain Voltage (V) Drain Voltage (V)

Fig.3.7 Output Characteristics of (a) the SJ Power LDMOST and (b) Conventional SOI LDMOST (k 1 Spm, W=O.Sprn).

It is clear from this set of graphs that the SJ Power LDMOSTs offer superior DC characteristics as

compared to the conventional SOI LDMOSTs. In the case of the SJ device, the drain current satu-

rates at a drain voltage of about 4V as compared to 15V (Vgs=5V) for the conventional device.

Blocking characteristics

Blocking characteristics were obtained for off- and on-states operation. The potential distri-

bution in the SJ device at breakdown is shown in Fig.3.8 with field lines spacing of 7V. The field

oxide was removed in this diagram to reveal the wavy nature of the equipotential lines in the SI

structure due to the RESURF effect.

Off-state blocking characteristics for both SJ Power LDMOST and conventional SOI

LDMOST are shown in Fig.3.9, where the normalized drain current is plotted against the drain


NoveI Superjunction Power LDMOSTs: kv i ce Simulation 45

Fig.3.8 Equipotential lines in the SJ Power LDMOST at breakdown during off-state simulation

voltage with the gate eiectrode grounded (Vp,=ûV). Both devices show equal blocking capabili-

ties. The off-state breakdown voltages are 154V and 153V for the SJ Power LDMOST and the

conventional SOI LDMOST respectively.

The on-state blocking characteristics for both SJ Power LDMOST and conventional SOI

LDMOST are shown in Fig.3.10, where the normalized drain current is plotted against the drain

voltage with an applied voltage of 5V at the gate electrode. Again the SJ LDMOST exhibits a sig-

nificant advantage over the conventional device.

The plots in Figs.3.9(a) and 3.10(a) show a soft breakdown of the SJ device. This is due to

the parasi tic bipolar transistor present in the device structure.


Novel Supe rjunction Power LDMOSTs: Device Simulation 46

O 50 i i o 140

Drain Voltage (V) O 50 100

Drain Voltage (V)

Fig.3.9 Off-state blocking characteristics of (a) the SJ Power LDMOST and (b) Conventional SOI LDMOST (L= 1 Spm, W=O.Spm).

Drain Vofragc (V)

Fig.3.10 On-state btocking characteristics of (a) the SJ Power LDMOST and (b) Conventional

SOI LDMOST (L= 1 Spm, W=O.Spm).

- --- - -

Lateral Supe junction Power MOSFETs - - - - - - -


Novel Supe rjunction Power LDMOSTs: Device Simulation 47

Charge Ika~nsfer Characteristics

The charge transfer characteristics of the devices were simulated using ISE DESSIS [Il. The

simulated circuit is shown in Fig.3.11 [3], where a constant current is applied to the gate of the

device under test (DUT) to generate required charactenstics. The DUT is shown here simplified to

comprise of the gate-to-source capacitance Cg,, the gate-to-drain or Miller capacitance Cgd, the

drain-to-source capacitance Cds and the body diode Dg. A small resistor Rg is used to regulate the

gate current and a diode DFw is placed in parallel with the resistive load RL as the freewheeling

rectifier. The input voltage is provided by a voltage source Vdd.

- Fig.3.11 Simulation circuit for the switching performance of the LDMOST.

Fig.3.12 shows the charge transfer characteristics which are plots of gate voltage as a func-

tion of nonnalized gate charge per pm of gate length for both SJ Power LDMOST and the con-

ventional SOI LDMOST. Assuming the device is initially tumed off, it supports the full circuit



voltage Vdd and the gate voltage and drain currents are zero. As tum-on starts, Cg, starts to charge

and the gate-to-source voltage increases. When the gate reaches the threshold voltage, the drain

current starts to rise while the drain voltage starts to fa11 and Cg, continues to charge. At time cor-

responding to points B and B' in Fig.3.12, Cg, becomes fully charged and the drive current diverts

in its entirety into the Miller capacitance Cgd. With charge no longer being transferred to the gate-

to-source capacitor, the gate voltage remains constant for as long as the Miller capacitance is

k i n g charged by the drive circuit. This accounts for the plateau region BC and B'C' in Fig.3.12.

At the points C and C', the drain current reaches its maximum ID and the drain voltage reaches a

value equal to ID.&,(,,). The Miller capacitance is fully charged and the gate voltage is no longer

constrained by the drain current and begins to increase again.

I l I " " 1 '

Sc-1s Ic-14

Gate Charge (O

Fig.3.12 Charge Transfer Characteristics for (a) the SJ Power LDMOST and (b) the conventional LDMOST (L= 1 Spm, W=O.Spm).

The Cg, and Cgd charge constitute the total gate charge Qg required to switch the given volt-

age Vdd (in this thesis 130V) and current ID ( 8 . 8 ~ 10-'~). In order to allow for a safety margin, the

level of drive voltage needed at the gate is made to be greater than that which is just required to


Nobel Superjunction Power LDMOSTs: Device Simulation 49

switch the given current and voltage. In this work a gate drive voltage of 10V is considered, which

is about 4V higher than the voltage needed at the gate to completely switch on the devices. The

total gate charge will therefore be greater than the minimum corresponding to the point C and C'.

From the difference in length of the plateaus in Fig. 3.12, it is obsewed that the SJ Power

LDMOST has smaller Cgd. The total charge required to switch on the devices (at gate voltage of

10V) can be established from Fig.3.12 and equals 7 . 5 ~ IO-% (about 1.17nC for the full device at

a drain current of OSA) in the case of the SJ device, and 9 . 5 x 1 0 - ' ~ ~ (about 3.39nC for the full

device at a drain current of OSA) in the case of the conventional device. The related figure of

merit (FOM=Qg. &,) are 0.23Q.nC and 0.68R.nC respectively and indicate a 60% improvement

in switching converter efficiency for the proposed SJ-LDMOST.

Switching Characteristics

Figs.3.13 and 3.14 show the voltage and current waveforms respectively, for the SJ Power

LDMOSTs and conventional SOI LDMOST, during turn-on. The drain voltage for both devices is

seen to drop from the input value of 130V to a minimum of 10V, meanwhite the drain current rises

from zero and saturates at about 8 . 8 x 1 û 5 ~ within 0.4ns for the SJ devices and 0.711s for the con-

ventional devices.

The tum-off voltage and current waveforms are shown in Figs.3.1 S. and 3.16 respectively.

The drain voltage rises from 10V to the applied value within 0.511s for the SJ devices and 0.7ns for

the conventional devices. Meanwhile, the drain current falls from the maximum value to zero

within 0.3ns for the SJ devices and 0.55ns for the conventional devices.


Novel Supejunction Power LDMOSTs: Device Simulation 50

Fig.3.13 Turn-on Characteristics: Voltage Waveforrns for (a) the SJ Power LDMOST and (b) the Conventional LDMOST (Lr 1 Spm, W=û.Sprn).

Fig.3.14 Turn-on Characteristics: Current Waveforms for (a) the SJ Power LDMOST and (b) the Conventional LDMOST (L= 1 Spm, W=û.Spm).


Novel Superjunction Power LDMOSTs: Device Simulation 5 1

The (SI

t.5c-W

Time (SI

Fig.3.15 Tum-off Characteristics: Voltage Waveforms for (a) the SJ Power LDMOST and (b) the Conventional LDMOST (L= 1 Spm, W=û.Spm).

Fig.3.16 Tum-off Characteristics: Current Waveforms for (a) the SJ Power LDMOST and (b) the Conventional LDMOST (L= 1 Spm, W=OSpm).



3.4 Comparison with Conventional SOI RESURF LDMOST and Si Limit

In the previous section, the results for the SJ Power LDMOST and the conventional SOI

LDMOST were presented to allow for direct cornparison with each other. Since both devices were

designed to be of the same voltage class as confirrned by their off-state blocking characteristics

shown in Fig.3.9, and have identical threshold voltages as shown in Fig.3.6, any advantage of the

SJ Power LDMOST over the conventional LDMOST, in terms of the on-state performance, is due

to the implementation of the SJ structure in the drift region.

The trade-off between breakdown voltage and specific on-resistance for the SJ Power

LDMOSTs, the conventional SOI LDMOSTs and the Silicon Limit is illustrated in Fig.3.17. It

shows the much superior performance of the SJ Power LDMOSTs over that of the conventional

SOI LDMOST (simulated in this thesis) and that of a recently published SOI n-channel LDMOST

r41

Table 3.2 summarizes the important simulation results obtained for both devices, indicating

over 60% improvement in the specific on-resistance which leads to great reduction in on-state

*\ - Conv. SOI LDMOST

Published 1 SOI LDMOST [4] - -

V 5 2.5

. . . . . . .

O 1' 1.6 147 1.. 149 1 5 0 151 152 155 154 155 1 s 1 5 7 158 159 1 1 , 1 1 1 1 1 1 1 1 1 I l 1 6 0

Brrskdown Voltage. VB (V)

- YI .- YI

2 -

: 'E 1.5

Ii cn 1

Fig.3.17 Comparison of trade-off between hnSp and VB for the SJ and conventional SOI LDMOSTs.

- Silicon Limit SJ Power LDMOST



conduction losses and over 60% reduction in device active area and figure of merit (FOM) for the

SJ LDMOST as compared to its conventional counterpart.

Table 3.2: Cornparison of simulation results for the SJ and conventional devices.

Parameter

Current Handling Capabi li ty

- -

Breakdown Voltage VB

(Vgs=OV)

Specific On-resistance Ronq Wgs=20V)

Conventional SOI LDMOST Unit

Threshold Voltage Vth (Vds&. 1 V)

SJ Power LDMOST (L= 1.5pm,W=72.8mm)

Drain Voltage at Drain Current saturation Vds.sat ( V ~ S = ~ V )

Gate Charge Qg

(V,= 1 20v, vgs= WV)

Figure of Merit (FOM=Qg.Ron,

Device Active Area 1 mm2 1 0.83 1 2.75

3.5 Summary

In this Chapter the device layout for the novel SJ Power LDMOST and the simulation

results for the novel SJ Power LDMOSTs and the conventional SOI LDMOSTs were presented.

This included the on-state and off-state forward and blocking characteristics, and switching per-

formance. A cornparison was made between the performance of both devices and the trade-off

between the breakdown voltage and specific on-resistance of the proposed devices, that of the

conventional SOI LDMOSTs and the Silicon Limit.


References 54

References

[Il ISE TCAD Manuals, Integrated Systems Engineering AG, Release 6.0, Vo1.3 and 4, Zurich,

Switzerland, 1999.

[2] T. Taur and T.H. Ning, Fundarnentals of Modem VLSI Devices, Cambridge University Press,

New York, 1998.

131 T. Sakai, S. Matsumoto, I.J. Kim, T. Fukumitsu, and T. Yachi, "Potential of SOI Power MOS-

FETs as a Switching Device for Megahertz DClDC Converters," IEEE Power Electronics Spe-

cialists Conference (PESC) Proceedings, Vol. 1, pp. 450-456, 1994.

[4] P-M Zang and O-K Kwon, "A Simple Method for Formation of the BufTer Layer in n-Channel

LDMOS," IEEE International Conference on VLSI and CAD, pp. 469-472, 1999.


Conclusions 55

CHAPTER 4

Conclusions

In the quest to improve on the performance of the conventional power LDMOSTs in t e m s

of breakdown voltage, specific on-resistance and switching speed, a novel power LDMOST was

proposed in this thesis. The device uses the superjunction concept in the drift region of the

LDMOST and is implemented in SOI technology which offers simplified processing and high

density integration. The novel SJ Power LDMOST is proposed for a variety of applications,

including DC/DC converters and SLICs used in telecommunication switching systems.

A method of fabrication was proposed for the novel SJ Power LDMOST using selective area

growth (SAG) to implement the SJ structure in the drift region. However, this requires highly spe-

cialized equipment with limited availability. Albeit, the present pace in the evolution of the tech-

nology will enable fabrication of the structures in the future. The process flow was designed and

verifïed using 2-D process simulations in TSUPREM-4, and 3-D device simulations were carried

out using ISE DESSIS to optimize and verify the functionality of the device.

The simulated electricat characteristics of the novel device were compared with t hose of the

conventional SOI LDMOST. It was demonstrated for the 150-V class devices, that the novel SJ

Power LDMOST features a specific on-resistance of 1.65mS2cm2 (which breaks the Silicon

Limit) leading to a reduction in on-state power losses, an active device area of 0.83mm2 and a fig-

ure of ment (FOM=Qg.%,) of O.23SL.nC, al1 of which offer a 60% improvement over the conven-

tional SOI LDMOST devices.

Future work should include experimental implementation and characterization of the pro-

posed device as well as modifying the design to obtain devices with other voltage ratings in suit-

able automobile and display applications.


Appendix A 56

Appendix A

Test Mask and Layout Design Rules

A.I Layout Design Rules

The mask was design based on the 0.5pm minimum Iine width, necessitated by the high

aspect ratio silicon etching to form the SJ structure in the drift region of the SI-LDMOST. This

requires trenches of width 0.5p.m and depth 3pm. Fi@] illustrates the layout design rules fol-

lowed by a summary of the rules in Table Al.

p WELLIMPLANT LOCOS P+IMPLANT

1-1 IstSi ETCHING 0 GGATE "* CONTACT L i l

2nd Si ETCHING v7A n+ WDIMPLANT r i METAL

Fig.Al Illustration of Layout Design Rules


Appendix A 57

Table Ai Summary of Layout Design Rules

Mask

IMPLANT 1.2

1st Si

2nd Si ETCHING 3 -2

LOCOS

GATE

n+ S/D IMPLANT

Description

5.1 5.2 5.3

6.1 6.2

p+ iMPLANT

CONTACT

Dimension I (Pm)

7.1 7.2

8.1 8.2 8.3 8.4

Minimum width Minimum clearance to 1st silicon ETCHING 1 2.5 l

Minimum width Minimum clearance to n+ S IMPLANT

Minimum width Minimum spacing Minimum clearance to 1 st Si ETCHING (widths of al1 2nd Si ETCHING must lie within the 1st Si ETCHING)

Minimum width Minimum clearance to Drain CONTACT Minimum overlap of 1 st Si ETCHING Minimum clearance to 1 st Si ETCHING (under GATE)

Minimum width Minimum overlap of 1st Si ETCHING Minimum overlap of LOCOS

Minimum width Minimum clearance to 1 rt silicon ETCHING 1 A.5

Minimum width Minimum clearance to GATE --

Minimum width (on Source/Drain) Minimum width (on Gate) Minimum overlap of n+ S IMPLANT Minimum clearance to GATE

- - - - -

Minimum width Minimum overlap of CONTACT

A.2 Test Chip Description

A plot of the test chip layout is shown in Fig.Az. The test chip consists of eight blocks of test

elements (A-H): (A) This group includes twelve interdigitated SJ Power LDMOST structures, six

- -


Appendix A 58

Fig.A2 Test Chip Layout (A) SJ LDMOS and Conventional LDMOS Devices. (B) Structures for Sheet Resistance Measurement, (C) Critical Dimension Structures, (D) Structures for Oxide Thickness Measurement, (E) SJ and Planar Capacitors, (F) Alignment Marks, (G) Structures for Contact Resistance Measurement, (H) Structures for Etching.

of gate widths of IOpm, 20pm, 40pm. 80pm, 100pm, and 200pm. and effective gate length of

tive gate length of lpm; eight conventional LDMOST structures, four of gate widths of IOpm,


Appendix A 59

40pm, lûûprn, and 200pm, and effective gate length of 0.8pm, and the other four have gate

widths of 20prn, 80pm, lûûpm, and 2ûûjm, and effective gate length of 1pm. (B) structures for

the measurement of sheet resistance. (C) critical dimensions structures. (D) structures for oxide

thickness measurement.(E) two SJ capacitors and two planar capacitors. (F) alignment marks. (G)

structures for contact resistance measurement. (H) structure for monitoring etching.

-


APPENDIX B

Optimization of the Novel Superjunction Power LDMOSTs

Using the RESURF condition and the condition for charge balance as shown in equation

( 1 S), the doping AT' and Np in the n and p drift layers respective1 y, for the corresponding layer

width d is estimated. By varying the doping around the estimated value, the dependence of the

breakdown voltage on the layer doping was then obtained for the various pillar widths. as shown

in Fig. B I . This plot clearly indicates that with decrease in pillar width, the required layer doping

increases. It is also observed that the optimum breakdown voltage increases with decrease in the

SJ layer width. This pemits further decrease in n and p drift layer widths with corresponding

increase in the doping, resulting in very low specific on-tesistance. The SJ structures with drift

layer widths of OSpm and less, exhibit very low specific on-resistmce beyond the silicon limit as

illustrated in Fig. B2.

Fig. BI Dependence of Breakdown Voltage VB on n and p layer doping.


It is illustrated in Fig. Bg (a) that there is no significant change in the specific on-resistance

of the SJ devices for any increase in the SJ depths as from 3um. The breakdown voltage drops

drasticaily for SJ depths below 3pm as seen from Fig. Bj (b). It is for these reasons that the SJ

depth of 3pm was considered in this thesis as the optimum.

I I 1 1 1 1 1 125 130 135 140 145 1 5 0 155 160 165

Bmkdown Voltage VB (V)

Fig. B2 Trade-off relationships for the conventional SOI LDMOST (Conv), and for the SJ Power LDMOSTs with pillar width d of 0.2Sp.m, OSprn, 1 pm, 2pm, and 3pm.

Fig. B3 Plots of Specific On-resistance (a) and Breakdown Voltage (b) versus the SI layer depth.


NOTE TO USERS · resistance and in the gate charge on-resistance figure of ment (~~.&,=0.23n.n~)...

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