Hierarchical Fault Collapsing for Logic Circuits Thesis Advisor:Vishwani D. Agrawal Committee...

Hierarchical Fault Collapsing

for Logic Circuits

Thesis Advisor:Vishwani D. AgrawalCommittee Members:Victor P. Nelson,

Charles E. StroudDept. of ECE, Auburn University

Master’s DefenseRaja K. K. R. SandireddyDept. of ECE, Auburn University

Feb. 9, 2005 Raja Sandireddy: MS Defense 2

Outline• Introduction• Background

– Fault Equivalence and Fault Dominance– Functional collapsing– Hierarchical fault collapsing

• Fault Equivalence and Dominance definitions• Algorithm to find dominance relations• Results of functional collapsing• Hierarchical fault collapsing• Results of hierarchical fault collapsing• Conclusions and Future work


Introduction

DUT

Generate fault list

Collapse fault list

Generate test vectors

Fault model

Required fault coverage

Test Vector Generation Flow


Stuck-at Fault

• Single stuck-at fault model is the most popular model.

a0 a1

b0 b1

c0 c1

• Subscript fault notation: a0 means stuck-at-0 on line a.

a

b

c


Equivalence

Structural R-equivalence1: Two faults f1 and f2 are said to be R-equivalent if they produce the same reduced circuit graph [netlist] when faulty values are implied and constant edges [signals] are removed.

Functional F-equivalence1: Two faults f1 and f2 are said to be F-equivalent if they modify the Boolean function of the circuit in the same way, i.e., they yield the same output functions.

1 E. J. McCluskey and F. W. Clegg, “Fault Equivalence in Combinational Logic Networks,” IEEE Trans. Computers, vol. C-20, no. 11, Nov. 1971, pp. 1286-1293.


Structural Equivalence

a1 ≡ b1 ≡ c1 : Equivalence

Equivalent faults are indistinguishable at all primary outputs of the circuit.

a0 a1

b0 b1

c0 c1


Structural Dominance

A fault fi is said to dominate fault fj if the faults are equivalent with respect to test set of fault fj.

Dominance relationsa0 c0

b0 c0

a1 c1

a1 c1

b1 c1

b1 c1

a1 b1

a1 b1

Equivalence Relations

}}}

a1 ≡ c1

b1 ≡ c1

a1 ≡ b1

a0 a1

b0 b1

c0 c1

}a1 ≡ b1 ≡ c1


Fault Collapsing

• Equivalence Collapsing: It is the process of selecting one fault from each equivalence fault set.

• Dominance Collapsing: From the equivalence collapsed set, all the dominating faults are left out retaining their respective dominated faults.

For the OR gate, Equivalence collapsed set = {a0, b0, c0, c1}

Dominance collapsed set = {a0, b0, c1}

a0 a1

b0 b1

c0 c1


Collapse Ratio

Example: Full adder circuit.

Total faults: 60

Structural equivalence collapsed set2, 3 = 38 (0.63)

Structural dominance collapsed set3 = 30 (0.5)

||

||

faultsallofSet

faultscollapsedofSetRatioCollapse

2 Using Hitec: T. M. Niermann and J. H. Patel, “HITEC: A Test Generation Package for Sequential Circuits,” Proc. European Design Automation Conference, Feb. 1991, pp. 214-218.

3 Using Fastest: T. P. Kelsey, K. K. Saluja, and S. Y. Lee, “An Efficient Algorithm for Sequential Circuit Test Generation,” IEEE Trans. Computers, vol. 42, no. 11, pp. 1361-1371, Nov. 1993.


Dominance Graph

A 2-input OR gate and its dominance graph

a0 a1 b0 b1 c0 c1

a01 0 0 0 1 0

a10 1 0 1 0 1

b00 0 1 0 1 0

b10 1 0 1 0 1

c00 0 0 0 1 0

c10 1 0 1 0 1

Dominance Matrix

a

bc

Used for fault collapsing.

c1

b1 a1

c0

b0 a0


Two Algorithms: Equivalence and Dominance4

4 A. V. S. S. Prasad, V. D. Agrawal, and M. V. Atre, “A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets,” Proc. International Test Conf., Oct. 2002, pp. 391-397.

a0 a1 b0 b1 c0 c1

a01 0 0 0 1 0

a10 1 0 1 0 1

b00 0 1 0 1 0

b10 1 0 1 0 1

c00 0 0 0 1 0

c10 1 0 1 0 1

1

1

a0 b0 c0 c1

a01 0 1 0

b00 1 1 0

c00 0 1 0

c10 0 0 1

a0 b0 c1

a01 0 0

b00 1 0

c10 0 1

1

1

Algorithm Equivalence

Algorithm Dominance

1

1

1

1


Functional Equivalence

If faults in blocks F1 and F2 are equivalent, then Z ≡ 0.

F1

F2

Z

F0

F2

F1

Z

For the full-adder, functional equivalence collapsed set = 26 (0.43).{Structural equiv. = 38, Structural dom. = 30}


Functional Dominance5

F1

F0

F2

Z

If the fault introduced in block F1 dominates the fault in block F2, then Z is always 0.

5 V. D. Agrawal, A. V. S. S. Prasad, and M. V. Atre, “Fault Collapsing via Functional Dominance,” Proc. International Test Conf., 2003, pp. 274-280.

1

1

0

For the full adder, functional dominance collapsed set = 12 (0.20){Structural equiv. = 38, Structural dom. = 30, Functional equiv.= 23}


Hierarchical Circuits

Increasing complexity of designs is efficiently handled by hierarchical design process.

Hierarchical fault collapsing:• Create a library

– For smaller sub-circuits, exhaustive collapsing is done using the methods discussed earlier.

– For larger sub-circuits, use structural collapsing.

• At the top level, do structural collapsing using the library information to collapse the faults at lower levels.



Advantages:• Fault set computed once is reused for all instances of

the sub-circuit.• Exhaustive collapsing of faults in smaller circuits to

achieve smaller collapsed sets.• Faster collapsing.Theorem6: If two faults are functionally equivalent in a

sub-circuit Ci that is embedded in a circuit Cj then they are also functionally equivalent in Cj .

6 R. Hahn, R. Krieger, and B. Becker, “A Hierarchical Approach to Fault Collapsing,” Proc. European Design & Test Conf., 1994, pp. 171–176.

Note: Functional equivalence here means diagnostic equivalence as defined next.


Equivalence Definitions

• Fault Equivalence: Two faults are equivalent if and only if the corresponding faulty circuits have identical output functions.

For multiple output circuits, this is extended for two possible interpretations.

• Diagnostic Equivalence - Two faults of a Boolean circuit are called diagnostically equivalent if and only if the pair of the output functions is identical at each output of the circuit.

• Detection Equivalence - Two faults are called detection equivalent if and only if all tests that detect one fault also detect the other fault, not necessarily at the same output.

For single output circuits, diagnostic and detection equivalence mean the same.Diagnostic equivalence implies detection equivalence.


Examples to Demonstrate Detection Equivalence

Y

Z

A

B

c s-a-0

s-a-0 The faults c0 and Y0 are detection equivalent faults, but not diagnostic equivalent.

s-a-1

s-a-1P

Q

R

For the full adder, diagnostic equivalence collapsed set = 26 (0.43), detection equivalence collapsed set = 23 (0.38)

{Structural equiv. = 38, Structural dom. = 30, Functional equiv.= 26, Functional dom.= 12}

s-a-1

The faults P1, Q1 and R1 are detection equivalent faults, but not diagnostic equivalent.


Dominance Definitions

• Fault Dominance7 - A fault fi is said to dominate fault fj if (a) the set of all vectors that detects fault fj is a subset of all vectors that detects fault fi and (b) each vector that detects fj implies identical values at the corresponding outputs of faulty versions of the circuit.

Conventionally dominance is defined as:• A fault fi is said to dominate fault fj if the faults are equivalent

with respect to test set of fault fj.• If all tests of fault fj detect another fault fi, then fi is said to

dominate fj.7 J. F. Poage, “Derivation of Optimum Tests to Detect Faults in Combinational Circuits", Proc. Symposium on Mathematical Theory of Automata, 1962, pp. 483-528.


Dominance Definitions Contd.

For multiple output circuits, the two possible interpretations of dominance:

• Diagnostic dominance - If all tests of a fault f1 detect another fault f2 on the exact same outputs where f1 was detected, then f2 is said to diagnostically dominate f1.

• Detection dominance - If all tests of a fault f1 detect another fault f2, irrespective of the output where f1 was detected, then f2 is said to detection dominate f1 .

Diagnostic dominance implies detection dominance.

For the full adder, diagnostic dominance collapsed set = 12 (0.2) detection dominance collapsed set = 6 (0.1)

{Structural equiv. = 38, Structural dom. = 30, Diagnostic equiv.= 26, Detection equiv.= 23}


Functional Dominance

F0

F0

F1

Faults in this circuit are checked for redundancy

Fault introduced in this circuit

D or D

10

0D or D


Algorithm to Find All Dominance Relations

1. Select a fault from the given circuit and build the circuit as shown in previous slide with the fault introduced in the bottom block whose function is F1.

2. Check for redundant faults in the top block, F0.3. For each redundant fault found in step 2, a 1 is placed in

the dominance matrix at the intersection of the row corresponding to the redundant fault and the column corresponding to the fault in the bottom block. Thus, we obtain all values of a column of the dominance matrix in a single iteration.

4. Go to step 1 until there is no fault left.5. Now we will have the dominance matrix with all the

functional dominance relations included.


Algorithm Contd.

6. Transitive closure of the dominance matrix is computed, which is then reduced using algorithm equivalence4. This reduced matrix still consists of dominance relations within an equivalence collapsed set of faults.

7. If dominance collapsing is required, then the reduced matrix of the previous step is further reduced according to algorithm dominance4.

For simplicity, the redundant faults of the given circuit (stand-alone F0) are not considered in step 1.

4 A. V. S. S. Prasad, V. D. Agrawal, and M. V. Atre, “A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets,” Proc. International Test Conf., Oct. 2002, pp. 391-397.


For Multiple Output Circuits

F0

F0

F1

Detection collapsing

For a circuit with 2 outputs, the schemes used to find the dominance relations:

Diagnostic collapsing

F0

F0

F1


Results: Functional Collapsing

Circuit Name

All Faults

Number of Collapsed Faults (Collapse Ratio)

Structural Functional5

Functional Collapsing – New Results

Diagnostic Criterion

Detection Criterion

Equiv.2 Dom.3 Equiv. Dom. Equiv. Dom. Equiv. Dom.

XOR 2416

(0.67)

13

(0.54)

10

(0.42)

4

(0.17)

10

(0.42)

4

(0.17)

10

(0.42)

4

(0.17)

Full Adder

6038

(0.63)

30

(0.50)

26

(0.43)

14

(0.23)

26

(0.43)

12

(0.20)

23

(0.38)

6

(0.10)

8-bit Adder

466290

(0.62)

226

(0.49)

194

(0.42)

112

(0.24)

194

(0.42)

96

(0.21)

191

(0.41)

48

(0.10)

ALU

(74181)502

301

(0.60)

248

(0.49)-- --

253

(0.50)

155

(0.31)

234

(0.47)

92

(0.18)2 Using Hitec (obtained from Univ. of Illinois at Urbana-Champaign)3 Using Fastest (obtained from Univ. of Wisconsin at Madison)5 Agrawal, et al. ITC’03


Results: Test Vectors

Circuit

No. of test vectors (no. of target faults)

Structural Functional – New Results

Equivalence DominanceDiagnostic Dominance

Detection Dominance

Full Adder 6 (38) 6 (30) 7 (12) 6 (6)

8-bit Adder 33 (290) 28 (226) 32 (96) 28 (48)

ALU 44 (293) 44 (240) 39 (147) 38 (84)

Test vectors obtained using Gentest ATPG8.

8 W. T. Cheng and T. J. Chakraborty, “Gentest: An Automatic Test Generation System for Sequential Circuits,” Computer, vol. 22, no. 4, pp. 43–49, April 1989.



Line Oriented Structural Fault Collapsing9:

Type of gate the line feeds into

Put this (these) fault (s) on the line

INV, BUF None

OR, NOR s-a-0

AND, NAND s-a-1

Sub-circuit, Fanout s-a-0, s-a-1

Primary Output s-a-0, s-a-1

9 M. Nadjarbashi, Z. Navabi, and M. R. Movahedin, “Line Oriented Structural Equivalence Fault Collapsing,“ IEEE Workshop on Model and Test, 2000.



Algorithm to find the dominance matrix and its transitive closure:1. Consider a fault (f1) stuck-at-b at the input of a Boolean gate.2. If the gate is of inverting type (NOT, NOR, NAND), then invert b.3. If the equivalent set has s-a-b on this gate output, say f2, then return this

fault – place a 1 at the intersection of the row corresponding to f1 and column corresponding to f2 – use Update10 for transitive closure. End.

4. Move one gate forward towards the primary output and go to step 2.

M

G10 1

1

1

11

1 00

0

0

0 G2 G3

G4

A

B

C

0

10 K. K. Dave, V. D. Agrawal, and M. L. Bushnell, “Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies,” Proc. 18th International Conf. VLSI Design, Jan. 2005, pp. 723-729.


Collapsed Information File as Saved in Library

a

b

g1

g2

g3

Circuit M

$INPUTs:a 1 2b* 3 4

$OUTPUTs:g3 12 13

$TOTAL: 14

$FAULTs:g1(0) 5g1(1) 6g2(1) 9

$RELATIONs:1: 4 5 12 02: 6 13 03: 9 13 04: 1 5 12 05: 1 4 12 06: 2 13 09: 13 012: 1 4 5 013: 0

$REDUNDANT:g1(b,0) 14 M

G1

G2 G3G4

AB

CFlat Hierarchical

Equivalence 12 11

Dominance 8 8

Collapsed fault set sizes


Results: Collapse Ratios

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

FullAdder

64-bitAdder

1024-bitAdder

c432 c499

Comparison of fault collapse ratios

Structural Equiv.

Hierarchical Equiv.(diagnostic)

Structural Dom.

Hierarchical Dom.(diagnostic)

Total Faults:Full adder: 60, 64-bit Adder: 3714, 1024-bit Adder: 59394, c432:1116, c499:2646

Detection collapsing can be used only for those sub-circuits whose outputs are POs at the top-level.


CPU Time (s) for Different Sections of Our Program for Flattened Circuits

674.11.631.49667.44096-bit

26763.733.4326628192-bit

166.40.840.74163.12048-bit

39.90.410.3638.31024-bit

9.380.200.178.60512-bit

2.490.090.092.05256-bit

0.750.050.050.54128-bit

0.240.030.020.1364-bit

TotalDominance Collapsing

Equivalence Collapsing

Flat Structure Processing

CPU time clocked on a 360MHz Sun UltraSparc 5_10 machine with 128MB memory.


CPU Time (s) for Different Sections of Our Program for Flattened Circuits


CPU Time (s) of Different Commands of Hitec for Fault Collapsing

125821010454096-bit

32650.4275.12048-bit

77.712.264.91024-bit

19.53.1516.0512-bit

5.090.884.0256-bit

1.470.341.03128-bit

0.570.160.3264-bit

TotalEquivalence

Collapsing (equiv)Structure

Processing (level)


Comparison of CPU Times (s) Taken by Hitec and Our Program


CPU Time (s) of Different Sections of Our Program for Hierarchical Circuits

14.33.10.379.254096-bit

50.26.00.7940.18192-bit

4.721.520.202.102048-bit

1.820.730.080.551024-bit

0.810.360.040.17512-bit

0.390.190.020.05256-bit

0.190.130.020.03128-bit

0.100.070.010.0164-bit

TotalLibraryEquiv.

+Dom.CollapsingStructure

Processing


CPU Time (s) of Our Program for Hierarchical and Flattened Circuits


CPU Time (s) Improvement by Hierarchy

Hierarchical circuitFlattened circuit

16.635.1674.112584096-bit

55.0127.22676--8192-bit

4.8010.3166.43262048-bit

2.313.6039.977.71024-bit

1.051.529.3819.5512-bit

0.490.692.495.09256-bit

0.240.320.751.47128-bit

0.100.160.240.5764-bit

Multi-levelTwo-levelOur ProgramHitec


CPU Time (s) for Hierarchical Collapsing


Conclusions• Diagnostic and detection collapsing should be used only with

smaller circuits.• Collapse ratios using detection dominance collapsing is about

10-20%.• For larger circuits described hierarchically, use hierarchical

fault collapsing.• Hierarchical fault collapsing:

– Better (lower) collapse ratios due to functional collapsed library– Order of magnitude reduction in collapse time.

• Smaller fault sets:– Fewer test vectors– Reduced fault simulation effort– Easier fault diagnosis.

• Use caution when using dominance collapsing!!

Dom. Collapsed Set Size (Collapse Ratio)

CPU s

Flat Hierarchical Flat Hier.

229378 (0.48) 98304 (0.21) 2676 55

8192-bit Adder


Future Work

• Generate fault collapsing library of standard cells (Mentor Graphics, etc.)

• Incorporate VHDL or Verilog input for hierarchical netlist.

• Efficient redundancy detection program.• Customized ATPG to obtain minimal test vector set.• Extend the work for sequential circuits.• Extend the work for other fault models.


THANK YOU

Hierarchical Fault Collapsing for Logic Circuits Thesis Advisor:Vishwani D. Agrawal Committee...

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