Independence Fault Collapsing

Aug.13, 2005 VDAT05: Doshi and Agrawal 1

Independence Fault Collapsing

Auburn University, Department of Electrical and Computer Engineering Auburn, AL 36849, USA

Alok S. Doshi (Speaker)Vishwani D. Agrawal


Outline

• Motivation

• Fault Classification

• Independence Graph and Matrix

• Independence Fault Collapsing

• Concurrent Test Generation

• Conclusions and Future Work


Motivation

ATPG Tests

Hitec1 10

Fastest2 7

Gentest3 7

1 T. M. Niermann and J. H. Patel, “HITEC: A Test Generation Package for Sequential Circuits,” Proc. European Design Automation Conference, Feb. 1991, pp. 214-218.2 T. P. Kelsey, K. K. Saluja, and S. Y. Lee, “An Efficient Algorithm for Sequential Circuit Test Generation,” IEEE Trans. Computers, vol. 42, no. 11, pp. 1361-1371, Nov. 1993.3 W. T. Cheng and T. J. Chakraborty, “Gentest: An Automatic Test Generation System for Sequential Circuits,” Computer, vol. 22, no. 4, pp. 43–49, April 1989.

C17 - ISCAS85 Benchmark Circuit

a

b

cd

e

x

y

Minimum 4


Fault Classification

T(F 1 )

T(F 1 ) T(F 1 )

T(F 2 )

T(F 2 ) T(F 2 )

(a) F 1 and F 2 ar e e qui val e nt . (b) F 1 do m i nate s F 2 .

(c ) F 1 and F 2 ar e i nde pe nde nt . (d) F 1 and F 2 ar e c o nc ur r e nt l y te s tabl e .

T(F 1 ) = T(F 2 )


Definitions

Independent Faults4:Two faults are independent if and only if they cannot be detected by the same test vector.

Concurrently-Testable Faults:Two faults that neither have a dominance relationship nor are independent, are defined as concurrently-testable faults.

4 S. B. Akers, C. Joseph, and B. Krishnamurthy, “On the role of Independent Fault Sets in the Generation of Minimal Test Sets,” in Proc. International Test Conf., 1987, pp. 1100-1107.


Structural Independences

sa1sa1

sa1

sa1

sa1

sa1

sa1

sa0

sa0

sa0

sa0

sa0

sa0

sa0 sa0

sa0

sa0

sa1

sa1

sa1


Implied Independences

Equivalence implied independence:If two faults are equivalent then all faults that are independent of one fault are also independent of the other fault.

Dominance implied independence:If one fault dominates a second fault then all faults that are independent of the first fault are also independent of the second fault.


Functional Independences

C UTC 0

C UTC 0

C UT(Fi)C i

C UTC 0

C UTC 0

C UT(Fi)C i

Prim a ryI n pu ts

Prim a ryI n pu ts

Prim a ryO u tpu tsPrim a ry

O u tpu t

R e du n da n t fa u lt s Fj a rein de pe n de n t o f F i

R e du n da n t fa u lt s Fj a rein de pe n de n t o f F i

(a ) F in din g a ll fa u lt s in de pe n de n t o f F i in a s in g le o u tpu t c ircu it . (b) F in din g a ll fa u lt s in de pe n de n t o f F i in a m u lt iple o u tpu t c ircu it .


Example Circuit2-1

4-1

1-1

6-1

8-1

7-13-1

9-1

5-1

10-1

11-1

a

b

cd

e

x

y

C17 - ISCAS85 Benchmark Circuit

5 R. K. K. R. Sandireddy and V. D. Agrawal, “Diagnostic and Detection Fault Collapsing for Multiple Output Circuits," in Proc. Design, Automation and Test in Europe (DATE) Conf., Mar. 2005, pp. 1014 - 1019.


Independence Matrix and Graph

F 1 2 3 4 5 6 7 8 9 10 11

1 0 1 1 1 1 1 0 0 1 0 1

2 1 0 0 1 1 0 1 0 0 0 1

3 1 0 0 0 1 1 1 1 0 1 1

4 1 1 0 0 1 0 1 0 0 0 1

5 1 1 1 1 0 0 0 1 1 1 0

6 1 0 1 0 0 0 1 1 1 0 0

7 0 1 1 1 0 1 0 1 1 0 0

8 0 0 1 0 1 1 1 0 1 1 1

9 1 0 0 0 1 1 1 1 0 1 1

10 0 0 1 0 1 0 0 1 1 0 1

11 1 1 1 1 0 0 0 1 1 1 0

1 2 3 4 5

6 7 8 9 1 0

11


Clique

A clique is defined as a fully-connected subgraph, i.e., a subgraph in which every node is connected to every other node.

A lower bound on the number of tests required to cover all faults of an irredundant combinational circuit is given by the size of the largest clique of the independence graph.


Cliques

1 2 3 4 5

6 7 8 9 1 0

11

1 2 3 4 5

6 7 8 9 1 0

11


Degree of Independence

Degree of Independence:

This is the number of edges attached to the fault node and is computed for the ith fault by adding all the elements of either the ith row or the ith column of the independence matrix.

DI (ith fault) = Σ xij = Σ xji NN

j=1 i=1


Degree of IndependenceFault 1 2 3 4 5 6 7 8 9 10 11 DI

1 0 1 1 1 1 1 0 0 1 0 1 7

2 1 0 0 1 1 0 1 0 0 0 1 5

3 1 0 0 0 1 1 1 1 0 1 1 7

4 1 1 0 0 1 0 1 0 0 0 1 5

5 1 1 1 1 0 0 0 1 1 1 0 7

6 1 0 1 0 0 0 1 1 1 0 0 5

7 0 1 1 1 0 1 0 1 1 0 0 6

8 0 0 1 0 1 1 1 0 1 1 1 7

9 1 0 0 0 1 1 1 1 0 1 1 7

10 0 0 1 0 1 0 0 1 1 0 1 5

11 1 1 1 1 0 0 0 1 1 1 0 7

DI 7 5 7 5 7 5 6 7 7 5 7


Similarity Metric

Similarity Metric:

This is a measure defined for a pair of faults that determines how similar they are in their independence and concurrent-testability with respect to the entire fault set of the circuit.

SIM (fault-i, fault-j) = Nxij + (1-xij) Σ |xik-xjk|N

k=1


Similarity Metrics

Fault 1 2 3 4 5 6 7 8 9 10 11

1 0 11 11 11 11 11 3 4 11 4 11

2 11 0 4 11 11 6 11 6 4 6 11

3 11 4 0 4 11 11 11 11 0 11 11

4 11 11 4 0 11 6 11 6 4 6 11

5 11 11 11 11 0 4 3 11 11 11 0

6 11 6 11 6 4 0 11 11 11 4 4

7 3 11 11 11 3 11 0 11 11 5 3

8 4 6 11 6 11 11 11 0 11 11 11

9 11 4 0 4 11 11 11 11 0 11 11

10 4 6 11 6 11 4 5 11 11 0 11

11 11 11 11 11 0 4 3 11 11 11 0


Independence CollapsingFault 1 3 5 8 9 11 7 2 4 6 10 DI

1 0 1 1 0 1 1 0 1 1 1 0 7

3 1 0 1 1 0 1 1 0 0 1 1 7

5 1 1 0 1 1 0 0 1 1 0 1 7

8 0 1 1 0 1 1 1 0 0 1 1 7

9 1 0 1 1 0 1 1 0 0 1 1 7

11 1 1 0 1 1 0 0 1 1 0 1 7

7 0 1 0 1 1 0 0 1 1 1 0 6

2 1 0 1 0 0 1 1 0 1 0 0 5

4 1 0 1 0 0 1 1 1 0 0 0 5

6 1 1 0 1 1 0 1 0 0 0 0 5

10 0 1 1 1 1 1 0 0 0 0 0 5

DI 7 7 7 7 7 7 6 5 5 5 5


Independence Collapsing

1

3

51,8

3,9

5,115,11,7

3,9,2 44,64,6,10

11

11

4 11

0

03

4 6

F 1 3 5 8 9 11 7 2 4 6 10

1 0 11 11 4 11 11 3 11 11 11 4

3 11 0 11 11 0 11 11 4 4 11 11

5 11 11 0 11 11 0 3 11 11 4 11

8 4 11 11 0 11 11 11 6 6 11 11

9 11 0 11 11 0 11 11 4 4 11 11

11 11 11 0 11 11 0 3 11 11 4 11

7 3 11 3 11 11 3 0 11 11 11 5

2 11 4 11 6 4 11 11 0 11 6 6

4 11 4 11 6 4 11 11 11 0 6 6

6 11 11 4 11 11 4 11 6 6 0 4

10 4 11 11 11 11 11 5 6 6 4 0

Similarity index for fault F for each existing node i:Max. SIM (F, kth fault of node i) where k = 1…..K, and K is number of faults in node i.


Concurrent test generation for C17

Fault Targets Test

(a b c d e)

1,8 10010

3,9,2 01111

5,11,7 X1010

4,6,10 10101

2-14-1

1-1

6-1

8-1

7-13-1

9-1

5-1

10-1

11-1

a

b

cd

e

x

y


Results (ALU – 74181)Node Number of faults Test vectorsno. Total Targeted Detected from Cumulative

this

nodeothernodes

coverage

1 5 5 5 6 11 010011110100012 3 3 3 2 16 010011111101013 8 7 7 3 26 010111010000014 3 3 3 3 32 101x01010100005 5 3 3 4 39 101001010110006 6 6 6 2 47 111110000010017 7 4 4 3 54 111000001000008 14 11 11 1 66 111001101010119 8 6 5 1 72 10010100110101

10 8 4 3 2 77 1x10101110110011 8 3 3 1 81 0101000010110012 9 2 2 1 84 1x011110001100


Conclusions and Future Work

• Faults are reclassified into four classes:• Equivalent• Dominant• Independent• Concurrently-testable (also called compatible in the literature)

• A new fault collapsing algorithm based on Independent Faults is introduced. This algorithm frequently collapses the graph into a minimal clique.

• This work motivates the need for ATPG algorithms for concurrent fault targets.

• The problem of completely determining all edges of the independence graph is complex. The algorithm needs to be extended for incompletely – specified

independence graph.


Thank You!

Independence Fault Collapsing

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