Independence Fault Collapsing and Concurrent Test Generation Thesis Advisor: Vishwani D. Agrawal...

Independence Fault Collapsing and Concurrent Test Generation

Thesis Advisor: Vishwani D. AgrawalCommittee Members: Victor P. Nelson, Charles E. Stroud

Dept. of ECE, Auburn UniversityJanuary 25, 2006

Master’s DefenseAlok S. Doshi

Dept. of ECE, Auburn University

Jan. 25, 2006 Alok Doshi: MS Defense 2

Outline• Introduction

– Problem Statement– Motivation– Background

• Contributions of this Research– Fault Classification and Independent Faults– Independence Fault Collapsing– Concurrent Test Generation– Simulation Based Techniques– Results

• Conclusions and Future Work


Problem Statement

To find a minimal test vector set to detect all single stuck-at faults in a combinational circuit.


MotivationATPG Tests

Hitec1 10

Fastest2 7

Gentest3 7

Atalanta4 6-9

1 T. M. Niermann and J. H. Patel, “HITEC: A Test Generation Package for Sequential Circuits,” Proc. European Design Automation Conference, Feb. 1991, pp. 214-218.2 T. P. Kelsey, K. K. Saluja, and S. Y. Lee, “An Efficient Algorithm for Sequential Circuit Test Generation,” IEEE Trans. Computers, vol. 42, no. 11, pp. 1361-1371, Nov. 1993.3 W. T. Cheng and T. J. Chakraborty, “Gentest: An Automatic Test Generation System for Sequential Circuits,” Computer, vol. 22, no. 4, pp. 43–49, April 1989.4H. K. Lee and D. S. Ha, “Atalanta: An Efficient ATPG for Combinational Circuits,” Tech. Report 93-12, Dept. of Electrical Eng., Virginia Poly. Inst. and State Univ., Blacksburg, Virginia, 1993.

C17 - ISCAS85 Benchmark Circuit

a

b

cd

e

x

y

Minimum 4


Motivation

4-bit ALU (74181)

ATPG Tests

Gentest 42

Fastest 37

Hitec 36

Atalanta 23-39

Minimum 12


Background

v1v2v3. . .T(F1) T(F2)

Problem of finding a minimal test:• Static compaction cannot guarantee optimality.• Dynamic compaction is complex.

• Solution: Target both faults F1 and F2 at the same time to find a single test.

Test set for fault F1 Test set for fault F2


Fault Classification

F1 and F2 are equivalent. F1 dominates F2.

F1 and F2 are independent. F1 and F2 are concurrently testable.

T(F1) = T(F2)

T(F1)

T(F2)

T(F1) T(F2) T(F2)T(F1)


Definitions

Independent Faults5:Two faults are independent if and only if they cannot be detected by the same test vector.

Concurrently-Testable Faults:Two faults that neither have a dominance relationship nor are independent, are defined as concurrently-testable faults.

5 S. B. Akers, C. Joseph, and B. Krishnamurthy, “On the role of Independent Fault Sets in the Generation of Minimal Test Sets,” in Proc. International Test Conf., 1987, pp. 1100-1107.


Structural Independences

sa1sa1

sa1

sa1

sa1

sa1

sa1

sa0

sa0

sa0

sa0

sa0

sa0

sa0 sa0

sa0

sa0

sa1

sa1

sa1


Implied Independences

Equivalence implied independence:If two faults are equivalent then all faults that are independent of one fault are also independent of the other fault.

Dominance implied independence:If one fault dominates a second fault then all faults that are independent of the first fault are also independent of the second fault.


Functional Independences

C UTC 0

C UTC 0

C UT(Fi)C i

C UTC 0

C UTC 0

C UT(Fi)C i

Prim a ryI n pu ts

Prim a ryI n pu ts

Prim a ryO u tpu tsPrim a ry

O u tpu t

R e du n da n t fa u lt s Fj a rein de pe n de n t o f F i

R e du n da n t fa u lt s Fj a rein de pe n de n t o f F i

(a ) F in din g a ll fa u lt s in de pe n de n t o f F i in a s in g le o u tpu t c ircu it . (b) F in din g a ll fa u lt s in de pe n de n t o f F i in a m u lt iple o u tpu t c ircu it .


Example Circuit2-1

4-1

1-1

6-1

8-1

7-13-1

9-1

5-1

10-1

11-1

a

b

cd

e

x

y


6 R. K. K. R. Sandireddy and V. D. Agrawal, “Diagnostic and Detection Fault Collapsing for Multiple Output Circuits," in Proc. Design, Automation and Test in Europe (DATE) Conf., Mar. 2005, pp. 1014 - 1019.


Independence Matrix and Graph

1 2 3 4 5

6 7 8 9 1 0

11


F 1 2 3 4 5 6 7 8 9 10 11

1 0 1 1 1 1 1 0 0 1 0 1

2 1 0 0 1 1 0 1 0 0 0 1

3 1 0 0 0 1 1 1 1 0 1 1

4 1 1 0 0 1 0 1 0 0 0 1

5 1 1 1 1 0 0 0 1 1 1 0

6 1 0 1 0 0 0 1 1 1 0 0

7 0 1 1 1 0 1 0 1 1 0 0

8 0 0 1 0 1 1 1 0 1 1 1

9 1 0 0 0 1 1 1 1 0 1 1

10 0 0 1 0 1 0 0 1 1 0 1

11 1 1 1 1 0 0 0 1 1 1 0


Independence Fault Collapsing

• The aim of independence fault collapsing is to collapse the independence graph into a fully-connected graph such that all or most faults in a given node will have a single test.

• These nodes will then serve as fault targets for Automatic Test Pattern Generation (ATPG).


Cliques

1 2 3 4 5

6 7 8 9 1 0

11

1 2 3 4 5

6 7 8 9 1 0

11


Clique

A clique is defined as a fully-connected subgraph, i.e., a subgraph in which every node is connected to every other node.

A lower bound on the number of tests required to cover all faults of an irredundant combinational circuit is given by the size of the largest clique of the independence graph.


Degree of Independence

Degree of Independence:

This is the number of edges attached to the fault node and is computed for the ith fault by adding all the elements of either the ith row or the ith column of the independence matrix.

DI (ith fault) = Σ xij = Σ xji NN

j=1 i=1


Degree of IndependenceFault 1 2 3 4 5 6 7 8 9 10 11 DI

1 0 1 1 1 1 1 0 0 1 0 1 7

2 1 0 0 1 1 0 1 0 0 0 1 5

3 1 0 0 0 1 1 1 1 0 1 1 7

4 1 1 0 0 1 0 1 0 0 0 1 5

5 1 1 1 1 0 0 0 1 1 1 0 7

6 1 0 1 0 0 0 1 1 1 0 0 5

7 0 1 1 1 0 1 0 1 1 0 0 6

8 0 0 1 0 1 1 1 0 1 1 1 7

9 1 0 0 0 1 1 1 1 0 1 1 7

10 0 0 1 0 1 0 0 1 1 0 1 5

11 1 1 1 1 0 0 0 1 1 1 0 7

DI 7 5 7 5 7 5 6 7 7 5 7


Similarity Metric

Similarity Metric:

This is a measure defined for a pair of faults that determines how similar they are in their independence and concurrent-testability with respect to the entire fault set of the circuit.

SIM (fault-i, fault-j) = Nxij + (1-xij) Σ |xik-xjk|N

k=1


Similarity MetricsFault 1 2 3 4 5 6 7 8 9 10 11

1 0 11 11 11 11 11 3 4 11 4 11

2 11 0 4 11 11 6 11 6 4 6 11

3 11 4 0 4 11 11 11 11 0 11 11

4 11 11 4 0 11 6 11 6 4 6 11

5 11 11 11 11 0 4 3 11 11 11 0

6 11 6 11 6 4 0 11 11 11 4 4

7 3 11 11 11 3 11 0 11 11 5 3

8 4 6 11 6 11 11 11 0 11 11 11

9 11 4 0 4 11 11 11 11 0 11 11

10 4 6 11 6 11 4 5 11 11 0 11

11 11 11 11 11 0 4 3 11 11 11 0


Similarity Metric of a Fault-Pair

HighlyDissimilar

HighlySimilar

Equivalent Independent(Group together) (Group separately)

Sim

ilari

ty m

etri

c of

a f

ault-

pair Max.

0


Step 1 – Compute Degree of Independence (DI) for All Faults

Fault 1 2 3 4 5 6 7 8 9 10 11 DI

1 0 1 1 1 1 1 0 0 1 0 1 7

2 1 0 0 1 1 0 1 0 0 0 1 5

3 1 0 0 0 1 1 1 1 0 1 1 7

4 1 1 0 0 1 0 1 0 0 0 1 5

5 1 1 1 1 0 0 0 1 1 1 0 7

6 1 0 1 0 0 0 1 1 1 0 0 5

7 0 1 1 1 0 1 0 1 1 0 0 6

8 0 0 1 0 1 1 1 0 1 1 1 7

9 1 0 0 0 1 1 1 1 0 1 1 7

10 0 0 1 0 1 0 0 1 1 0 1 5

11 1 1 1 1 0 0 0 1 1 1 0 7

DI 7 5 7 5 7 5 6 7 7 5 7


Step 2 – Order Faults by DIFault 1 3 5 8 9 11 7 2 4 6 10 DI

1 0 1 1 0 1 1 0 1 1 1 0 7

3 1 0 1 1 0 1 1 0 0 1 1 7

5 1 1 0 1 1 0 0 1 1 0 1 7

8 0 1 1 0 1 1 1 0 0 1 1 7

9 1 0 1 1 0 1 1 0 0 1 1 7

11 1 1 0 1 1 0 0 1 1 0 1 7

7 0 1 0 1 1 0 0 1 1 1 0 6

2 1 0 1 0 0 1 1 0 1 0 0 5

4 1 0 1 0 0 1 1 1 0 0 0 5

6 1 1 0 1 1 0 1 0 0 0 0 5

10 0 1 1 1 1 1 0 0 0 0 0 5

DI 7 7 7 7 7 7 6 5 5 5 5


Step 3 – Compute Similarity Metrics for All Fault-Pairs

1

3

51,8

3,9

5,115,11,7

3,9,2 44,64,6,10

11

11

4 11

0

03

4 6

F 1 3 5 8 9 11 7 2 4 6 10

1 0 11 11 4 11 11 3 11 11 11 4

3 11 0 11 11 0 11 11 4 4 11 11

5 11 11 0 11 11 0 3 11 11 4 11

8 4 11 11 0 11 11 11 6 6 11 11

9 11 0 11 11 0 11 11 4 4 11 11

11 11 11 0 11 11 0 3 11 11 4 11

7 3 11 3 11 11 3 0 11 11 11 5

2 11 4 11 6 4 11 11 0 11 6 6

4 11 4 11 6 4 11 11 11 0 6 6

6 11 11 4 11 11 4 11 6 6 0 4

10 4 11 11 11 11 11 5 6 6 4 0

Similarity index for fault F for each existing node i:Max. SIM (F, kth fault of node i) where k = 1…..K, and K is number of faults in node i.

Step 4 – Collapse the Graph


Bounds on Number of Tests

Nc < Number of tests < Σ

where, Nc’ is the number of nodes in the collapsed graph (Nc’ ≥ Nc).

and, ki is the number of faults in the ith node.

For C17, 4 < Number of tests < 7.

Nc’

i=1

ki

2

_


Concurrent Test Generation

Concurrent Test: Given a set of target faults, a concurrent-test

is an input vector that detects all (or most) faults in the set.


Concurrent D Algebra for 2-Input AND Gate


Concurrent Test Generation for C17

2-1

3-1

9-1

0

1

1

1

1

D2 D2

D3

D9

D3

D9

D23

D390


Concurrent Test Generation for C17

Fault Targets Test

(a b c d e)

1,8 10010

3,9,2 01111

5,11,7 X1010

4,6,10 10101

2-14-1

1-1

6-1

8-1

7-13-1

9-1

5-1

10-1

11-1

a

b

cd

e

x

y


Results (ALU – 74181)Node Number of faults Test vectorsno. Total Targeted Detected from Cumulative

this

nodeothernodes

coverage

1 5 5 5 6 11 010011110100012 3 3 3 2 16 010011111101013 8 7 7 3 26 010111010000014 3 3 3 3 32 101x01010100005 5 3 3 4 39 101001010110006 6 6 6 2 47 111110000010017 7 4 4 3 54 111000001000008 14 11 11 1 66 111001101010119 8 6 5 1 72 10010100110101

10 8 4 3 2 77 1x10101110110011 8 3 3 1 81 0101000010110012 9 2 2 1 84 1x011110001100


Simulation-Based Techniques• The functional dominance fault collapsing6,

used prior to independence fault collapsing, is based on ATPG and is complex.

• The independence graph generation procedure is also based on ATPG.

• The use of concurrent D-algebra requires a new ATPG program that may not be readily available to a user.

6 R. K. K. R. Sandireddy and V. D. Agrawal, “Diagnostic and Detection Fault Collapsing for Multiple Output Circuits," in Proc. Design, Automation and Test in Europe (DATE) Conf., Mar. 2005, pp. 1014 - 1019.


Simulation-Based Independence Fault Collapsing

• Start with a fully-connected independence graph for an equivalence collapsed fault set (structural collapsing only), i.e., assume initially all faults are independent of each other.

• Simulate random vectors without fault dropping to remove edges between faults detected by the same vector. Stop the random vector simulation when a large number of vectors do not remove any new edges.

• Apply the original independence fault collapsing algorithm on the generated independence matrix.


Simulation-Based Independence Fault Collapsing

74181 4-bit ALU

301

0

25000

50000

75000

100000

0 500 1000 1500 2000 2500

Random Vectors

Nu

mb

er o

f ed

ges

0

80

160

240

320

Fau

lts

Det

ecte

d

90601 Faults Detected (293)

Number of edges in graph (20004)


Simulation-Based Concurrent Test Generation

• For each group, generate all test vectors for the first fault in the group.– If the number of test vectors for a fault is large, use

a subset (e.g., 250 maximum) of vectors.

• Simulate all faults in the group to select one vector that detects most faults in that group.– If more vectors than one detect the same number

of faults within the group, then select the vector that detects most faults outside the group as well.


74181 4-Bit ALU ResultGroup number Number of faults in group Concurrent test vector

1

2

3

4

5

6

7

8

9

10

11

12

13

9

15

11

6

11

17

11

16

16

22

22

56

81

01100011111100

01101100000110

10100101111010

11011010100000

10110101011010

10100111101010

10010101001110

01000111101011

11100010010011

11011100110100

01010001100001

All 56 faults detected by eleven

previously generated vectors

10101001110110


* Sun Ultra 5 *** Pentium Pro PC ** Hamzaoglu and Patel, IEEE-TCAD, 2000

Concurrent ATPG Results

CircuitNo. of

concurrent groups

Concurrent ATPG Single-fault ATPG

Vectors CPU s*

Atalanta Best known

Vectors CPU s* Vectors CPU s***

1-b adder2-b adder4-b adder8-b adder

16-b adder32-b adder4-b ALU

c17c432c499c880

c1355c1908c2670c3540c5315c6288c7552

555777

134

30522484

10681

1079223

190

55579

11124

34522984

11192

13010425

198

0.0850.0920.1030.182

3.39.7

11.40.08210.414.623.334

49.6 57.6

119.6216.3158.1360.7

5-77-9

8-1110-1513-2217-2522-40

6-949-7754-68

52-10685-109

118-173106-192147-263114-224

32-48209-358

0000

0.0170.0500.033

00.0830.0330.133

0.10.51.21.9

0.7334.7

5.283

555555

124

27**52**16**84**

106**44**84**37**12**73**

--------

150.1

21.90.9

88.147.1

174.5748.6347.7663.8


Number of Vectors for Increasing Circuit Sizes (100% Stuck-at Coverage)

0

50

100

150

200

250

300

350

400

minconc-ATPGsf-ATPG

Single-fault ATPG(no compaction)

Concurrent ATPG

Minimum achieved!(dynamic compaction)

1-bit c7552adder


CPU Seconds for Increasing Circuit Sizes (100% Stuck-at Fault Coverage)

0

100

200

300

400

500

600

700

800

minconc-ATPG

Concurrent ATPG

Minimum achieved!(dynamic compaction)

1-bit c7552adder


Conclusions• Concurrent test generation produces compact

tests when combined with independence fault collapsing.

• ATPG and set covering problems have exponential time complexities. Hence, we cannot expect absolute optimality for large circuits.

• The concurrent ATPG procedure gives significantly smaller, and sometimes the optimum, test sets.


Future Work

• There is scope for improving the simulation-based algorithms for independence fault collapsing and concurrent test generation.– Can be made more dynamic.

• Concern about memory requirement.

• Implement an ATPG program using the concurrent D algebra.


Future Work – Another Collapsing Technique

6

8

76, 5

8, 4

7, 16, 5, 11 7, 1, 10

99, 39, 3, 2

11

11

4 11

0

3

4

F 1 3 5 8 9 11 7 2 4 6 10

1 0 11 11 4 11 11 3 11 11 11 4

3 11 0 11 11 0 11 11 4 4 11 11

5 11 11 0 11 11 0 3 11 11 4 11

8 4 11 11 0 11 11 11 6 6 11 11

9 11 0 11 11 0 11 11 4 4 11 11

11 11 11 0 11 11 0 3 11 11 4 11

7 3 11 3 11 11 3 0 11 11 11 5

2 11 4 11 6 4 11 11 0 11 6 6

4 11 4 11 6 4 11 11 11 0 6 6

6 11 11 4 11 11 4 11 6 6 0 4

10 4 11 11 11 11 11 5 6 6 4 0

Fault Targets

Test(a b c d e)

6, 5, 11 01100

7, 1, 10 10011

8, 4 10100

9, 3, 2 01111

1146

5


Thank You!

Independence Fault Collapsing and Concurrent Test Generation Thesis Advisor: Vishwani D. Agrawal...

Documents

Transcript of Independence Fault Collapsing and Concurrent Test Generation Thesis Advisor: Vishwani D. Agrawal...