Graduate Computer Architecture I VHDL Structure and Testing Michael Sorensen.
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Transcript of Graduate Computer Architecture I VHDL Structure and Testing Michael Sorensen.
Graduate Computer Architecture I
VHDL Structure and Testing
Michael Sorensen
2 - CSE/ESE 560M – Graduate Computer Architecture I
Overview
• Everything You Always Wanted To Know About Synthesizable VHDL But Where Afraid To Ask by William D. Richard, PhD.
• Components• VHDL 2 Process Structure
– ALU using 2 Processes• Using Modelsim (Tips)• Testing
– VHDL Test bench / Test Vectors– Modelsim Do files
• VHDL Debugging Notes and Tips
3 - CSE/ESE 560M – Graduate Computer Architecture I
Everything You Always Wanted To Know
• Everything You Always Wanted To Know About Synthesizable VHDL But Where Afraid To Ask by William D. Richard, PhD. – It is available on the website, just remember William D. Richard.– It is a great resource for those that don’t have a VHDL book.
4 - CSE/ESE 560M – Graduate Computer Architecture I
Components
Component AND2entity and2 is Port ( a : in std_logic; b : in std_logic; s : out std_logic);end and2;architecture Behavioral of and2 isBegin
s <= a and b;
end Behavioral;
Component AND4entity and4 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; b : in std_logic; s : out std_logic);end and4;
architecture Behavioral of and4 is
component and2 Port ( a : in std_logic; -- Ports must match b : in std_logic; s : out std_logic);end component;
signal temp1, temp2 : std_logic;
Begin
and2one:and2 port map ( a => a, b => b, s => temp1);
and2two:and2 port map ( a => c, b => d, s => temp2);
and2three:and2 port map ( a => temp1, b => temp2, s => s);
end Behavioral;
5 - CSE/ESE 560M – Graduate Computer Architecture I
VHDL 2 Process Structure
• Benefits– Design Pattern, easily recognized– “Easier” to program– “Easier” to debug– Works best for finite state machines
• Basics– First process defines what occurs on a rising clock– Second process defines the combinational logic
• Basics (in terms of finite state machine)– First process sets the state from the next_state on a rising clock– Second process calculates the next_state
6 - CSE/ESE 560M – Graduate Computer Architecture I
VHDL 2 Process Structureentity example is Port ( clk : in std_logic; reset : in std_logic; a : in std_logic_vector(31 downto 0); z : out std_logic_vector(31 downto 0));end example;architecture Behavioral of example issignal a_int, z_int : std_logic_vector(31 downto 0);Begin
-- D-Flip Flopsprocess (clk) -- <-- process of only clockbegin
if clk'event and clk = '1' then -- <-- proper way to trigger on a rising clock edgeif reset = '1' then -- <-- proper way to create a reset
z <= “00000000000000000000000000000000”;a_int <= “00000000000000000000000000000000”;
elsea_int <= a;z <= z_int;
end if;end if;
end process;
-- Combinational Logicprocess (a_int) -- <-- process of signals used in c/l but no clockbegin
-- z_int <= F(a_int);end process;end Behavioral;
7 - CSE/ESE 560M – Graduate Computer Architecture I
ALU using the 2 Processesentity alu32bit is Port ( clk : in std_logic; a : in std_logic_vector(31 downto 0); b : in std_logic_vector(31 downto 0); ctrl : in std_logic_vector(2 downto 0); z : out std_logic_vector(31 downto 0); ovr : out std_logic; zero : out std_logic);end alu32bit;
architecture Behavioral of alu32bit is
signal a_int, b_int, z_int : std_logic_vector(31 downto 0);signal ctrl_int : std_logic_vector(2 downto 0);signal ovr_int, zero_int : std_logic;signal tmp1, tmp2 : std_logic_vector(31 downto 0);
begin
process (clk)begin
if clk'event and clk = '1' thena_int <= a;b_int <= b;ctrl_int <= ctrl;z <= z_int;ovr <= ovr_int;zero <= zero_int;
end if;end process;
8 - CSE/ESE 560M – Graduate Computer Architecture I
ALU using the 2 Processes (cont.)process (a_int, b_int, ctrl_int, tmp1, tmp2)begin
ovr_int <= '0';zero_int <= '1';z_int <= tmp1;case ctrl is
when "000" => -- ADD-- REMOVED FOR SPACE REASONS
when "001" => --SUBTRACTtmp1 <= a_int - b_int;if tmp1 = "00000000000000000000000000000000" then zero_int <= '0';end if;
when "010" => --bitwise ANDtmp1 <= a_int and b_int;
when "011" => --bitwise ORtmp1 <= a_int or b_int;
when "100" => --bitwise XORtmp1 <= a_int xor b_int;
when "101" => --shifttmp1 <= to_stdlogicvector(to_bitvector(a_int) sll conv_integer(b_int));
when "110" => --lessif a_int < b_int then tmp1 <= "00000000000000000000000000000001";else tmp1 <= "00000000000000000000000000000000";end if;
when others => null;end case;
end process;
end Behavioral;
9 - CSE/ESE 560M – Graduate Computer Architecture I
Using Modelsim (Tips)
• Commands: – vcom
• Modelsim’s vhdl compiler. Run Vcom and a GUI pops up to allow you to select files to compile. Make sure you do them in order of dependency.
– vsim• Start a simulation. Example: vsim alu32bit (notice no .vhd)
– quit -sim • Exits out of a simulation. For you to recompile if you make changes.
– restart -f• Restarts a simulation. For you to change your do file and rerun it.
• Zoom Full, the blue magnify glass, Auto Scales the wave form• Change Radix, right click on signals, select Radix
– View signals or vectors in Binary, Unsigned, Decimal, etc.
10 - CSE/ESE 560M – Graduate Computer Architecture I
Testing (VHDL Test Vectors)
• To create one select, New Source, VHDL Test Bench• OR – Create a new VHDL Module and rewrite• Benefit – can be set to check desired results
Example: Synchronized And Gateentity syncand2 is Port ( clk : in std_logic; a : in std_logic; b : in std_logic; s : out std_logic);end syncand2;
architecture Behavioral of syncand2 is
begin
process (clk)begin
if clk'event and clk = '1' thens <= a and b;
end if;end process;
end Behavioral;
11 - CSE/ESE 560M – Graduate Computer Architecture I
Testing (VHDL Test Vectors)library ieee;use ieee.std_logic_1164.all; entity syncand2tb is -- No Ports for VHDL Test Benchend syncand2tb; architecture stimulus of syncand2tb is component syncand2 Port ( clk : in std_logic; a : in std_logic; b : in std_logic; s : out std_logic); end component;
signal clk : std_logic; signal a: std_logic; signal b: std_logic; signal s: std_logic; signal vector_cnt: integer := 1; signal error_flag: std_logic := '0'; type test_record is record -- Declare a record type a: std_logic; -- Signals of component to test b: std_logic; s: std_logic; -- Expected result end record;
12 - CSE/ESE 560M – Graduate Computer Architecture I
Testing (VHDL Test Vectors)
type test_array is array(positive range <>) of test_record; -- Collect them -- in an array -- The following constant declaration describes the test vectors to be -- applied to the design during simulation, and the expected result after a -- rising clock edge. constant test_vectors : test_array := ( -- a, b, s ('0', '0', '-'), -- RESET (IGNORE THE RESULT) ('0', '0', '0'), ('1', '0', '0'), ('0', '1', '0'), ('1', '1', '1'), ('0', '0', '0') ); begin -- instantiate the component UUT: syncand2 -- instance declared as UUT (Unit Under Testing)
port map ( clk => clk, a => a, b => b,
s => s);
The Test Vectors
13 - CSE/ESE 560M – Graduate Computer Architecture I
Testing (VHDL Test Vectors) -- provide stimulus and check the result
testrun: process variable vector : test_record; begin for index in test_vectors'range loop vector_cnt <= index; vector := test_vectors(index); -- Get the current test vector -- Apply the input stimulus... a <= vector.a; b <= vector.b; -- Clock (low-high-low) with a 100 ns cycle... clk <= '0'; wait for 25 ns; -- Quarter of the desired clock cycle clk <= '1'; wait for 50 ns; -- Half of the desired clock cycle clk <= '0'; wait for 25 ns; -- Quarter of the desired clock cycle
-- Check the results... if (vector.s /= '-' and s /= vector.s) then error_flag <= '1'; assert false report "Output did not match!" severity WARNING; else error_flag <= '0'; end if; end loop; wait; end process;end stimulus;
14 - CSE/ESE 560M – Graduate Computer Architecture I
Testing (VHDL Test Vectors)
Results
15 - CSE/ESE 560M – Graduate Computer Architecture I
Testing (Modelsim Do files)
• To create a Do file use any standard text editor
Example: Synchronized And Gateentity syncand2 is Port ( clk : in std_logic; a : in std_logic; b : in std_logic; s : out std_logic);end syncand2;
architecture Behavioral of syncand2 is
begin
process (clk)begin
if clk'event and clk = '1' thens <= a and b;
end if;end process;
end Behavioral;
16 - CSE/ESE 560M – Graduate Computer Architecture I
Testing (Modelsim Do files)
• Copy generated commands to do file• To read bidirectional lines after Freezing them, select Force,
set value to Z and set Kind to Deposit
force -freeze sim:/syncand2/clk 1 0, 0 {50 ps} -r 100ps force -freeze sim:/syncand2/a 0 0
Set a clock Force a signal
17 - CSE/ESE 560M – Graduate Computer Architecture I
Testing (Modelsim Do files)
syncand2.doforce -freeze sim:/syncand2/clk 1 0, 0 {50 ps} -r 100psforce -freeze sim:/syncand2/a 0 0force -freeze sim:/syncand2/b 0 0run 200force -freeze sim:/syncand2/a 1 0force -freeze sim:/syncand2/b 0 0run 100force -freeze sim:/syncand2/a 0 0force -freeze sim:/syncand2/b 1 0run 100force -freeze sim:/syncand2/a 1 0force -freeze sim:/syncand2/b 1 0run 100force -freeze sim:/syncand2/a 0 0force -freeze sim:/syncand2/b 0 0run 200
To run do file from Modelsim command prompt type:
VSIM #> do syncand2.do
Default unit of time is ns.
18 - CSE/ESE 560M – Graduate Computer Architecture I
VHDL DEBUGING NOTES AND TIPS
• Make backups, at least backup copies of working code before you add features to it.
• Correct all undefined (red) signals in Modelsim first.• Check sensitivity list• Check that signals are only modified/driven in one process (or
if outside of a process, modified/driven on only one line)• If problems are with bidirectional lines make sure that
components correctly share line. And if your forcing the line in simulation remember to deposit Z’s before you want to read values from it.
• Ask Questions!