Fast Boot Camp
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Transcript of Fast Boot Camp
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Fast Boot Camp
non-BIOS IPL on the Intel Menlow Platform
Dave Green
Project Manager, Automotive Services
Team
QNX Software Systems
December 9/10, 2008
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2 QNX Confidential. All content copyright QNX Software Systems.
Course Overview
Day 1
Introduction
Terminology
How we got here A Brief History of QNX running without BIOSBIOS vs. IPL
when booting
at runtime
a closer look at the startup code
PCI server pci-bios vs. custom
the IPL
what it does and does not dowhy exactly is IPL faster than BIOS
walk-through of IPL, including memory controller init
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3 QNX Confidential. All content copyright QNX Software Systems.
Course Overview (cont.)
Day 2
installing/building the FASTboot BSP
a closer look at the code (IPL, startup, PCI server)
What else is needed (docs, secret stuff)generating the images
BIOS-based boot image
boot from USB stick or on-board NAND hard drive
non-BIOS IPL and boot image
first with debug info, serial download, etc.
make sure everything is working
make it faster
remove debug info
automatically start gears demo
generate the final fastboot image
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4 QNX Confidential. All content copyright QNX Software Systems.
Terminology
Silverthorne = Atom = Z500,Z510, etc.
Poulsbo = US15W = System Controller Hub (SCH)
Menlow = a combination of Silverthorne/Poulsbo (or Atom/US15W)
Atom CPU with Intel ICH7/ICH8/ICH9 is NOT Menlow!
Northbridge the fast bus portions
memory controller
host/PCI bridgegraphics controller
Southbridge
PCI devices (USB controller, PATA/SATA, kbd/mouse/interrupt
control ler, legacy devices)
Chipset Northbridge and southbridge chips, in companion withCPU
System On a Chip (SoC) CPU and chipset all in one (AMD SC400,IBM PPC4xx, Freescale MPC8641D, most SystemH, MIPS, and ARM)
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History
QNX was originally x86 only (QNX 2, QNX 4)
BIOS was the only way to boot
Intel very protective of information
only BIOS vendors had accessOS / runtime drivers also relied on BIOS
console I/O, video mode switching
Using the BIOS just made good sense
ensured OS compatabil ity with the widest variety of hardware
In the late 90s, things began to change
AMD SC400, Intel 386ex, NatSemi/Cyrix all create embedded x86processors (SoCs, really)
full documentation available!
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History (cont.)
QNX created a non-BIOS Initial Program Loader (IPL) for each ofthese new SoCs
part of the original QNX4 EKit
required some additional work to remove BIOS dependencies fromdevice drivers
no VGA console output, so we use serial port instead
Photon graphics drivers no BIOS to change graphics mode, so direct mode switchers were required
The Dawn of QNX Neutrino
more than just x86
QNX will support all major 32 bit processors with MMU
the Five Families - x86, ARM, MIPS, PowerPC, SystemH
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QNX Neutrino
New Challenges
maintaining code base for five different architectures would be anightmare
required proper planning
common code base for all platforms, except for well-defined exceptions
kernel
portions of startup library code
board specific code (normally contained in startup and IPL)device drivers must be common code base, regardless of whichplatform they run on
required removing any BIOS dependencies from legacy x86 drivers
New Opportunitiesno BIOS on any of these new platforms
IPL code is alternative to ROM Monitor / boot loader
unlike x86, all the necessary information is out there
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Before we get to the Fast Boot
overview of startup, PCI, and IPL in general
preboot, startup library, board-specific code
interrupts and interrupt routing
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Startup Code
QNX startup code consists of:
preboot
allows different image formats
ELF, S-record, binary, raw on x86, any BIOS calls are limited to this portion
extra x86 stuff
probe for memory, hard drive, etc.
gate A20 control switch from real mode to protected mode
for use with BIOS only; with a non-BIOS boot, stuff that is normally donein preboot is done elsewhere, or else isnt necessary
for example, no need to know about hard drives; devb-eide will work fine
with no BIOS info
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Startup Code (cont.)
startup library
common code portion (for all 5 CPU families)
architecture specific port ion
even the x86 specific portion of startup library has no dependence on BIOS
main role of startup library is to populate the System Page
system page is used heavily by kernel and device drivers
board directories
contain board-specific code which cant be abstracted to the libraryfor BIOS based x86 systems, startup-bios is the norm
dont let the name fool you it works fine with a non-BIOS x86 system!
although youll likely still need a custom startup at some point
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Interrupts
interrupts are disabled during IPL execution
startup code sets up the interrupt controller, defines callouts
kernel uses callouts to identify, mask, and unmask system interrupts
on other architectures, there are many different interrupt controllersx86 must support legacy, so it s typically a master/slave 8259configuration
no new callout work, but not a lot of available interrupts
what about all these PCI devices?
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Interrupts (cont.)
BIOS makes interrupt assignments, sets up routing of PCI ints
if theres no BIOS, we need to do i t ourselves
BIOS often makes inefficient assignments
under-utilizes available routing optionsmany peripherals routed to the same interrupt
this leads to poor performance
many ISRs need to run, when only one actually needs to do anything
if we have to set up interrupt routing anyhow, why not make it better?
high-traffic interrupts can be assigned their own channel
low-traffic interrupts can share interrupt lines
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Interrupts (cont.)
not many physical interrupts available on x86
modern systems offer additional features to compensate
each PCI device can be assigned to one of 4 pins (INTA# - INTD#)
PCI INTA# - INTD# can be routed to any of 8 programmable IRQ lines PIRQa PIRQh
each PIRQ can be routed to a different input on the dual 8259 system
additional logic to configure individual ISA interrupts as level triggered
these registers override the setup of the master/slave 8259s, where thewhole controller had to be either level or edge
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the PCI server
the BIOS enumerates the PCI bus
scans all devices
assigns memory, I/O, and interrupts to devices at boot time
QNX PCI server takes advantage of thiswhat happens in a non-BIOS system?
PCI server must do more
doesnt do anything for individual devices until necessary
for memory and I/O resources, PCI server probes hardware to determinerequirements
calls into QNX Resource Database Manager for allocation
for interrupts, BSP developer must determine assignments
must match whats done in startup code
assignments based on PCI device/function number
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IPL
Whats needed to do a new IPL?
an existing IPL helps a lot
very few changes from one board to the next
Access to Intel Secret Restricted Confidential docsSilverthorne Processor BIOS Writers Guide
Poulsbo SCH Firmware Writers Guide
Intel MRC code based on these docs
MRC source itself is not really necessary
QNX IPL code also follows algorithms in these docs
helpful if you want to work out something from the IPL
Publicly available Intel docs
US15W SCH Datasheet
available on web
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Initial Program Loader (IPL)
Why is the IPL so much faster than BIOS?
its the things we dont do that make a difference
for optimum boot time, do as litt le as possible
minimal IPL consists of: basic HW init (clocks, chip selects, etc)
memory controller init
locate QNX OS image (image_scan)
copy QNX startup to DRAM (image_setup)jump to startup code (image_start)
everything else is opt ional
addit ional gains booting from ROM vs. HD
when booting from disk with BIOS, BIOS calls are used to copy image toDRAM, one block at a time (slow)
flash/ROM is l inearly mapped, so it can all be seen at once
traditional copy(src,dest,size) call can be used
much faster!