Expectations for optical network from the viewpoint of system software research
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OTREI A ANOASIONAL NRSISTSE OF ,DUANCED NDTRS IAL CIENCE AND ECHNOLOG
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0WPECSASIONR FO OPSICAL NESVOF OM SHE UIEVPOINS OF R RSEM
ROFSVA E EREA CH
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-‐‑‒
Architecture
Service Cluster Back-End Cluster
Front-End Cluster
Web250 racks
Ads 30 racks
Cache (~144TB)
Search Photos Msg Others UDB ADS-DB Tao Leader
Multifeed 9 racks
Other small services
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Standard Systems
IWeb
IIIDatabase
IVHadoop
VPhotos
VIFeed
CPUHigh
2&x&E5*2670
High
2&x&E5*2660
High
2&x&E5*2660Low
High
2&x&E5*2660
Memory LowHigh
144GB
Medium
64GBLow
High
144GB
Disk LowHigh&IOPS
3.2&TB&Flash
High
15&x&4TB&SATA
High
15&x&4TB&SATAMedium
Services Web,&Chat DatabaseHadoop
(big&data)Photos,&Video
MulPfeed,
Search,&Ads
Five Standard Servers
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PEN OMPTSE : OJECS
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3: HE ACHINE
0
The$Machine$could$be$six$%mes$more$powerful$than$an$equivalent$conven2onal$design,$while$using$just$1.25$percent$of$the$energy$and$being$around$1/100$the$size.
h:p://www.hpl.hp.com/research/systems@research/themachine/
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HE ACHINE , CHISECST E
)(
Photonic Interconnect
Compute Elements
Memory Elements
NV Memory Elements
Storage Elements
Architecture evolution/revolution“Computing Ensemble”: bigger than a
server, smaller than a datacenter, built-in system software
– Disaggregated pools of uncommitted compute, memory, and storage elements
– Optical interconnects enable dynamic, on-demand composition
– Ensemble OS software using virtualization for composition and management
– Management and programmingvirtual appliances add value for IT and application developers
On-demand composition
Ensemble OS Management
Ensemble Programming
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UC Berkeley
1 Terabit/sec optical fibers FireBox Overview!
High Radix Switches
SoC
SoC
SoC
SoC
SoC
SoC
SoC SoC SoC
SoC
SoC
SoC
SoC
SoC
SoC
SoC
Up to 1000 SoCs + High-BW Mem
(100,000 core total)
NVM
NVM
NVM
NVM
NVM
NVM
NVM
NVM NVM NVM
NVM
NVM
NVM
NVM
NVM
NVM
Up to 1000 NonVolatile Memory Modules (100PB total)
InterXBox&Network&
Many&Short&Paths&Thru&HighXRadix&Switches&
1I E-‐‑‒OW UE UIEV
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UC Berkeley Photonic-Switches-
! Monolithically&integrated&silicon&photonics&with&WaveXDivision&MulCplexing&(WDM)&- A&fiber&carries&32&wavelengths,&each&32Gb/s,&in&each&direcCon&- OffXchip&laser&opCcal&supply,&onXchip&modulators&and&detectors&
! MulCple&radixX1000&photonic&switch&chips&arranged&as&middle&stage&of&Clos&network&(first&and&last&Clos&stage&inside&sockets)&
! 2K&endpoints&can&be&configured&as&either&SoC&or&NVM&modules&! In&Box,&all&paths&are&two&fiber&hops:&
- ElectricalXphotonic&at&socket&- One&fiber&hop&socketXtoXswitch&- PhotonicXelectrical&at&switch&- Electrical&packet&rouCng&in&switch&- ElectricalXphotonic&at&socket&- One&fiber&hop&switchXtoXsocket&- PhotonicXelectrical&at&socket&
30
SoC&
Switch& Switch&
SoC& NVM&
)+
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IMPULSE: Initiative for Most Power-efficient Ultra-Large-Scale data Exploration�
2014� 2020� 2030�
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Op2cal$Network�
3D stacked package�2.5D stacked package�Separated packages�
Future data center�
Logic� I/O�
NVRAM�
Logic�
NVRAM�
I/O�I/O�
Logic�
NVRAM�
High-Performance Logic Architecture
Non-Volatile Memory Optical Network - Voltage-controlled, magnetic RAM mainly for cache and work memories�
- 3D build-up integration of the front-end circuits including high-mobility Ge-on-insulator FinFETs. / AIST-original TCAD �
- Silicon photonics cluster SW - Optical interconnect technologies�
- Future data center architecture design / Dataflow-centric warehouse-scale computing�
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15
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AIST’s IMPULSE Program�
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Voltage-controlled Nonvolatile Magnetic RAM�
Nonvolatile CPU
Nonvolatile Cash
Nonvolatile Display�
Power saved storage
NAND Flash
Voltage Controlled Spin RAM�
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Voltage Controlled Topological RAM�
Memory keeping w/o power
Insulation Layer�
Thin film
Ferro-magnetics
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Low Power High-performance Logic�
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S � D � S � D � Insulation layer�
● Dense integration w/o miniaturization�● Reduction of the wiring length for power saving ● Introduction of Ge and III-V channels by simple stacking process ● Innovative circuit by using Z direction�
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Simulations�
Anisotropic magnetic material�
First-principle sim.�TCAD�- Large-scale simulation for 3D structure, novel devices, and latest material �
Simulation for temperature distribution�
- Clarification for voltage-control
- Parameter setting to the TCAD
Phase-change�
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DEMUX
Wavelength/bank(Optical/comb) �
��
MOD. MUX
Fiber
Silicon/Photonics/Integration
Datacenter$server$racks� Silicon photonics cluster switches�DWDM, multi-level
modulation optical interconnects�
DSP
Tx RxCombsource
Memory cube
CPU/GPU
2.5D-CPU Card�No of λs� Order of mod.� Bit rate�
1� 1� 20 Gbps�
4� 8� 640 Gbps�
32� 8� 5.12 Tbps�
●Large-scale silicon photonics based cluster switches�●DWDM, multi-level modulation, highly integrated “elastic” optical interconnects ●Ultra-low energy consumption network by making use of optical switches�
! Ultra-compact switches based on silicon photonics
! 3D integration by amorphous silicon
! A new server architecture
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Optical Network Technology for Future Datacenters�
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Architecture for Big Data and Extreme-scale Computing�
Real-time Big data�
Optimal arrangement of the data flow� Resource management / Monitoring�
Storage�
Server Module�
IXiX<Z\di\g<PS�
Input� Output�Conv.� Ana.�Data flow�
Data$flow$centric$warehouse$scale$compu%ng�
1 - Single OS controls entire data center�
2 - Split a data center OS into the data plane and the control plane to guarantee real-time data processing
Connect to universal processor / hardware and storage by using optical network
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http://simgrid.gforge.inria.fr
SimGrid Overview
MSG
Simple application-
level simulator
SimDag
Framework for
DAGs of parallel tasksapplications on top of
a virtual environment
Library to run MPISMPI
virtual platform simulator
SURF
Contrib
Grounding features (logging, etc.), data structures (lists, etc.) and portability
XBT
TRACE
Tracing
simulation
User Code
SimGrid user APIsI If your application is a DAG of (parallel) tasks ; use SimDag
I To study an existing MPI code ; use SMPI
I In any other cases ; use MSG(easily study concurrent processes and prototype distributed applications)
Da SimGrid Team SimGrid User 101 Introduction Installing MSG Java lua Ruby Trace Config xbt Performance CC 8/28
SimGrid is not a Simulator
logs
stats
visu
Availibility
Changes
Platform
Topology
Application
Deployment
Simulation Kernel
Application
Simulator
OutcomesScenario
ApplicativeWorkload
Parameters
Input
That’s a Generic Simulation Framework
Da SimGrid Team SimGrid User 101 Introduction Installing MSG Java lua Ruby Trace Config xbt Performance CC 23/28
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O LOAD AP EDTCE
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Disk bandwidth: 200Mbps Network bandwidth: 10Gbps
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Memory�
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Logic�
Board�Chassis�����
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1TB/s�
100GB/s�
1TB/s�
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-‐‑‒OSSLENEC R IN AP EDTCE
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© Copyright 2013 ISSCC—Do Not Reproduce Without Permission - 107 -
Optical Interconnect: As the bandwidth demand for traditionally electrical wireline interconnects has accelerated, optics has become an increasingly attractive alternative for interconnects within computing systems. Optical communication offers clear benefits for high-speed and long-distance interconnects. Relative to electrical interconnects, optics provides lower channel loss. Circuit design and packaging techniques that have traditionally been used for electrical wireline are being adapted to enable integrated optical with extremely low power. This trend has resulted in rapid progress in optical ICs for Ethernet, backplane and chip-to-chip optical communication. ISSCC 2014 includes a 2-dimensional (12×5) optical array achieving an aggregate data-rate of 600Gb/s [8.2]. Pre-emphasis using group-delay filtering extends the useful date rate of a 25Gb/s VCSEL to 40Gb/s [8.9]. Additional examples of low-power-linear and non-linear equalizers tackle electronic dispersion compensation in multi-mode and long-haul cables [8.1, 8.3]. Concluding Remarks: Continuing to aggressively scale I/O bandwidth is both essential for the industry and extremely challenging. Innovations that provide higher performance and lower power will continue to be made in order to sustain this trend. Advances in circuit architecture, interconnect topologies, and transistor scaling are together changing how I/O will be done over the next decade. The most exciting and most promising of these emerging technologies for wireline I/O will be highlighted at ISSCC 2014.
Per-pin data-rate vs. year for a variety of common I/O standards.
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© Copyright 2013 ISSCC—Do Not Reproduce Without Permission - 119 -
DRAM Data bandwidth trends.
Non-Volatile Memories (NVMs): In the past decade, significant investment has been put into emerging memories to find an alternative to floating-gate based non-volatile memory. The emerging NVMs, such as phase-change memory (PRAM), ferroelectric RAM (FeRAM), magnetic spin-torque-transfer (STT-MRAM), and Resistive memory (ReRAM), are showing potential to achieve high cycling capability and lower power per bit in read/write operations. Some commercial applications, such as cellular phones, have recently started to use PRAM, demonstrating that reliability and cost competitiveness in emerging memories is becoming a reality. Fast write speed and low read-access time are the potential benefits of these emerging memories. At ISSCC 2014, a high-density ReRAM with a buried WL access device is introduced to improve the write performance and area. The next Figure highlights how MLC NAND Flash write throughput continues to improve. However, while the Figure following shows no increase in NAND Flash density over the past year, recent devices are built with finer dimensions or more sophisticated 3-dimensional vertical bit cells.
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