ECE C03 Lecture 91 Lecture 9 Registers, Counters and Shifters Hai Zhou ECE 303 Advanced Digital...
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Transcript of ECE C03 Lecture 91 Lecture 9 Registers, Counters and Shifters Hai Zhou ECE 303 Advanced Digital...
ECE C03 Lecture 9 1
Lecture 9 Registers, Counters and Shifters
Hai Zhou
ECE 303
Advanced Digital Design
Spring 2002
ECE C03 Lecture 9 2
Outline
• Registers• Register Files• Counters • Designs of Counters with various FFs• Shifters• READING: Katz 7.1, 7.2, 7.4, 7.5, 4.7 Dewey
10.2, 10.3, 10.4, Hennessy-Patterson B26
ECE C03 Lecture 9 3
Building Complex Memory Elements
• Flipflops: most primitive "packaged" sequential circuits
• More complex sequential building blocks:
Storage registers, Shift registers, Counters Available as components in the TTL Catalog
• How to represent and design simple sequential circuits: counters
• Problems and pitfalls when working with counters:
Start-up States Asynchronous vs. Synchronous logic
ECE C03 Lecture 9 4
Registers
• Storage unit. Can hold an n-bit value• Composed of a group of n flip-flops
– Each flip-flop stores 1 bit of information
• Normally use D flip-flopsD Q
Dffclk
D QDffclk
D QDffclk
D QDffclk
ECE C03 Lecture 9 5
Controlled RegisterReset Load Action0 0 Q = old Q1 0 Q = 00 1 Q = D
D QDffclk
D QDffclk
D QDffclk
D QDffclk
ECE C03 Lecture 9 6
RegistersGroup of storage elements read/written as a unit
4-bit register constructed from 4 D FFsShared clock and clear lines
TTL 74171 Quad D-type FF with Clear(Small numbers represent pin #s on package)
Schematic Shape
Q1
CLR
D3D2D1D0
171
Q1
Q0Q0
CLK Q3Q3Q2Q2
11
109
5
67
43
2
14
13
151
12
ECE C03 Lecture 9 7
Shift RegistersStorage + ability to circulate data among storage elements
Shift from left storage element to right neighbor on every lo-to-hi transition on shift signal
Wrap around from rightmost element to leftmost element
Master Slave FFs: sample inputs while clock is high; change outputs on falling edge
Shift Direction\Reset
\ResetShift
Q 1 1 0 0 0
Q 2 0 1 0 0
Q 3 0 0 1 0
Q 4 0 0 0 1
Shift
Shift
Shift
JK
JK
JK
JK
Shift
Q1
Q2
Q3
Q4
ECE C03 Lecture 9 8
Shift Registers I/OSerial vs. Parallel InputsSerial vs. Parallel OutputsShift Direction: Left vs. Right
74194 4-bit UniversalShift Register
Serial Inputs: LSI, RSIParallel Inputs: D, C, B, AParallel Outputs: QD, QC, QB, QAClear SignalPositive Edge Triggered Devices
S1,S0 determine the shift functionS1 = 1, S0 = 1: Load on rising clk edge synchronous loadS1 = 1, S0 = 0: shift left on rising clk edge LSI replaces element DS1 = 0, S0 = 1: shift right on rising clk edge RSI replaces element AS1 = 0, S0 = 0: hold state
Multiplexing logic on input to each FF!
Shifters well suited for serial-to-parallel conversions, such as terminal to computer communications
QDQCQBQA
ECE C03 Lecture 9 9
Application of Shift RegistersParallel to Serial Conversion
QAQBQCQD
S1S0LSIDCBA
RSICLK
CLR
QAQBQCQD
S1S0LSIDCBA
RSICLK
CLR
D7D6D5D4
Sender
D3D2D1D0
QAQBQCQD
S1S0LSIDCBA
RSICLK
CLR
QAQBQCQD
S1S0LSIDCBA
RSICLK
CLR
Receiver
D7D6D5D4
D3D2D1D0
Clock
194 194
194194
ParallelInputs
Serialtransmission
ParallelOutputs
ECE C03 Lecture 9 10
Counters
Proceed through a well-defined sequence of states in response to count signal
3 Bit Up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ...
3 Bit Down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ...
Binary vs. BCD vs. Gray Code Counters
A counter is a "degenerate" finite state machine/sequential circuitwhere the state is the only output
A counter is a "degenerate" finite state machine/sequential circuitwhere the state is the only output
ECE C03 Lecture 9 11
Counter Design ProcedureThis procedure can be generalized to implement ANY finite state machine
Counters are a very simple way to start: no decisions on what state to advance to next current state is the output
Example: 3-bit Binary Upcounter
000
001
State TransitionTable
FlipflopInput Table
Decide to implement withToggle Flipflops
What inputs must bepresented to the T FFsto get them to change
to the desired state bit?
This is called"Remapping the Next
State Function"
PresentState
NextState
FlipflopInputs
C B A C+ B+ A+ TC TB TA
0 0 0 0 0 1 0 0 10 0 1 0 1 0 0 1 10 1 0 0 1 1 0 0 10 1 1 1 0 0 1 1 11 0 0 1 0 1 0 0 11 0 1 1 1 0 0 1 11 1 0 1 1 1 0 0 11 1 1 0 0 0 1 1 1
ECE C03 Lecture 9 12
Example Design of CounterK-maps for Toggle
Inputs:Resulting Logic Circuit:
CB00 01 11 10A
0
1
TA =
CB00 01 11 10A
0
1
TB =
CB00 01 11 10A
0
1
TC =
ECE C03 Lecture 9 13
Count
\Reset
Q C
Q B
Q A
100
Resultant Circuit for CounterK-maps for Toggle
Inputs:Resulting Logic Circuit:
Timing Diagram:
T
CLK
\Reset
Q
Q
S
R
QAT
CLK
Q
Q
S
R
QBT
CLK
Q
Q
S
R
QC
Count
+
TB = A
TC = A • B
T A = 1
CB A
C
00 01 11 10
0
1
B
1 1 1 1
1 1 1 1
CB
A
C
00 01 11 10
0
1
B
0 0 0 0
1 1 1 1
CB A
C
B
00 01 11 10
0
1
0 0 0 0
0 1 1 0
ECE C03 Lecture 9 14
More Complex Counter Design
Step 1: Derive the State Transition Diagram
Count sequence: 000, 010, 011, 101, 110
Step 2: State Transition Table
PresentState
NextState
0 0 0 0 1 00 1 0 0 1 10 1 1 1 0 11 0 1 1 1 01 1 0 0 0 0
ECE C03 Lecture 9 15
Complex Counter Design (Contd)
Step 1: Derive the State Transition Diagram
Count sequence: 000, 010, 011, 101, 110
Step 2: State Transition Table
Note the Don't Care conditions
PresentState
NextState
0 0 0 0 1 00 0 1 X X X0 1 0 0 1 10 1 1 1 0 11 0 0 X X X1 0 1 1 1 01 1 0 0 0 01 1 1 X X X
ECE C03 Lecture 9 16
Counter Design (Contd)Step 3: K-Maps for Next State Functions
CB00 01 11 10A
0
1
C+ =
CB00 01 11 10A
0
1
A+ =
CB00 01 11 10A
0
1
B+ =
ECE C03 Lecture 9 17
Counter Design (contd)Step 4: Choose Flipflop Type for Implementation Use Excitation Table to Remap Next State Functions
Toggle ExcitationTable
Remapped Next StateFunctions
PresentState
ToggleInputs
Q Q+ T
0 0 00 1 11 0 11 1 0
0 0 0 0 1 00 0 1 X X X0 1 0 0 0 10 1 1 1 1 01 0 0 X X X1 0 1 0 1 11 1 0 1 1 01 1 1 X X X
C B A TC TB TA
ECE C03 Lecture 9 18
Resultant Counter DesignRemapped K-Maps
CB00 01 11 10A
0
1
TC
CB00 01 11 10A
0
1
TA
CB00 01 11 10A
0
1
TB
TC = A C + A C = A xor C
TB = A + B + C
TA = A B C + B C
ECE C03 Lecture 9 19
Resultant Circuit for Complex Counter
Resulting Logic:
Timing Waveform:
5 Gates13 Input Literals + Flipflop connections
TCT
CLK
Q
Q
S
RCount
T
CLK
Q
Q
S
R
TBC
\C
B A
\B \A
TAT
CLK
Q
Q
S
R
\Reset
0
0
0
0
0
0
0
1
0
0
1
1
1
0
1
1
1
0
0
0
0
100
Count
\Reset
C
B
A
TC
TBTA
AC
A\BC
\ABC\BC
ECE C03 Lecture 9 20
Implementing Counters with Different FFs
• Different counters can be implemented best with different FFs
• Steps in building a counter– Build state diagram
– Build state transition table
– Build next state K-map
• Implementing the next state function with different FFs
• Toggle flip flops best for binary counters
• Existing CAD software for finite state machines favor D FFs
ECE C03 Lecture 9 21
Implementing 5-state counter with RS FFs
Continuing with the 000, 010, 011, 101, 110, 000, ... counter example
RS Exitation Table
Remapped Next State Functions
Q+ = S + R Q
PresentState
NextState
0 0 0 0 1 0 X 0 0 1 X 0 0 0 1 X X X X X X X X X0 1 0 0 1 1 X 0 0 X 0 10 1 1 1 0 1 0 1 1 0 0 X1 0 0 X X X X X X X X X1 0 1 1 1 0 0 X 0 1 1 01 1 0 0 0 0 1 0 1 0 X 01 1 1 X X X X X X X X X
Q Q+ R S
0 0 X 00 1 0 11 0 1 01 1 0 X
Rmepped next state
RC SC RB SB RA SA
ECE C03 Lecture 9 22
Implementation with RS FFsRS FFs Continued
RC = A
SC = A
RB = A B + B C
SB = B
RA = C
SA = B C
CB00 01 11 10A
0
1
RC
CB00 01 11 10A
0
1
RA
CB00 01 11 10A
0
1
RB
CB00 01 11 10A
0
1
SC
CB00 01 11 10A
0
1
SA
CB00 01 11 10A
0
1
SB
X X 1 X
X 0 X 0
0 0 0 X X 1 X X
0 0 1 X
X 1 X 0
1 X 0 X
X 0 X 1
X 0 X XX 0 X 1
0 1 0 XX X X 0
ECE C03 Lecture 9 23
Implementation With RS FFs
Resulting Logic Level Implementation: 3 Gates, 11 Input Literals + Flipflop connections
CLK CLK CLK
\ A R
S A
C
\ C
Q
Q
RB
\ B
R
S
Q
Q \ B
B C
SA
R
S
A
\A
B
A C B
\C RB SA
Q
Q
Count
ECE C03 Lecture 9 24
Implementing with JK FFs
Continuing with the 000, 010, 011, 101, 110, 000, ... counter example
RS Exitation Table
Remapped Next State Functions
Q+ = S + R Q
PresentState
NextStateQ Q+ J K
0 0 0 X0 1 1 X1 0 X 11 1 X 0
Rmepped next stateJC KC JB KB JA KA
0 0 0 0 1 0 0 X 1 X 0 X 0 0 1 X X X X X X X X X0 1 0 0 1 1 0 X X 0 1 X0 1 1 1 0 1 1 X X 1 X 01 0 0 X X X X X X X X X1 0 1 1 1 0 X 0 1 X X 11 1 0 0 0 0 X 1 X 1 0 X1 1 1 X X X X X X X X X
ECE C03 Lecture 9 25
Implementation with JK FFsCB
00 01 11 10A
0
1
JC
CB00 01 11 10A
0
1
JA
CB00 01 11 10A
0
1
JB
CB00 01 11 10A
0
1
KC
CB00 01 11 10A
0
1
KA
CB00 01 11 10A
0
1
KB
JC = A
KC = A/
JB = 1
KB = A + C
JA = B C/
KA = C
ECE C03 Lecture 9 26
Implementation with JK FFs
Resulting Logic Level Implementation: 2 Gates, 10 Input Literals + Flipflop Connections
CLK CLK CLK J
K
Q
Q
A
\ A
C
\ C KB
J
K
Q
Q
B
\ B
+
J
K
Q
Q
JA
C
A
\ A
B \ C
Count
A C KB JA
ECE C03 Lecture 9 27
Implementation with D FFsSimplest Design Procedure: No remapping needed!
DC = A
DB = A C + B
DA = B C
Resulting Logic Level Implementation: 3 Gates, 8 Input Literals + Flipflop connections
CLK CLK
D Q
Q
A
\ A
D Q
Q
DA DB B
\ B CLK
D Q
Q
A C
\ C Count
\ C \ A
\ B
B \ C DA DB
ECE C03 Lecture 9 28
Comparison with Different FF Types• T FFs well suited for straightforward binary counters
But yielded worst gate and literal count for this example!
• No reason to choose R-S over J-K FFs: it is a proper subset of J-K
R-S FFs don't really exist anyway
J-K FFs yielded lowest gate count
Tend to yield best choice for packaged logic where gate count is key
• D FFs yield simplest design procedure
Best literal count
D storage devices very transistor efficient in VLSI
Best choice where area/literal count is the key