ECE 431 Digital Circuit Design Chapter 8: Sequential MOS...
Transcript of ECE 431 Digital Circuit Design Chapter 8: Sequential MOS...
ECE 431 Digital Circuit Design
Chapter 8: Sequential MOS Logic Circuits
Lecture given by Qiliang Li
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8.2 Behavior of Bistable Elements
Static behavior of the two-inverter basic bistable element
Circuit diagram of a CMOS bistable elementOne-possibility for the expected time-domain behavior
Small signal input and output currents of the inverters
dtdv
Cvg gggm
12 =
dtdv
Cvg gggm
21 =
See page326-328
8.3 SR Latch Circuit
Circuit diagram of CMOS SR latch showing the lumped load capacitance
Circuit diagram of depletion-load nMOS SR latch
Circuit diagram of CMOS SR latch based on NAND2 gatesPage 335
8.4 Clocked Latch and Flip-Flop Circuits
Clocked SR Latch
Clocked NOR-basedSR latch
Clocked SR Latch
Clocked NOR-basedSR latch
Clocked SR Latch
Clocked Nand-basedSR latch
8.5 CMOS D-latch and Edge-Triggered Flip-Flop
D-latch
D-latch
D-latch (version 2)
D Flip-Flop (DFF) (edge-triggered master-slave D flip-flop)
DFF
DFF Transient Response with Setup time violation at 10 ns
NAND3-based positive edge-triggered DFF