ECE 371Microprocessor Interfacing

Unit 4 - Introduction to Memory Interfacing

Simple Example to Demonstrate Memory Interfacing Concepts

Objective: To Implement a 32 Element Memory System,Using 8-Element Chips

General Approach:

1. Use Lower Address Bits to Select An Element Within a Memory Chip. (In This Example It Requires 3 Address Bits, Since Each Memory Chip Contains 8 = 23 Elements.)

2. Use the Upper Address Bits to Select Which Particular Chip Should Be Activated.

A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1

A4 A3 A2 A1 A0 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1

(FIRST GROUP OF 8 ADDRESSES)

(SECOND GROUP OF 8 ADDRESSES)

A4 A3 A2 A1 A0 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1

A4 A3 A2 A1 A0 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1

(THIRD GROUP OF 8 ADDRESSES)

(FOURTH GROUP OF 8 ADDRESSES)

Example: Interfacing 8K Memory Chips to a ComputerHaving a 20-Bit Address Bus

27 PossibilitiesA19 A18 A17 A16 A15 A14 A13 A12 • • • A0 0 0 0 0 0 0 0 0 - (8K -1) 0 0 0 0 0 0 1 8K - (16K -1) 0 0 0 0 0 1 0 16K - (24K -1) 0 0 0 0 0 1 1 24K - (32K -1)

0 0 0 1 0 0 0 64K - (72K -1)

0 0 0 1 0 1 1 88K - (16K -1)

1 1 1 1 1 1 1 1016K - (1024K -1)

To Chips’ Address Inputs

Example: Interfacing 8K Memory Chips to a ComputerHaving a 20-Bit Address Bus

ADDRESS TABLE:(512K) (256K) (128K) (64K) (32K) (16K) (8K)

A19 A18 A17 A16 A15 A14 A13 0 0 0 0 0 0 0 0 8K 0 0 0 0 0 0 1 16K 0 0 0 0 0 1 0 24K 0 0 0 0 0 1 1

64K 0 0 0 1 0 0 0

88K 0 0 0 1 0 1 1

1016K 1 1 1 1 1 1 1

Of the 27 Possible Ranges, Choose 88K - (96K-1)

Critical Lines Are: A19 A18 A17 A16 A15 A14 A13 0 0 0 1 0 1 1

One Solution to Address Decoding:

A19

A18

A17

A16A15

A14A13

To High-Active ChipSelect

If the Memory Chips have One High-Active Chip Select andOne Low Active Chip Select:

A19A18A17A15

CS1

A16A14A13

CS2

Or, Using a Decoder (74138):

A13A14A15

A17A18A16

ABC

CS3CS2CS1

CS1

A19 CS2

Y0

Y1

Y2Y3

Y4

Y5

Y6

Y7

3-8 Decoder IF SELECTEDA2 A1 A0 /Y0 /Y1 /Y2 /Y3 /Y4 /Y5 /y6 /y7 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 IF NOT SELECTED x x x 1 1 1 1 1 1 1 1

ADDRESS TABLE APPROACH TO MEMORY INTERFACING

1. List in binary the starting address of the address range assigned to each memory chip to be interfaced. (List only the upper address lines, I.e., the ones left over after excluding the ones which must be connected directly to a particular memory chip for its internal selection.

2. Analyze this Address Table and mark with an asterisk (*) all critical address line values for each memory chip in the system. (For each memory chip, the critical address values are the minimum set of address line values which will uniquely specify that chip.) The address line values marked with an asterisk are the ones which must be involved in generating the chip-select signals for that particular chip.

Example: Interfacing Memory Chips to a ComputerHaving a 20-Bit Address Bus

CHIP START.SIZE ADDR (512K) (256K) (128K) (64K) (32K) (16K)

A19 A18 A17 A16 A15 A14 64K 0 0 0 0 0 64K 64K 0 0 0 1 32K 128K 0 0 1 0 0 32K 160K 0 0 1 0 1 32K 192K 0 0 1 1 0 16K 224K 0 0 1 1 1 0 16K 240K 0 0 1 1 1 1 64K 256K 0 1 0 0

Example: Interfacing Memory Chips to a ComputerHaving a 20-Bit Address Bus

CHIP START.SIZE ADDR (512K) (256K) (128K) (64K) (32K) (16K)

A19 A18 A17 A16 A15 A14 64K 0 0 0* 0* 0* 64K 64K 0 0 0* 1* 32K 128K 0 0 1* 0* 0* 32K 160K 0 0 1* 0* 1* 32K 192K 0 0 1* 1* 0* 16K 224K 0 0 1* 1* 1* 0* 16K 240K 0 0 1* 1* 1* 1* 64K 256K 0 1* 0 0

Example: When chips are paired so that one chip coverseven part of an address range and one chip covers the odd part.

CHIP START.SIZE ADDR (512K) (256K) (128K) (64K) (32K) (16K)

A19 A18 A17 A16 A15 A14 64K 0 0 0* 0* 64K 16K 128K 0 0 1* 0* 0* 16K 16K 160K 0 0 1* 0* 1* 16K 32K 192K 0 0 1* 1* 32K 16K 256K 0 1* 0 0 0* 16K 8K 288K 0 1* 0 0 1* 0 8K