Dsp_lab Manual Final

8/3/2019 Dsp_lab Manual Final

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ST.JOHNS COLLEGE OF ENGINEERING & TECHNOLOGYDSP LAB MANUAL

INDEX

CYCLE -I

1. SUM OF THREE SINUSOIDAL SIGNALS

2. FREQUENCY RESPONSE OF ANALOG FILTERS

3. N-POINT FET FOR A GIVEN SEQUENCE

4. POWER SPECTRA; DENSITY

5. LINEAR CONVOLUTION

6. FREQUENCY RESPONSE OF FIR FILTERS

a. Rectangular Window

b. Hanning window

c. Hamming Window

d. Kaiser Window

7. SAMPLING OF A SINUSOIDAL SIGNALS

CYCLE II

1. STUDY OF TMS320C6713 PROCESSOR


3. CIRCULAR CONVOLUTION4. FFT OF 1 DIMENSIONAL SIGNAL

5. POWER SPECTRAL DENSITY OF A SEQUENCE


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PROCEDURE:

1. Open the matlab software by double clicking the icon on desktop.

2. Open the new M-file by using file menu

3. Write the program in new file

4. Click on save and run the icon

5. Perform error check which displayed on command window

6. Plot the waveforms which displays on figure window.

7. Note down the values, which displays on the work space.


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1. GENERATION OF SUM OF THREE SINUSOIDAL SIGNALS

PROGRAM:

fs=100;

t=(1:100)/fs;

s1=sin (2*pi*15*t);

subplot (3,3,1);

plot (t,s1);

title('sin signal with 15HZ');

s2= sin (2*pi*20*t);

subplot(3,3,2);

plot(t,s2);


s3=sin (2*pi*30*t);

subplot(3,3,3);

plot(t,s3);


%sum of three signals

s=s1+s2+s3;

subplot(3,3,4);

plot (t,s);

title ('sum of three sin waves');

%design of elliptical BPF

[b,a]=ellip(4,0.1,40,[10,20]*(2/fs));

[h,w]=freqz(b,a,512);


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subplot(3,3,5);

plot((w*fs)/(2*pi),abs(h));

title('elliptical bandpass filter');

grid;

%filtering the sum signal

z=filter(b,a,s);

subplot(3,3,6);

plot(z);

title('filter output');

%fft of sum signal

y=fft(s,512);

w=((0:255)/256*(fs/2));

subplot (3,3,7);

plot (w,abs(y(1:256)));

title('fft of three sin waves');

grid;

legend('before');

%fft of filter output

k=fft (z,512);

w=((0:255) /256*(fs/2));

subplot (3,3,8);

plot (w,abs(k(1:256)));

title('fft of filter output');

grid;

legend ('after');


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OUTPUT:


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2. FREQUENCY RESPONSE OF ANALOG FILTERS

2a) Program for the design of butter worth analog LPF:

rp=input ('enter passband ripple');

rs=input ('enter stopband ripple');

wp=input ('enter passband frequency');

ws=input ('enter stopband frequency');

fs=input ('enter sampling frequency');

w1=2*(wp/fs);

w2=2*(ws/fs);

[n,wn]=buttord(w1,w2,rp,rs,'s');

[z,p,k]=butter (n,wn);

[b,a]=zp2tf (z,p,k);

[b,a]= butter(n,wn,'s');

w=0:0.01:pi;

[n,om]=freqs(b,a,w);

m=20*log10(abs(n));

an=angle(n);

subplot(2,1,1);

plot(om/pi,m);

ylabel ('grid in db....');

xlabel ('(a) normalised freq...');

subplot (2,1,2);

plot (om/pi,an);

xlabel ('(b) normalised freq...');

ylabel ('phase in radians....');


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INPUT:

enter passband ripple 0.15

enter stopband ripple 30

enter passband frequency 500

enter stopband frequency 1000

enter sampling frequency 2000

OUTPUT:


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2b) Program for the design of butter worth analogHPF:






w1=2*(wp/fs);

w2=2*(ws/fs);


[b,a]= butter(n,wn,'high','s');

w=0:0.01:pi;

[n,om]=freqs(b,a,w);

m=20*log10(abs(n));

an=angle(n);

subplot(2,1,1);

plot(om/pi,m);

ylabel ('grid in db....');


subplot (2,1,2);

plot (om/pi,an);




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INPUT:

enter passband ripple0.15

enter stopband ripple20

enter passband frequency500

enter stopband frequency1000

enter sampling frequency2000

OUTPUT:


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2c) Program for the design of butter bandpass filter






w1=2*wp/fs;

w2=2*ws/fs;


wn=[w1,w2];

[b,a]= butter(n,wn,'bandpass','s');

w=0:0.01:pi;

[b,om]=freqs(b,a,w);

m=20*log10(abs(b));

an=angle(b);

subplot(2,1,1);

plot(om/pi,m);

ylabel ('gain in db....');


subplot (2,1,2);

plot (om/pi,an);




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INPUT:





enter sampling frequency10000

OUTPUT:


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2d) Program for the design of butter bandstop filter






w1=2*wp/fs;

w2=2*ws/fs;


wn=[w1,w2];

[b,a]= butter(n,wn,'stop','s');

w=0:0.01:pi;

[b,om]=freqs(b,a,w);

m=20*log10(abs(b));

an=angle(b);

subplot(2,1,1);

plot(om/pi,m);

ylabel ('gain in db....');


subplot (2,1,2);

plot (om/pi,an);




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INPUT:





OUTPUT:


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3. N - POINT FFT OF GIVEN SEQUENCE

PROGRAM:

fs=100;

%INPUT SEQUENCE

xn=input('enter the input sequence');

%ORDER OF FFT

N=input('enter the no of points in the FFT');

subplot(3,1,1);

stem(xn);

title('input sequence');

L=length(xn);

if(N


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INPUT:

enter the input sequence[1 1 1 1]

enter the no of points in the FFT4

OUTPUT:


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4. POWER SPECTRAL DENSITY

PROGRAM:

fs=100;

t=(1:100)/fs;

s= sin(2*pi*15*t);

subplot(2,1,1);

plot(t,s);

title('Sine Wave');

xlabel('-------> time(sec)');

ylabel('-------> Amp(volts)');

grid;

pxx=psd(s);

subplot(2,1,2);

plot(pxx);

grid;

xlabel('-------> Frequency(Hz)');

ylabel('-------> Magnitudue');


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OUTPUT:


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PROGRAM:

x=input('enter the first sequence');

h=input('enter the second sequence');

% COMPUTING CONVERSION

y=conv(x,h);

subplot(3,1,1);

stem(x);

title('First Sequence');

xlabel('Amp ------>');

ylabel('(a)n------->');

subplot(3,1,2);

stem(h);

title('Second Sequence');

ylabel('Amp-------->');

xlabel('(b)--------->');

subplot(3,1,3);

stem (y);

title('output sequence');

ylabel('amp...');

xlabel('(c)n...');

disp (' the resultant signal is');


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INPUT:

enter the first sequence[1 3 1 2]

enter the second sequence[1 2 1 2]

OUTPUT:


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6. PROGRAM FOR WINDOWING TECHNIQUES

6(a)PROGRAM FOR RECTANGULAR WINDOW

rp= input ('enter the passband ripple');

rs= input ('enter the stopband ripple');

fp= input ('enter the passband frequency');

fs= input ('ente the stopband frequency');

f= input ('enter the sampling frequency');

wp=2*fp/f;

ws=2*fs/f;

num=-20*log10(sqrt (rp*rs))-13;

den=14.6*(fs-fp)/f;

n= ceil(num/den);

n1=n+1;

if(rem(n,2)~=0);

n1=n;

n=n-1;

end;

y=boxcar(n1);

% LOWPASS FILTER

b=fir1(n,wp,y);

[h,om]=freqz(b,1,256);

m=20*log10 (abs(h));

subplot(2,2,1);

plot(om/pi,m);

title('LOW PASS FILTER')


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ylabel('gains in dB....');

xlabel('normalised frequency...');

%HIGHPASS FILTER

b=fir1(n,wp,'HIGH',y);



subplot(2,2,2);

plot(om/pi,m);

title('HIGH PASS FILTER');



%BANDPASS FILTER

wn= [wp ,ws];

b=fir1(n,wn,y);



subplot(2,2,3);

plot(om/pi,m);

title('BAND PASS FILTER')



%BANDSTOP FILTER

b=fir1(n,wn,'STOP',y);




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subplot(2,2,4);

plot(om/pi,m);

title('BAND STOP FILTER')



INPUT:

enter the passband ripple0.03

enter the stopband ripple0.01

enter the passband frequency1400

ente the stopband frequency2000

enter the sampling frequency8000

OUTPUT:


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6(b)PROGRAM FOR KAISER WINDOW






beta=input ('enter the beta value');

wp=2*fp/f;

ws=2*fs/f;


den=14.6*(fs-fp)/f;

n= ceil(num/den);

n1=n+1;

if(rem(n,2)~=0);

n1=n;

n=n-1;

end;

y=kaiser(n1,beta);

% LOWPASS FILTER

b=fir1(n,wp,y);



subplot(2,2,1);

plot(om/pi,m);



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%HIGHPASS FILTER




subplot(2,2,2);

plot(om/pi,m);

title('HIGH PASS FILTER')



%BANDPASS FILTER

wn= [wp ws];

b=fir1(n,wn,y);



subplot(2,2,3);

plot(om/pi,m);




%BANDSTOP FILTER





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subplot(2,2,4);

plot(om/pi,m);




INPUT:






enter the beta value5.8

OUTPUT:


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6(c) PROGRAM FOR HAMMING WINDOW






wp=2*fp/f;

ws=2*fs/f;


den=14.6*(fs-fp)/f;

n= ceil(num/den);

n1=n+1;

if(rem(n,2)~=0);

n1=n;

n=n-1;

end;

y=hamming(n1);

% LOWPASS FILTER

b=fir1(n,wp,y);



subplot(2,2,1);

plot(om/pi,m);




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%HIGHPASS FILTER




subplot(2,2,2);

plot(om/pi,m);




%BANDPASS FILTER

wn= [wp ws];

b=fir1(n,wn,y);



subplot(2,2,3);

plot(om/pi,m);




%BANDSTOP FILTER




subplot(2,2,4);


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plot(om/pi,m);




INPUT:






OUTPUT:


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6(d) PROGRAM FOR HANNING WINDOW






wp=2*fp/f;

ws=2*fs/f;


den=14.6*(fs-fp)/f;

n= ceil(num/den);

n1=n+1;

if(rem(n,2)~=0);

n1=n;

n=n-1;

end;

y=hanning(n1);

% LOWPASS FILTER

b=fir1(n,wp,y);



subplot(2,2,1);

plot(om/pi,m);




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%HIGHPASS FILTER




subplot(2,2,2);

plot(om/pi,m);




%BANDPASS FILTER

wn= [wp ws];

b=fir1(n,wn,y);



subplot(2,2,3);

plot(om/pi,m);




%BANDSTOP FILTER




subplot(2,2,4);


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plot(om/pi,m);




INPUT:






OUTPUT:


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7. SAMPLING OF A SINUSOIDAL SIGNALS

7(a) DOWNSAMPLING

N=50;n=0:1:N-1;

X=sin(2*pi*n/20)+sin(2*pi*n/15);

M=2;

X1=X(1:M:N);

n1=1:1:N/M;

subplot(2,1,1);

stem(n,X);

xlabel('n');

ylabel('X');

title('Input Sequence');

subplot(2,1,2);

stem(n1-1,X1);

xlabel('n');

ylabel('X1');

title('Downsampling Sequence');


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OUTPUT:


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7(b) UPSAMPLING

N=10;

n=0:1:N-1;

X=sin(2*pi*n/10)+sin(2*pi*n/5);

L=3;

X1=[zeros(1,L*N)];

n1=1:1:L*N;

j=1:L:L*N;

X1(j)=X;

subplot(2,1,1);

stem(n,X);

xlabel('n');

ylabel('X');

title('Input Sequence');

subplot(2,1,2);

stem(n1,X1);

xlabel('n');

ylabel('X1');

title('Upsampling Sequence');


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OUTPUT:


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CYCLE-II


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1. INTRODUCTION TO DSP PROCESSORS

A signal can be defined as a function that conveys information, generally about the stateor behavior of a physical system. There are two basic types of signals viz Analog (continuous

time signals which are defined along a continuum of times) and Digital (discrete-time).

Remarkably, under reasonable constraints, a continuous time signal can be adequatelyrepresented by samples, obtaining discrete time signals. Thus digital signal processing is an ideal

choice for anyone who needs the performance advantage of digital manipulation along with

todays analog reality. Hence a processor which is designed to perform the specialoperations(digital manipulations) on the digital signal within very less time can be called as a

Digital signal processor. The difference between a DSP processor, conventional microprocessor

and a microcontroller are listed below.

Microprocessor or General Purpose Processor such as Intel xx86 or Motorola 680xx family

Contains

- only CPU

-No RAM

-No ROM

-No I/O ports

-No Timer

Microcontroller such as 8051 family Contains

- CPU

- RAM

- ROM

-I/O ports

- Timer &

- Interrupt circuitry

Some Micro Controllers also contain A/D, D/A and Flash Memory

DSP Processors such as Texas instruments and Analog Devices Contains

- CPU

- RAM

-ROM

- I/O ports

- Timer


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Optimized for fast arithmetic

- Extended precision

- Dual operand fetch

- Zero overhead loop

- Circular buffering

The basic features of a DSP Processor are

Feature Use

Fast-Multiply

accumulate

Most DSP algorithms, including filtering, transforms, etc. are

multiplication- intensive

Multiple access

memory

architecture

Many data-intensive DSP operations require reading a programinstruction and multiple data items during each instruction cycle

for best performance

Specialized

addressing modes

Efficient handling of data arrays and first-in, first-out buffers in

memory

Specialized programcontrol

Efficient control of loops for many iterative DSP algorithms. Fastinterrupt handling for frequent I/O operations.

On-chip peripherals

and I/O

interfaces

On-chip peripherals like A/D converters allow for small low cost

system designs. Similarly I/O interfaces tailored for common

peripherals allow clean interfaces to off-chip I/O devices.

Key Features

The C6713 DSK is a low-cost standalone development platform that enables users to evaluateand develop applications for the TI C67xx DSP family. The DSK also serves as a hardware

reference design for the TMS320C6713 DSP. Schematics, logic equations and application notes

are available to ease hardware development and reduce time to market.


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The DSK comes with a full compliment of on-board devices that suit a wide variety of

application environments. Key features include:

A Texas Instruments TMS320C6713 DSP operating at 225 MHz. An AIC23 stereo codec

8 Mbytes of synchronous DRAM

512 Kbytes of non-volatile Flash memory (256 Kbytes usable in default configuration) 4 user accessible LEDs and DIP switches

Software board configuration through registers implemented in CPLD

Configurable boot options

Standard expansion connectors for daughter card use

JTAG emulation through on-board JTAG emulator with USB host interface or externalemulator

Single voltage power supply (+5V)


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2.CHITECTURE OF 6713 DSP PROCESSOR

This chapter provides an overview of the architectural structure of the TMS320C67xx DSP,

which comprises the central processing unit (CPU), memory, and on-chip peripherals. The

C67xE DSPs use an advanced modified Harvard architecture that maximizes processing powerwith eight buses. Separate program and data spaces allow simultaneous access to program

instructions and data, providing a high degree of parallelism. For example, three reads and one

write can be performed in a single cycle.Instructions with parallel store and application-specificinstructions fully utilize this architecture. In addition, data can be transferred between data and

program spaces. Such Parallelism supports a powerful set of arithmetic, logic, and bit-mani

pulation operations that can all be performed in a single machine cycle. Also, the C67xx DSPincludes the control mechanisms to manage interrupts, repeated operations, and function calling.

Fig 2 1 BLOCK DIAGRAM OF TMS 320VC 6713


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Bus Structure

The C67xx DSP architecture is built around eight major 16-bit buses (four program/data busesand four address buses):

_ The program bus (PB) carries the instruction code and immediate operands from program

memory.

_ Three data buses (CB, DB, and EB) interconnect to various elements, such as the CPU, dataaddress generation logic, program address generation logic, on-chip peripherals, and data

memory.

_ The CB and DB carry the operands that are read from data memory.

_ The EB carries the data to be written to memory.

_ Four address buses (PAB, CAB, DAB, and EAB) carry the addresses needed for instruction

execution. The C67xx DSP can generate up to two data-memory addresses per cycle using the

two auxiliary register arithmetic units (ARAU0 and ARAU1). The PB can carry data operandsstored in program space (for instance, a coefficient table) to the multiplier and adder for

multiply/accumulate operations or to a destination in data space for data move instructions

(MVPD and READA). This capability, in conjunction with the feature of dual-operand read,supports the execution of single-cycle, 3-operand instructions such as the FIRS instruction. The

C67xx DSP also has an on-chip idirectional bus for accessing on-chip peripherals. This bus is

connected to DB and EB through the bus exchanger in the CPU interface. Accesses that use this

bus can require two or more cycles for reads and writes, depending on the peripherals structure.

Central Processing Unit (CPU)

The CPU is common to all C67xE devices. The C67x CPU contains:

_ 40-bit arithmetic logic unit (ALU)

_ Two 40-bit accumulators

_ Barrel shifter

_ 17 17-bit multiplier

_ 40-bit adder

_ Compare, select, and store unit (CSSU)

_ Data address generation unit

_ Program address generation unit


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Arithmetic Logic Unit (ALU)

The C67x DSP performs 2s-complement arithmetic with a 40-bit arithmetic logic unit (ALU)and two 40-bit accumulators (accumulators A and B). The ALU can also perform Boolean

operations. The ALU uses these inputs:

_ 16-bit immediate value

_ 16-bit word from data memory

_ 16-bit value in the temporary register, T

_ Two 16-bit words from data memory

_ 32-bit word from data memory

_ 40-bit word from either accumulator

The ALU can also function as two 16-bit ALUs and perform two 16-bit operationssimultaneously.

Fig 2 2 ALU UNIT


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Accumulators

Accumulators A and B store the output from the ALU or the multiplier/adder block. They canalso provide a second input to the ALU; accumulator A can be an input to the multiplier/adder.

Each accumulator is divided into three parts:

_ Guard bits (bits 3932)

_ High-order word (bits 3116)

_ Low-order word (bits 150)

Instructions are provided for storing the guard bits, for storing the high- and the low orderaccumulator words in data memory, and for transferring 32-bit accumulator words in or out of

data memory. Also, either of the accumulators can be used as temporary storage for the other.

Barrel Shifter

The C67x DSP barrel shifter has a 40-bit input connected to the accumulators or to data memory(using CB or DB), and a 40-bit output connected to the ALU or to data memory (using EB). The

barrel shifter can produce a left shift of 0 to 31 bits and a right shift of 0 to 16 bits on the input

data. The shift requirements are defined in the shift count field of the instruction, the shift countfield (ASM) of status register ST1, or in temporary register T (when it is designated as a shift

count register).The barrel shifter and the exponent encoder normalize the values in an

accumulator in a single cycle. The LSBs of the output are filled with 0s, and the MSBs can beeither zero filled or sign extended, depending on the state of the sign-extension mode bit (SXM)

in ST1. Additional shift capabilities enable the processor to perform numerical scaling, bit

extraction, extended arithmetic, and overflow prevention operations.

Multiplier/Adder Unit

The multiplier/adder unit performs 17 _ 17-bit 2s-complement multiplication with a 40- bitaddition in a single instruction cycle. The multiplier/adder block consists of several elements: a

multiplier, an adder, signed/unsigned input control logic, fractional control logic, a zero detector,

a rounder (2s complement), overflow/saturation logic, and a 16-bit temporary storage register(T). The multiplier has two inputs: one input is selected from T, a data-memory operand, or

accumulator A; the other is selected from program memory, data memory, accumulator A, or an

immediate value. The fast, on-chip multiplier allows the C54x DSP to perform operationsefficiently such as convolution, correlation, and filtering. In addition, the multiplier and ALU

together execute multiply/accumulate (MAC) computations and ALU operations in parallel in a

single instruction cycle. This function is used in determining the Euclidian distance and inimplementing symmetrical and LMS filters, which are required for complex DSP algorithms. Seesection 4.5, Multiplier/Adder Unit, on page 4-19, for more details about the multiplier/adder unit.


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Fig 2 3 MULTIPLIER/ADDER UNIT

These are the some of the important parts of the processor and you are instructed to

go through the detailed architecture once which helps you in developing the

optimized code for the required application.

PROCEDURE:

1. Open Code Composer Studio, make sure the DSP kit is turned on.

2. Start a anew project using Project-new pull down menu, save it in a separatedirectory (c:\ti\myprojects)with name iconv.pjt.

3. Add the source files conv.asm to the project using Projectadd files toproject pull down menu

4. Add the linker command file hello.cmd(Path:c;\ti\tutorial\dsk6713\hello1\hello.cmd)

5. Add the run time support library file rts6700.lib(Path:c;\ti\c600\cgtools\lib\rts6700.lib)

6. Compile the program using the Project-compile pull down menu or bychecking the shortcut icon on the left side of program window.

7. Build the program using the Project-Build pull down menu or by clicking theshortcut icon on the left side of program window.

8. Load the program(icnov.out) in program memory of DSP chip using the File-load program pull down menu

9. To View output graphicallySelect viewgraphtime and frewuency.


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PROGRAM:

#include

int x[15],h[15],y[15];

main()

{

int i,j,m,n;

printf("\n enter value for m");

scanf("%d",&m);

printf("\n enter value for n");

scanf("%d",&n);

printf("Enter values for i/p x(n):\n");

for(i=0;i


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{

y[i]=0;

for(j=0;j


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OUTPUT WAVE FORM:


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2. CIRCULAR CONVOLUTION

PROGRAM:

#include

int m,n,x[30],h[30],y[30],i,j, k,x2[30],a[30];

void main()

{

printf(" Enter the length of the first sequence\n");

scanf("%d",&m);

printf(" Enter the length of the second sequence\n");

scanf("%d",&n);

printf(" Enter the first sequence\n");

for(i=0;i


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x[i]=0;

m=n;

}

y[0]=0;

a[0]=h[0];

for(j=1;j


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for(i=0;i


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3.FAST FOURIER TRANSFORM

PROGRAM:

#include

#define PTS 64

#define PI 3.14159265358979// # of points for FFT

typedef struct{float real,imag;} COMPLEX;

void FFT(COMPLEX*Y, int n);

float iobuffer[PTS];

float x1[PTS];

short i;

short buffercount=0;

int upper_leg,lower_leg;

//iobuffer

short flag=0;

//full

COMPLEX w[PTS];

COMPLEX samples[PTS];

main()

{

for (i=0;i


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}

for (i=0;i freq, 64---> sampling freq*/

samples[i].real=0.0;

samples[i].imag=0.0;

}

for (i=0;i


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void FFT(COMPLEX *y,int N)

{

COMPLEX temp1,temp2;

int i,j,k;


int leg_diff;

int num_stages=0;

int index,step;

i=1;

do

{

num_stages +=1;

i=i*2;

}while(i!=N);

leg_diff=N/2;

for(i=0;i


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temp2.real=(y[upper_leg]).real-(y[lower_leg]).real;

temp2.imag=(y[upper_leg]).imag+(y[lower_leg]).imag;

(y[lower_leg]).real=temp2.real*(w[index]).real-temp2.imag*(w[index]).imag;

(y[lower_leg]).imag=temp2.real*(w[index]).imag+temp2.imag*(w[index]).real;

(y[upper_leg]).real = temp1.real;

(y[upper_leg]).imag = temp1.imag;

}

index += step;

}

leg_diff = leg_diff/2;

step *=2;

}

j=0;

for (i=1; i


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temp1.imag = (y[j]). imag;

(y[j]).real = (y[i]).real;

(y[j]).imag = (y[i]).imag;

(y[i]).real = temp1.real;

(y[i]).imag = temp1.imag;

}

}

return;

}


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RESULT: Input


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OUTPUT:


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5.POWER SPECTRAL DENSITY OF A SEQUENCE

PROGRAM:

#include

#define pts 128

#define pi 3.14159265358979

typedef struct { float real,imag;}complex;

void fft (complex *y, int n);

float iobuffer[pts];

float x1[pts],x[pts];

int n,k,i;

//short i;

short buffercount=0;

short flag =0;

float y[128];

complex w[pts];

complex samples [pts];

main()

{

float sum=0.0;

int n,k,i;

for (i=0;i


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for (i=0;i


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{

x1[i] = sqrt (samples[i].real*samples[i].real+samples[i].imag*samples[i].imag);

}

}

//fft.c:

void fft(complex *y, int N)

{

complex temp1,temp2;

int i,j,k;


int leg_diff;

int num_stages =0;

int index,step;

i=1;

do

{

num_stages +=1;

i=i*2;

}

while(i!=N);

leg_diff=N/2;

step = (pts *2)/N;

for (i=0; i


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for(j=0; j


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{

j=j-k;

k=k/2;

}

j=j+k;

if (i


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INPUT:


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OUTPUT:


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Dsp_lab Manual Final

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Transcript of Dsp_lab Manual Final