Document Description Documents Files Comments - bnl.gov · PDF fileSpecific logic diagram for...

15
NSLS II 18ID IRR Front End Phase 2 Equipment Protection System Documents List G. Ganetis 10/10/2017 Beam Line __18ID FIXFront End –Phase 2________________________ The following list represents the documents that summarize the review for the Front End Equipment Protection System Phase 2: Document Description Documents Files Comments Front End and SR Logic Diagram (Water & Vacuum interlocks) LTELBLEIEPS010190_REVB.pdf Overall basic logic diagram for Storage ring and front end water flow and vacuum EPS interlocks. Insertion Devices Front End Logic Diagram LTELBLEIEPS010191_REVD.pdf Specific logic diagram for all ID Front Ends Electrical Schematics Front End EPS Chassis –Cell 18 Rack Interconnection Wiring for 18ID in cell 18 rack E4. LTELSREIEPS011890_REVB.pdf LTELSRPSRAK118591_REVE.pdf ID Front End EPS connects to same cell – 18ID goes to Cell 18 EPS Chassis 18ID Front End EPS test report for Phase 2 front end. 18ID Front End EPS test report for Phase 1 front end. cell 18 test report phaseII 9_26_2017.pdf 18ID Front End EPS Phase 1 Test Report 8_28_2017 .pd This report covers only Phase 2 front end. This includes ID Photon Shutter, GV2, Beamline Vacuum Interlocks This report covers only Phase 1 front end. This includes ID Bending Magnet Shutter, GV1, ID open gap, and Front End water interlocks. Design Description for Storage Ring and Front Ends EPS PSCASDSPCEPS001.pdf This document gives an overview of the many interlock functions that the EPS preforms. ( A copy is available upon request) 18ID EPS Front End Program Stored (PLC located in Cell 18 EPS chassis) LTELSREIEPS011870_REVD.pdf Drawing represents the storing of the PLC program in the Electrical Design room.

Transcript of Document Description Documents Files Comments - bnl.gov · PDF fileSpecific logic diagram for...

Page 1: Document Description Documents Files Comments - bnl.gov · PDF fileSpecific logic diagram for all ID Front Ends ... Rack Interconnection Wiring ... PLC program in the Electrical Design

NSLS II 18‐ID IRR Front End Phase 2 Equipment Protection System Documents List G. Ganetis 10/10/2017 

 

        

Beam Line __18‐ID FIX‐Front End –Phase 2________________________ 

   

 

The following list represents the documents that summarize the review for the Front End 

Equipment Protection System Phase 2:  

 

Document Description  Documents Files    Comments 

 Front End and SR  Logic Diagram  (Water & Vacuum interlocks)  

 LT‐EL‐BL‐EI‐EPS‐0101‐90_REV‐B.pdf 

   Overall basic logic diagram for Storage ring and front end water flow and vacuum EPS interlocks. 

 Insertion Devices  Front End Logic Diagram 

LT‐EL‐BL‐EI‐EPS‐0101‐91_REV‐D.pdf 

   Specific logic diagram for all ID Front Ends  

Electrical Schematics Front End EPS Chassis –Cell 18 ‐ ‐ Rack Interconnection Wiring for 18‐ID  in cell 18 rack E4.  

LT‐EL‐SR‐EI‐EPS‐0118‐90_REV‐B.pdf ‐ ‐ LT‐EL‐SR‐PS‐RAK‐1185‐91_REV‐E.pdf 

   ID Front End EPS connects to same cell – 18‐ID  goes to Cell 18 EPS Chassis   

18‐ID Front End EPS test report for Phase 2 front end.   18‐ID Front End EPS test report for Phase 1 front end.  

cell 18 test report phaseII 9_26_2017.pdf    18‐ID Front End EPS Phase 1 Test Report 8_28_2017 .pd 

  This report covers only Phase 2 front end. This includes ID Photon Shutter, GV2,  Beamline Vacuum Interlocks  This report covers only Phase 1 front end. This includes ID Bending Magnet Shutter, GV1, ID open gap, and Front End water interlocks. 

Design Description for Storage Ring and Front Ends EPS 

PS‐C‐ASD‐SPC‐EPS‐001.pdf      This document gives an overview of the many interlock functions that the EPS preforms. ( A copy is available upon request) 

18‐ID EPS Front End  Program Stored (PLC located in Cell 18 EPS chassis)  

LT‐EL‐SR‐EI‐EPS‐0118‐70_REV‐D.pdf   

  Drawing represents the storing of the PLC program in the Electrical Design room. 

 

 

Page 2: Document Description Documents Files Comments - bnl.gov · PDF fileSpecific logic diagram for all ID Front Ends ... Rack Interconnection Wiring ... PLC program in the Electrical Design
Page 3: Document Description Documents Files Comments - bnl.gov · PDF fileSpecific logic diagram for all ID Front Ends ... Rack Interconnection Wiring ... PLC program in the Electrical Design
Page 4: Document Description Documents Files Comments - bnl.gov · PDF fileSpecific logic diagram for all ID Front Ends ... Rack Interconnection Wiring ... PLC program in the Electrical Design
Page 5: Document Description Documents Files Comments - bnl.gov · PDF fileSpecific logic diagram for all ID Front Ends ... Rack Interconnection Wiring ... PLC program in the Electrical Design
Page 6: Document Description Documents Files Comments - bnl.gov · PDF fileSpecific logic diagram for all ID Front Ends ... Rack Interconnection Wiring ... PLC program in the Electrical Design
Page 7: Document Description Documents Files Comments - bnl.gov · PDF fileSpecific logic diagram for all ID Front Ends ... Rack Interconnection Wiring ... PLC program in the Electrical Design
Page 8: Document Description Documents Files Comments - bnl.gov · PDF fileSpecific logic diagram for all ID Front Ends ... Rack Interconnection Wiring ... PLC program in the Electrical Design

o0.5ANGULAR TOLERANCE

+

+

-

-

+-

.XXX

.XX

.X

-+

DECIMAL TOLERANCES

INTEGER TOLERANCES

MIN .005MAX .03

125

DATE

JOB NUMBER

INTERPRET DRAWING AS PER

ANSI Y14.5 OR Y32.2

FINISH

BREAK SHARP

CORNERS AND EDGES

UNLESS OTHERWISE SPECIFIED

DRWN BY

REV

SHEET 0F

DRAWING NUMBER

.06

.030

.015

.010

ESH&Q

RISK LEVEL

A-2

OUTSTANDING

ECN'S

UNSPECIFIED RADII .02 MAXCHK BY

ENG APP

SUPV APP

QA APP

ESH APP

DRAWING DIRECTORY

USED ON DWG. NO.

-+

UNLESS OTHERWISE SPECIFIED

DIMENSIONS ARE IN INCHES

DIMENSIONS IN [*.**] ARE

MILLIMETERS EQUIV. FOR REF. ONLY

REV

4 3

A

B

C

D

4 3 2 1

D

C

B

A

12

SCALE: N/A 1 2

DESCRIPTION BYDATE CHECKED APP

LT-EL-BL-EI

56

6 5

LT-EL-BL-EI-EPS-0101-90 B

A INITIAL RELEASE

S. JARZABKOWSKI 9/09/2014

J. MALLEY

A. CASTIBLANCO

G. GANETIS

E. CHESWICK

B. LEE

SEJ9/09/2014

LT

-EL

-BL-E

I-E

PS

-01

01-9

0

LOGIC DIAGRAM,

FRONT END EPS INTERLOCK

JM AC

COMPUTER REPRODUCIBLE

CELL CONTROLLER

BEAM POSITION

INTERLOCK

RF PPS A CHAIN RF FPGA

RAMP DOWNRF PPS B CHAIN

RF PIN DIODE/RELAY

H2O SENSOR INPUT 1

H2O SENSOR INPUT 12

RESET

CELL PLC CHASSIS

CELL H2O SUM INPUT 1

CELL H2O SUM INPUT 30

RESET

IN- 0 (RED)

MAIN EPS PLC CHASSIS

LOCATED IN COMPUTER ROOM RGC2

NETWORKED WATER FLOW INTERLOCK TO RF SYSTEM

( RF INTERFACE)

C30 VACUUME VALVE OPEN

RESET

(HMI)

C30 BMPS CLOSED

OPEN BPMS

(HMI)

C30 VACUUME

VALVE OPEN

CLOSE BPMS

(HMI)

BPMS SOLENOID

COMMAND

CELL 30 EPS CHASSIS NEAR SLM 30

BEAMLINE

CLOSED BPMS STATUS

CLOSED VACUUME VALVE STATUS

NETWOKED

SLM BMPS

SLM VAC VALVE

RF TEST MODE FROM KSU

INHIBITS H20 INTERLOCK

FROM RF INTERFACE

Delay to OFF

5 ms

RF CAVITY POWER

OFF READBACK

FROM RF INTERFACE

WATER FLOW INTERLOCK BACKUP

(TO RF SYSTEM)

RF CONTACTORS OPEN

FROM PPS RF INTERFACE

CELL VAC & DUMP SUM INPUT 1

CELL VAC & DUMP SUM INPUT 1

PPS A

CHAIN

PPS B

CHAIN

SY

S 1

SY

S 1

SY

S 2

A

SY

S 2

B

24 V

IN- 3

IN- 4

BLU/BLK

BLK/WHT

RED

IN- 1 (WHT)

IN- 2 (GRN)

OUT- 1

OUT- 1 (RED/BLK)

VACUUM

RTD

RESET

H2O TRIP SIGNAL

BEAM & VACUUM TRIP SIGNAL

K75

K74

K75 K74

24 VK79

MASTER SHUTTER

ENABLE

COMMAND FROM

EPICS

MASTER SHUTTER

ENABLE SWITCH

725 MCR

IN- 5

OUT- 3

K80

SIGNAL TO

FRONT END

PPS

GLOBAL MASTER

SHUTTER TO ALL FE

EPS PLC’S

(NETWORKED)

NETWORKED

PPS/EPS RF KLY D INTERFACE

OUT- 2

CELL CONTROLLER

BEAM POSITION

INTERLOCK

OUT- 0 (BLU)

9/09/2014

9/09/2014

9/10/2014

9/09/2014

9/09/2014

B REVISED PER ECN LT-ECN-015-1338 SEJ10/7/2015 JM AC

BEAM DUMP

ETHERNET

RF TEST MODE

Page 9: Document Description Documents Files Comments - bnl.gov · PDF fileSpecific logic diagram for all ID Front Ends ... Rack Interconnection Wiring ... PLC program in the Electrical Design

REV

4 3

A

B

C

D

4 3 2 1

D

C

B

A

12

REV

SHEETSCALE: N/A 2 20F

DRAWING NUMBER

DESCRIPTION BYDATE CHECKED APP

LT-EL-BL-EI

56

6 5

B

B SEE SHEET 1

DRAWING DIRECTORY

LT-EL-BL-EI-EPS-0101-90

LT

-EL-B

L-E

I-E

PS

-01

01-9

0

10/07/2015 SEJ JM AC

COMPUTER REPRODUCIBLE

ID3 FRONT END EPS PLC

ID5 FRONT END EPS PLC

ID10 FRONT END EPS PLC

ID11 FRONT END EPS PLC

ID23 FRONT END EPS PLC

ID28 FRONT END EPS PLC

PPS SHUTTER POSITIONS

SHUTTER SOLENOID COMMANDS

VACUUM VALVE POSITIONS

FAST VALVE POSITIONS

BMPS POSITION AND SOLENOID

PPS SHUTTER POSITIONS

SHUTTER SOLENOID COMMANDS

VACUUM VALVE POSITIONS

FAST VALVE POSITIONS

BMPS POSITION AND SOLENOID

PPS SHUTTER POSITIONS

SHUTTER SOLENOID COMMANDS

VACUUM VALVE POSITIONS

FAST VALVE POSITIONS

BMPS POSITION AND SOLENOID

PPS SHUTTER POSITIONS

SHUTTER SOLENOID COMMANDS

VACUUM VALVE POSITIONS

FAST VALVE POSITIONS

BMPS POSITION AND SOLENOID

PPS SHUTTER POSITIONS

SHUTTER SOLENOID COMMANDS

VACUUM VALVE POSITIONS

FAST VALVE POSITIONS

BMPS POSITION AND SOLENOID

PPS SHUTTER POSITIONS

SHUTTER SOLENOID COMMANDS

VACUUM VALVE POSITIONS

FAST VALVE POSITIONS

BMPS POSITION AND SOLENOID

ACCESS PERMIT TO PPS I/O 7 BOX RELAY K7

P2 ICR DOOR ACCESS

PUSHBUTTON

RF OFF

DIPOLE OFF

INJECTION SHUTTER CLOSED AND

INJECTION BENDING MAGNET OFF

CELL 30 EPS PLC CHASSIS P2

ACCESS PERMIT TO PPS I/O 30 BOX RELAY K7

RF OFF

DIPOLE OFF

INJECTION SHUTTER CLOSED AND

INJECTION BENDING MAGNET OFF

CELL 1 EPS PLC CHASSIS P2

ACCESS PERMIT TO PPS I/O 1 BOX RELAY K7

P2 DOOR ACCESS

PUSHBUTTON

RF OFF

DIPOLE OFF

INJECTION SHUTTER CLOSED AND

INJECTION BENDING MAGNET OFF

CELL 25 EPS PLC CHASSIS P1

ACCESS PERMIT TO PPS I/O 25 BOX RELAY K7

P1 DOOR ACCESS

PUSHBUTTON

RF OFF

DIPOLE OFF

INJECTION SHUTTER CLOSED AND

INJECTION BENDING MAGNET OFF

CELL 7 EPS PLC CHASSIS P3P3 DOOR ACCESS

PUSHBUTTON

ACCESS PERMIT TO PPS I/O 19 BOX RELAY K7RF OFF

DIPOLE OFF

INJECTION SHUTTER CLOSED AND

INJECTION BENDING MAGNET OFF

CELL 13 EPS PLC CHASSIS P4P4 DOOR ACCESS

PUSHBUTTON

ACCESS PERMIT TO PPS I/O 13 BOX RELAY K7RF OFF

DIPOLE OFF

INJECTION SHUTTER CLOSED AND

INJECTION BENDING MAGNET OFF

CELL 19 EPS PLC CHASSIS P5P5 DOOR ACCESS

PUSHBUTTON

INJECTION SHUTTER CLOSED AND

INJECTION BENDING MAGNET OFF

(from boosterPPS)

(networked)

(networked)

(networked)

(networked)

(networked)

(networked)

STORAGE RING VACUUM INTERLOCK

SUMMATION TO BOOSTER SIGNAL

STORAGE RING VACUUM

INTERLOCK

STORAGE RING VACUUM

INTERLOCK

STORAGE RING VACUUM

INTERLOCK

STORAGE RING VACUUM

INTERLOCK

STORAGE RING VACUUM

INTERLOCK

STORAGE RING VACUUM

INTERLOCK CELL1

STORAGE RING VACUUM

INTERLOCK CELL30

(networked)

J6-1,2

J9-11 INPUT

J6-6 +24J9-1

J6-1,2

J9-11 INPUT

J6-6 +24

J6-1,2

J9-11 INPUT

J6-6 +24

J6-1,2

J9-11 INPUT

J6-6 +24

J6-1,2

J9-11 INPUT

J6-6 +24

J6-1,2

J9-11 INPUT

J6-6 +24J9-1

J1-21INPUT

J1-9 +24

J9-3

TB25-12A (Wht/blk/red)

TB25-7A (Red/Wht)

TB25-12A (22)

TB25-7A (12)

TB25-12A (Blk/Red/Wht)

TB25-7A (Blk/Wht)

TB25-12B (23)

TB25-7A (12)

TB25-11B

(Red/Grn)

TB25-6A

(Blu/Blk)

TB25-13A (24)

TB25-6A (11)

C30 BMPS CLOSED

C30 VACUUME VALVE OPEN

CLOSED VACUUME VALVE

C30 BMPS OPEN

TB25-11B (21)

TB25-6A (11)

STORAGE RING VACUUM

INTERLOCK

TB25-11B (Org/Grn)

TB25-6A (Blu/Blk/Wth)

J9-2

J9-2

J9-2

J9-1

J9-1

J9-2

J9-1

J9-2

J9-2

J9-1

J9-4

TB25-12A (22)

TB25-7A (12)

TB25-12A (22)

TB25-7A (12)

TB25-7A (12)

TB25-12A (22)

TB25-6A (11)

TB25-11B (21)

TB25-6A (11)

TB25-11B (21)

TB25-6A (11)

TB25-11B (21)

J6-6 +24V

Key switch

RG-E4

CELL 3 EPS PLC CHASSIS P2

DIPOLE OFF

READBACK

(Dipole PPS interface)DIPOLE OFF

READBACK

NETWORKED VARIABLE

COMPUTER ROOM EPS PLC

RF POWER SUPPLY

CONTACTORS OFF

READBACK

(RF PPS interface)

RF OFF

READBACKNETWORKED VARIABLE

J9-11INPUT

J6-6 +24TB25-6A (11)

TB25-13A (24)

Page 10: Document Description Documents Files Comments - bnl.gov · PDF fileSpecific logic diagram for all ID Front Ends ... Rack Interconnection Wiring ... PLC program in the Electrical Design

o0.5ANGULAR TOLERANCE

+

+

-

-

+-

.XXX

.XX

.X

-+

DECIMAL TOLERANCES

INTEGER TOLERANCES

MIN .005MAX .03

125

DATE

JOB NUMBER

INTERPRET DRAWING AS PER

ANSI Y14.5 OR Y32.2

FINISH

BREAK SHARP

CORNERS AND EDGES

UNLESS OTHERWISE SPECIFIED

DRWN BY

REV

SHEET 0F

DRAWING NUMBER

.06

.030

.015

.010

ESH&Q

RISK LEVEL

A-2

OUTSTANDING

ECN'S

UNSPECIFIED RADII .02 MAXCHK BY

ENG APP

SUPV APP

QA APP

ESH APP

DRAWING DIRECTORY

USED ON DWG. NO.

-+

UNLESS OTHERWISE SPECIFIED

DIMENSIONS ARE IN INCHES

DIMENSIONS IN [*.**] ARE

MILLIMETERS EQUIV. FOR REF. ONLY

REV

4 3

A

B

C

D

4 3 2 1

D

C

B

A

12

SCALE: N/A 1 2

DESCRIPTION BYDATE CHECKED APP

LT-EL-BL-EI

56

6 5

LT-EL-BL-EI-EPS-0101-91 D

A INITIAL RELEASE

S. JARZABKOWSKI 9/09/2014

J. MALLEY

A. CASTIBLANCO

G. GANETIS

E. CHESWICK

B. LEE

SEJ9/09/2014

LT

-EL

-BL-E

I-E

PS

-01

01-9

1

LOGIC DIAGRAM,

FRONT END EPS

JM AC

P1

P2

ID_PS_CLOSE_A1

ID_SSA_CLOSE_A1

ID_SSB_CLOSE_B1

ID_REQUEST_TO_OPEN/CLOSE

ID_PS_OPEN_A3

ID_SSA_OPEN_A2

ID_SSB_OPEN_A4

ID_SSA_SOLENOID

ID_PS_SOLENOID

ID_GV1_OPEN

ID_BMPS_CLOSE_COMMAND

LOW_POWER

ID_BMPS_OPEN_COMMAND

ID_BMPS_SOLENOID

FE_COMMAND RAD MONITOR SIGNAL

ID_BE_ENABLE

15 Sec DELAY

ID_XX_KIRK KEY

SOLENOID

P3

FE EPS LOGIC

ID_VACU_GV2

(Enable GV2 signal)

ID_VACU_GV1

(Enable GV1 signal)

INSERTION_D_OPEN

ID_BMPS_CLOSE

(Same as page2)

(Same as page2)

(Same as page2)

ID_SSB_SOLENOID

TO VACUUM PLC

TO PPS I / O BOX

GLOBAL_MS_ENA

COMPUTER REPRODUCIBLE

9/09/2014

9/09/2014

9/10/2014

9/09/2014

9/09/2014

INJ SHUTTER CLOSED AND BM OFF

B REVISED PER ECN 015-1026 SEJ11/5/2014 JM AC

C REVISED PER ECN 015-1121 CG1-12-15

CYCLE LIMITER

4 SEC

FE_COMM_LIMITED

SSA

SSB

PS

OPEN_TIME_FAULT

SSA

SSB

PS

CLOSE_TIME_FAULT

CLOSE_TIME_FAULT

ID_PS_CLOSE_A1

ID_GV2_OPEN

ID_FV_OPEN

SEE SHEET 2

0.5 SEC

DELAY

0.5 SEC

DELAY

JM AC

D REVISED PER ECN LT-ECN-015-1334 SEJ10/7/2015 JM AC

FV CM OUT SYS READY

GV2 OPEN

FV CM CLOSE OUTENABLE KIRK KEY

Page 11: Document Description Documents Files Comments - bnl.gov · PDF fileSpecific logic diagram for all ID Front Ends ... Rack Interconnection Wiring ... PLC program in the Electrical Design

REV

4 3

A

B

C

D

4 3 2 1

D

C

B

A

12

REV

SHEETSCALE: N/A 2 20F

DRAWING NUMBER

DESCRIPTION BYDATE CHECKED APP

LT-EL-BL-EI

56

6 5

D

SEE SHEET 1

DRAWING DIRECTORY

LT-EL-BL-EI-EPS-0101-91

LT

-EL-B

L-E

I-E

PS

-01

01-9

1

INSERTION_D_OPEN

INSERTION_D_INSTALLED

ID_BMPS_CLOSE

ID_GV1_OPEN

ID_BMPS_OPEN

ID_FV_CM_CLOSE_OUT

ID_FV_CM_OUT_SYS_READY

ID_FV_OPEN

ID_SSA_OPEN_A2

ID_SSB_OPEN_A4

ID_GV2_OPEN

RESET

ID_B_DUMP_1

FE EPS LOGIC

LOW POWER

ID_PS_CLOSE_A1(Same as page1)

ID_B_DUMP_2

ID_BMPS_OPEN_OUT

ID_PS_OPEN_OUT

INSERTION_D_OPEN_OUT

HEART BEAT (WATCH DOG)

TO CELL CONTROLLER

COMPUTER REPRODUCIBLE

SSACLOSE TIME FAULT

SSB CLOSE TIME FAULT

PS CLOSE TIME FAULT

Page 12: Document Description Documents Files Comments - bnl.gov · PDF fileSpecific logic diagram for all ID Front Ends ... Rack Interconnection Wiring ... PLC program in the Electrical Design

FIRMWARE/SOFTWARE/PROGRAMMING LOGIC DESCRIPTION:

EPS Front End PLC program that monitors and controls the front end components within the Cell and its data transfer with the EPS Controller

located in the 740 building computer room.

PROGRAM RSLogix 5000 VERSION 20.1 DEVICE Compact Logix Controller L32E

OPERATING SYSTEM Windows PROGRAMMING

METHOD Ladder Logic

FILE EPS_BOX_cell18_V25_FM_URV.ACD

o0.5ANGULAR TOLERANCE

++--+-

.XXX.XX

.X

-+DECIMAL TOLERANCES

INTEGER TOLERANCES

MIN .005MAX .03

125

COMPUTER REPRODUCIBLE

DATE

JOB NUMBER

UNLESS OTHERWISE SPECIFIED

FINISH

BREAK SHARPCORNERS AND EDGES

UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHESDIMENSIONS IN [*.**] ARE

MILLIMETERS EQUIV. FOR REF. ONLY

INTERPRET DRAWING AS PER

ANSI Y14.5 OR Y32.2

DRWN BY

REV

SHEETSCALE: N/A 1 10F

DRAWING NUMBER

LT-EL-SR-EI

.06

.030

.015

.010

RISK LEVELESH&Q

A-2

ECN'S

OUTSTANDING

UNSPECIFIED RADII .02 MAXLT-EL-SR-EI-EPS-0118-70 D

CHK BY

ENG APP

SUPV APP

QA APP

ESH APP

DRAWING DIRECTORY

USED ON DWG. NO.

-+

LT

- EL

- SR

- EI -

EPS

-011

8 -70

A. CastiblancoM. Pfeffer

04/01/14

NSLS-II- STORAGE RING EPS CHASSIS LOGIC CELL 18

A. Castiblanco

G. GanetisE.CHESWICK

B.LEE

04/01/14

04/01/14

REV DESCRIPTION BY DATE CHK APP

INITIAL RELEASE 04/01/14AC ACMPA

04/01/14

04/10/14

04/11/14

REVISED PER ECN 016-1524 06/20/16AC ACMPB

PROGRAMMABLE LOGIC

REVISED PER ECN 017-1657 11/04/16AC ACMPCREVISED PER ECN 017-1855 10/04/17AC ACMPD

Page 13: Document Description Documents Files Comments - bnl.gov · PDF fileSpecific logic diagram for all ID Front Ends ... Rack Interconnection Wiring ... PLC program in the Electrical Design

D4

D2

D1

+24V

+24V

+24V

+24V

+24V

+24V

+24V

+24V

+24V

+24V +2

4V

+24V

+24V

+24V

+24V

+24V

D3

+24V

+24V

+24V

SEJ 10/27/2015 JM

1 1

LT-E

L-S

R-E

I-EP

S-0

118-

90

B

STORAGE RING EPS CHASSIS, CELL 18

LT-EL-SR-EI-EPS-0118-90

J. MALLEY

10/27/2015

10/28/2015

NOTES: UNLESS OTHERWISE SPECIFIED1. ALL RESISTOR VALUES ARE IN OHMS, 1%, 100PPM.2. ALL CAPACITOR VALUES ARE IN MICROFARADS, 50V.3 ALL INDUCTOR VALUES ARE IN MICROHENRIES.

E. CHESWICK

G. GANETIS

A. CASTIBLANCO

10/28/201510/28/2015

WIRING DIAGRAM

1.03.06.02

R. LEE

S. JARZABKOWSKI

A-2N/A

125

o

ANGULAR TOLERANCE

X..X

.XX +++

---

DIMENSIONAL TOLERANCES

D

C

B

A

8

8 7 6 5 4 3 2 1

D

C

A

1234567

FINISH

DRAWN BY

CHECKED BYVACUUM

SHEET

0.0600.0300.015

0.5

DRAWING/PART NUMBER

UPTON, N.Y. 11973BROOKHAVEN SCIENCE ASSOCIATES

BROOKHAVEN NATIONAL LABORATORY

REVISION

OF

INTERPRET DRAWING AS PER ANSI Y14.5-1994 OR Y32.2-1975

DIMENSIONS IN BRACKETS [X.XX] (WHERE PRESENT)

ALL DIMENSIONS ARE IN INCHESUNLESS OTHERWISE SPECIFIED

ESH&QRISK LEVELWBS#

REV. ZONE CKR. APP.DESCRIPTION BY DATE

APPROVALENGINEERAPPROVAL

SUPERVISORAPPROVAL

ES&H APPROVAL

QA APPROVAL

Exploring Life's Mysteries,Protecting its FutureARE MILLIMETERS AND ARE FOR REFERENCE ONLY

+-

.XXX +- 0.005SHEET SIZE

DBREAK EDGES & SHARP CORNERS 0.005 MIN. TO 0.030 MAX

SCALETHIRD ANGLEPROJECTION

NEXT ASSY:

PROJECT

NA

390

R1

R2

390

R3

390

R4

390

R5

390

R6

390

CH

GN

D

1

ACREVISED PER ECN LT-ECN-016-1515B SEJ

AC

3 3 3

A

10/27/2015

10/30/2015

INITIAL RELEASE

6/10/2016 JM

Page 14: Document Description Documents Files Comments - bnl.gov · PDF fileSpecific logic diagram for all ID Front Ends ... Rack Interconnection Wiring ... PLC program in the Electrical Design

o0.5ANGULAR TOLERANCE

+

+

-

-

+-

.XXX.XX

.X

-+

DECIMAL TOLERANCES

INTEGER TOLERANCES

MIN .005MAX .03

125

WBS # 1.3.6.2

DATE

JOB NUMBER

REV

UNLESS OTHERWISE SPECIFIED

4 3

A

B

C

D

4 3 2 1

D

C

B

A

12

FINISH

BREAK SHARPCORNERS AND EDGES

UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHESDIMENSIONS IN [*.**] ARE

MILLIMETERS EQUIV. FOR REF. ONLY

INTERPRET DRAWING AS PER

ANSI Y14.5 OR Y32.2

DRWN BY

REV

SHEETSCALE: N/A 1 0F

DRAWING NUMBER

DESCRIPTION BYDATE CHECKED APP

LT-EL-SR-PS

.06

.030

.015

.010

RISK LEVELESH&Q

A-2

ECN'S

OUTSTANDING

UNSPECIFIED RADII .02 MAX

56

6 5

E

CHK BY

ENG APP

SUPV APP

QA APP

ESH APP

DRAWING DIRECTORY

USED ON DWG. NO.

-+

LT-EL-SR-PS-RAK-1185-91

C.GUARINO 2/15/14

A INITIAL RELEASE CG

J.MALLEY

A.CASTIBLANCO

G.GANETIS

E.CHESWICK

R.LEE

WIRING DIAGRAM

PENTANT 5 CELL 18

RACK GROUP E4 EPS CHASSIS

2

LT-E

L-S

R-P

S-R

AK

-11

85-9

1

2/15/14 JM AC

2/18/14

2/18/14

2/21/14

2/19/14

2/20/14

1 2 6 5

BL

KW

HT

RE

D

GR

N

1 2 6 5

BM

GV

1

1 2 6 5

BL

KW

HT

RE

D

GR

N

BL

KW

HT

RE

D

GR

N

TU

NN

EL

TU

NN

EL

TU

NN

EL

BM

GV

2

BM

GV

3

1 2 3 4 5 6 7 8 9 10

11

121 2 3 4 5 6

WH

T

BL

K0

0A

2 0

B

17

34-O

W4

SR

:C1

7-E

PS

-42

09-

BM

17_G

V1

_F

E-M

C1

8-R

GE

-4

SR

:C1

7-E

PS

-42

08-

BM

17_G

V3_

FE

-MC

18-

RG

E-4

10

0 m

A+

BREVISED PER ECN LT-ECN-016-1491MOVED SHEET 1 TO SHEET 2 AND ADDED NEW SHEET 1

SEJ10/14/2015 JM AC

C REVISED PER ECN LT-ECN-016-1516 SEJ6/09/2016 JM AC

A1

A2

Rela

y1

1

14

1 9 2 10

BL

K

WH

T

RE

D

GR

N

A1

A2

Rela

y1

1

14

FE

VA

C P

LC

FE

EP

S

CO

NN

EC

TO

R

D REVISED PER ECN LT-ECN-017-1642 SEJ10/10/2016 JM AC

E REVISED PER ECN LT-ECN-017-1853 SEJ9/21/2017 JM AC

SR

:C1

8-E

PS

-41

34-

ID1

8_

GV

1_

FE

-MC

18-R

GE

-4

SR

:C1

8-E

PS

-41

33-

ID1

8_F

V_F

E-M

C1

8-R

GE

-4

SR

:C1

8-E

PS

-41

36-

ID1

8_G

V2

_F

E-M

C1

8-R

GE

-4

+1

00

mA

Page 15: Document Description Documents Files Comments - bnl.gov · PDF fileSpecific logic diagram for all ID Front Ends ... Rack Interconnection Wiring ... PLC program in the Electrical Design

REV

SHEET OF 2

DRAWING NUMBERDRAWING DIRECTORY

COMPUTER REPRODUCABLE

REV

4 3

A

B

C

D

4 3 2 1

D

C

B

A

12

SCALE: N/A 2

DESCRIPTION BYDATE CHECKED APP

LT-EL-SR-PS

5

6 5

ELT-EL-SR-PS-RAK-1185-91

LT-E

L-S

R-P

S-R

AK

-11

85-9

1

FLOW METERS J. BOX FLOW METERS J. BOX

*** These cables ends must be isolated

with shrink tubing and tie wrapped to the

panel.

A2

A1

1 2 3 4 5 6 7 8

SEE SHEET 1