MARWADI EDUCATION FOUNDATION’S GROUP OF INSTITUTIONS (MEFGI) Department of Electronics and Communication Engineering

Digital logic design Question bank

Chapter-1 Binary System No Question Marks Year Book

1 Convert the following numbers to decimal (i) (10001.101) 2 (ii) (101011.11101) 2 (iii) (0.365) 8 (iv) A3E5 (v) CDA4 (vi) (11101.001) 2 (vii) B2D4

7 9-Dec

2 Perform the operation of subtractions with the following binary numbers using 2′ complement (i) 10010 - 10011 (ii) 100 -110000 (iii) 11010 -10000

7 9-Dec

3 Define : Integrated Circuit and briefly explain SSI, MSI, LSI and VLSI 7 Mar-10

4 Define: Digital System. Convert following Hexadecimal Number to Decimal : B28, FFF, F28 Convert following Octal Number to Hexadecimal and Binary: 414, 574, 725.25

7 Mar-10

5

Convert the following Numbers as directed: (1) (52)10 = ( ) 2 (2) (101001011)2 = ( ) 10 (3) (11101110) 2 = ( ) 8 (4) (68)10 = ( )16

7 Dec-10

6 Convert decimal 225.225 to binary ,octal and hexadecimal 3 6

11-May 11-Dec

7 Convert decimal 8620 into BCD , excess-3 code and Gray code. 3 11-May

8 Represent the decimal number 8620 in BCD , Excess-3 , and Gray code 3 11-Dec

9 Convert the Decimal Number 250.5 to base 3, base 4, base 7 & base 16. 4 12-May

Chapter- 2 Boolean algebra and Logic Gates No Question Marks Year Book

1 Demonstrate by means of truth tables the validity of the following theorems of Boolean algebra (i) De Morgan’s theorems for three variables (ii) The Distributive law of + over -

7 Dec-09

2 Draw the logic symbol and construct the truth table for each of the following gates. [1] Two input NAND gate [2] Three input OR gate [3] Three input EX-NOR gate [4] NOT gate

7 Mar-10

3 Give classification of Logic Families and compare CMOS and TTL families 7 Mar-10

4 Explain SOP and POS expression using suitable examples 7 Mar-10

5 Draw symbol and construct the truth table for three inputs Ex-OR gate. 2 May-11

6 What is the principle of Duality Theorem? 2 May-11

7 Explain briefly: standard SOP and POS forms. 2 May-11

8 What are Minterms and Maxterms? 2 May-11

9 Define: Noise margin , Propagation delay 2 May-11

10 Explain briefly : SOP & POS , minterm & maxterm , canonical form , propagation delay, fan out

5 11-Dec

11 Given Boolean function F= x y + x′ y′ + y′ z 1. Implement it with only OR & NOT gates 2. Implement it with only AND & NOT gates

5 12-May

12 Express following Function in Product of Maxterms F(x,y,z)= ( xy + z ) ( y + xz ) 3 12-May

Chapter- 3 Simplification of Boolean Functions No Question Marks Year Book

1 Obtain the simplified expressions in sum of products for the following Boolean functions: (i) F(A,B,C,D,E) =Σ(0,1,4,5,16,17,21,25,29) (ii) A′B′CE′ + A′B′C′D′ +B′D′E′ + B′C D′

7 Dec-09

2 Reduce the expression: (1) A+B(AC+(B+C’)D) (2) (A+(BC)’)’(AB’+ABC)

7 Dec-10

3 Simplify the Boolean function: (1) F = A’B’C’+B’CD’+A’BCD’+AB’C’ (2) F =A’B’D’+A’CD+A’BC d=A’BC’D+ACD+AB’D’ Where “d ” indicates Don’t care conditions.

7 Dec-10

4 Simplify the Boolean function: (1)F(w,x,y,z) = Σ (0,1,2,4,5,6,8,9,12,13,14) (2)F(w,x,y) = Σ (0,1,3,4,5,7)

7 Dec-10

5 Simplify the following Boolean function by using Tabulation method. F = Σ (0,1,2,8,10,11,14,15 )

8 11-Dec

6 Simplify the following Boolean function using K-map F( w,x,y,z) = Σ( 1 , 3 , 7 , 11 , 15 ), with don’t care conditions d(w,x,y,z) = Σ( 0, 2 ,5 )

4 May-11

7 Simplify the following Boolean function using tabulation Method and draw logic diagram using NOR gates only F(w,x,y,z ) = Σ( 0 ,1 , 2 , 8 ,10 ,11,14,15 )

7 May-11

8 Determine the Prime Implicants of following Boolean Function using Tabulation Method. F(A,B,C,D,E,F,G)=Σ(20,28,38,39,52,60,102,103,127)

7 12-May

9 Simplify the following Boolean function using K-Map. F=A′B′C′+B′CD′+A′BCD′+AB′C′

4 12-May

Chapter- 4 Combinational Logic No Question Marks Year Book

1 Design a combinational circuit that accepts a three bit binary number and generates an output binary number equal to the square of the input number.

7 Dec-09

2 With necessary sketch explain full adder in detail 7 Dec-09

3 Design a 4 bit binary to BCD code converter 7 Mar-10

4 Design a combinational circuit that generates the 9′ complement of a BCD digit 7 Dec-09

5 Design a full-adder with two half-adders and an OR gate 7 May-11

6 Implement Boolean expression for Ex-OR gate using NAND gates only 4 May-11

7 Draw symbol and truth table for four input EX-OR gate. Explain NAND and NOR as an universal gate

6 11-Dec

8 Simplify Boolean function F ( w,x,y,z ) = Σ ( 0,1,2,4,5,6,8,9,12,13,14 ) using K-map and Implement it using (i) NAND gates only (ii) NOR gates only

8 11-Dec

9 Design the Combinational Circuits for Binary to Gray Code Conversion. 5 12-May

10 Explain Design Procedure for Combinational Circuit & Difference between Combinational Circuit & Sequential Circuit.

4 12-May

11 Explain with figures how NAND gate and NOR gate can be used as Universal gate.

7 4

Dec-10 May-11

12 Implement the following Boolean functions (i) F= A (B +CD) +BC′ with NOR gates (ii) F= (A + B′) (CD + E) with NAND gates

7 Dec-09

13 Design a BCD to decimal decoder 7 May-11

14 Design a combinational circuit whose input is four bit binary number and output is the 2’s complement of the input binary number.

7 8

May-11 11-Dec

15 Design BCD to Excess-3 code converter using minimum number of NAND gates 8 11-Dec

Chapter- 5 Combinational Logic With MSI AND LSI No Question Marks Year Book

1 Discuss 4-bit magnitude comparator in detail

7 7

Dec-09 12-May

2 Design a full adder circuit using decoder and multiplexer 7 Mar-10

3 write short note on EEPROM,EPROM and PROM 7 Mar-10

4 Define: [1] Comparator [2] Encoder [3] Decoder [4] Multiplexer [5] De-multiplexer [6] Flip Flop [7] PLA

7 Mar-10

5 What is multiplexer? Implement the following function with a multiplexer: F(A,B,C,D) = Σ(0 , 1 , 3 , 4 , 8 , 9 ,15 )

7 May-11

6 Write short note on : Read Only Memory (ROM) 7 May-11

7 A combinational circuit is defined by functions: F1(A,B,C) = Σ( 3 , 5 , 6, 7 ) ,F2(A,B,C) = Σ( 0 , 2 , 4, 7 ) Implement the circuit with PLA having three inputs ,four product term and two outputs

7 May-11

8 What is meant by multiplexer? Explain with diagram and truth table the Operation of 4-to-1 line multiplexer

7 7

11-Dec 10-Dec

9 What is meant by decoder? Explain 3-to-8 line decoder with diagram and truth table

7 7

11-Dec 10-Dec

10 Construct 4*16 Decoder with help of 2*4 Decoder. 5 12-May

11 Discuss 4 bit BCD Adder in Detain. 5 12-May

12 Design a combination circuits for a full adder. 4 12-May

Chapter- 6 Sequential Logic No Question Marks Year Book

1 Discuss D-type edge- triggered flip-flop in detail 7 Dec-09

2 (i)With neat sketch explain the operation of clocked RS flip (ii)Show the logic diagram of clocked D

7 Dec-09

3 With logic diagram and truth table explain the working JK Flipflop. Also obtain its characteristic equation. How JK flip-flop is the refinement of RS flip-flop?

7 Dec-10

4 Draw and explain the working of following flip-flops [1] Clocked RS [2] JK 7 Mar-10

5 Convert SR flip-flop into JK flip-flop 7 Mar-10

6 Draw logic diagram , graphical symbol , and Characteristic table for clocked D flip-flop

3 May-11

7 What is race-around condition in JK flip-flop? 2 May-11

8 Explain working of master-slave JK flip-flop with necessary logic diagram , state equation and state diagram

7 May-11

9 Explain the working of the Master Slave J K flip-flop 6 11-Dec

10 Explain the procedure followed to analyze a clocked sequential circuit With suitable example

10 11-Dec

11 Explain Master Slave Flip Flop through J.K Flip Flop 4 12-May

12 Give comparison between combinational and Sequential logic circuits 2 May-11

13 Design a counter with the following binary sequence:0,4,2,1,6 and repeat (Use JK flip-flop)

7 7

Dec-09 10-Dec

14 Design a counter with the following binary sequence:0,1,3,7,6,4, and repeat.(Use T flip-flop)

7 Dec-09

15 Design sequential counter as shown in the state diagram using JK flip-flops 7 Mar-10

16 Design Sequential Circuit with J.K. Flip Flops to satisfy the following state equation. A( t + 1 ) =A′ B′ CD + A′ B′ C + ACD +AC′ D′ B(t+1)= A′ C + CD′ + A′ BC′ C(t + 1) = B

7 12-May

D(t +1)=D′

Chapter- 7 Registers Transfer Logic & Micro-Operation No Question Marks Year Book

1 Discuss Interregister Transfer in detail 7 Dec-09

2 With respect to Register Transfer logic, explain Inter-register Transfer with necessary diagrams.

7 Dec-10

3 Prepare a detailed note on: Instruction Codes. 7 Dec-10

4 State and explain the features of register transfer logic 7 Mar-10

5 Explain briefly: (i) logic and shift micro-operations (ii) fixed-point binary data and floating-point data

7 May-11

6 Define : state table , state equation , state diagram , input & output equations 4 11-Dec

7 Define the different mode of operation of registers & explain any two in details. 7 12-May

8 Explain Macro operations Versus micro operations 3 12-May

Chapter- 8 Registers, Counters and the Memory unit No Question Marks Year Book

1 Draw the state diagram of BCD ripple counter, develop it’s logic diagram, and explain it’s operation.

7 Dec-09

2 Construct a Johnson counter with Ten timing signals. 7 Dec-10

3 What is the function of shift register? With the help of simple diagram explain its working. With block diagram and timing diagram explain the serial transfer of information from register A to register B.

7 Dec-10

4 With logic diagram explain the operation of 4 bit binary ripple counter. Explain the count sequence, How up counter can be converted into down counter?

7 Dec-10

5 Explain the working of 4 bit asynchronous counter 7 Mar-10

6 Explain memory unit 7 Mar-10

7 Give classification of counters and explain asynchronous 4-bit binary ripple counter

7 May-11

8 Explain working of 4-bit binary ripple counter

7 7

11-Dec 12-May

9 Draw and explain block diagram of 4-bit bidirectional shift register with Parallel load

7 7

11-Dec 09-Dec

10 How many flip flops are required to build a shift register to store following numbers. i) Decimal 28 ii) Binary 6 bits iii) Octal 17 iv)Hexadecimals A

4 12-May

11 Explain 4-bit up-down binary synchronous counter. 7 12-May

12 Explain Johnson Counters. 7 12-May

Chapter- 9 Processor Logic Design No Question Marks Year Book

1 What is scratchpad memory? With diagram explain the working of a processor unit employing a scratchpad memory.

7 Dec-10

2 Draw the block diagram of a processor unit with control variables and explain its operation briefly.

7 Dec-10

3 Explain the design of Arithmetic Logic Unit 7 Mar-10

8 Dec-11 4 Draw block diagram of a 4-bit arithmetic logic unit. Design an adder / 5subtractor

circuit with one selection variable S and two inputs A and B .when S = 0 circuit performs A+B, when S = 1 circuit performs A – B by taking the 2’s complement of B

7 May-11

5 Explain Arithmetic micro operations 6 11-Dec

6 Explain Arithmetic addition and arithmetic subtraction. 4 12-May

7 Briefly explain processor unit with a 2-port memory 3 12-May

8 Explain common cathode types seven segments displays. 3 12-May

Chapter- 10 Control Logic Design No Question Marks Year Book

1 With simple diagram explain the working of control logic with sequence register and decoder.

7 Dec-10

2 Briefly explain control organization. With diagram explain control logic with one flip-flop per state.

7 Dec-10

3 Explain Control Logic Design 7 Mar-10

4 Draw and explain block diagram of microprograme control. 7 May-11

5 What is the difference between hardwired control and micro program control? Write advantages and disadvantages of each method

6 11-Dec

6 Write the Comparisons between Hard wired control and micro programmed Controls.

3 12-May

Distribution:

Chapter Dec-09 Mar-10 Dec-10 May-11 Dec-11 May-12 Total Rank

Ch- 1

Ch- 2

Ch- 3

Ch- 4

Ch- 5

Ch- 6

Ch- 7

Ch- 8

Ch- 9

Ch- 10

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