Dld Klu Manual
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Transcript of Dld Klu Manual
8/6/2019 Dld Klu Manual
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Digital Logic Design Lab Dept. of ECE
KL University, Guntur
1. Realization of gates using Universal gates
Implementation using NAND gate:
(a) NOT gate: = ′
(b) AND gate: = ∙
(c) OR gate: = +
(d) NOR gate: = ( + )′
(e) Ex-OR gate: = ⊕
A Y
0 1
1 0
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
A B Y0 0 0
0 1 1
1 0 1
1 1 0
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Digital Logic Design Lab Dept. of ECE
KL University, Guntur
Implementation using NOR gate:
(a) NOT gate: = ′
(b) AND gate: = ∙
(c) OR gate: = +
(d) NAND gate: = ()′
(e) Ex-NOR gate: = ⊙ = ( ⊕ )′
A Y
0 1
1 0
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
A B Y0 0 1
0 1 1
1 0 1
1 1 0
A B Y
0 0 10 1 0
1 0 0
1 1 1
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Digital Logic Design Lab Dept. of ECE
KL University, Guntur
2. Combinational Logic Circuits
Half-Adder:
Half-Adder is a Combinational Logic Circuit used to perform arithmetic addition of two bits
and produces two outputs, Sum & Carry.
= + = ⊕
=
Truth table
Half-Adder using NAND gates
Full-Adder:
Full-Adder is a Combinational Logic Circuit used to perform arithmetic addition of three bits
and produces two outputs, Sum & Carry.
= + + + = ⊕ Y ⊕ Z
= + ( ⊕ Y)
Truth table
X Y S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
X Y Z S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 01 0 1 0 1
1 1 0 0 1
1 1 1 1 1
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Digital Logic Design Lab Dept. of ECE
KL University, Guntur
Full-Adder using NAND gates
Half-Subtractor:
Half-Subtractor is a Combinational Logic Circuit used to perform subtraction of two bits and
produces two outputs, Difference & Borrow
= + = ⊕
= ′
Truth table
Half-Subtractor using NAND gates
X Y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
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Digital Logic Design Lab Dept. of ECE
KL University, Guntur
3. Code Converters
(a) Binary to Gray Code Converter:
4 bit Binary to Gray code converter is a logic circuit which converts 4 bit Binary code to
corresponding Gray code.
=
= ⊕ B
= ⊕ B
= ⊕ B
Truth table
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
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Digital Logic Design Lab Dept. of ECE
KL University, Guntur
(b) Gray to Binary Code Converter:
4 bit Gray to Binary code converter is a logic circuit which converts 4 bit Gray code tocorresponding Binary code.
=
= ⊕ G
= ⊕ G ⊕ G
= ⊕ G ⊕ G ⊕ G
Truth table
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 10 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 01 0 0 0 1 1 1 1
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Digital Logic Design Lab Dept. of ECE
KL University, Guntur
4. Comparator
Magnitude Comparator is a logic circuit to compare the magnitude of two numbers and
contains three outputs, (A>B), (A=B) and (A<B) depending on the magnitude.
(a) One Bit Magnitude Comparator:
( > ) = ′
( = ) = +
( < ) = ′
(b) 4 Bit Magnitude Comparator using 7485:
The 7485 is a high speed, expandable 4-bit magnitude comparator which compares
two 4-bit words and generates three outputs: (A>B), (A=B) and (A<B). Three
cascading inputs allow serial expansion over any word length without external gates.
=
=
For 4-bit comparison, the cascading inputs
( > ) = 0
( = ) = 1
( < ) = 0
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Digital Logic Design Lab Dept. of ECE
KL University, Guntur
Function Table of 7485:
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Digital Logic Design Lab Dept. of ECE
KL University, Guntur
5. Multiplexer and Demultiplexer
Multiplexer:
A multiplexer is a combinational circuit that selects binary information from one of many
input lines and directs it to a single output line. The selection of a particular input line is
controlled by a set of selection lines. In general, there are 2n
input lines and n selection lines
whose bit combinations determine which input is selected.
× Multiplexer:
There are 4 input lines , , , and 2 select inputs and .
0 0
0 1
1 0
1 1
=
+ +
+
4x1 Multiplexer
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Digital Logic Design Lab Dept. of ECE
KL University, Guntur
Demultiplexer:
A demultiplexer is a circuit that receives information on a single line and transmits this
information on one of 2n
possible output lines. The selection of a specific output line is
controlled by the bit values of n selection lines.
× :
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1
=
, = , =
, =
1x4 Demultiplexer