Digital Logic LAB Manual KL-300 [Shorted]

DIGITAL WGIC LAB

KL-300

EXPERIMENT MANUAL

~1-:" ~~l .. a · K&H MFG CO., LTD. ~ / _!";-;.~ 5F, No.8, Sec. 4 Tzu-Chiang Rd., San Chung City 241, Taipei Hsien, Taiwan R.O.C. (il V -~~~ TEL : 886-2-2286-0700 FAX : 886-2-2287-3066 ''f.-,.,,1# sr.$ ~~

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KL-300 DIGITAL LOGIC LAB

EXPERIMENT MANUAL

CONTENTS

CHAPTER 1 BASIC LOGIC GATE EXPERIMENTS

1-1 Introduction to Logics and Switches .... ................ ... ........ .... ........ .. 1-2

1-2 Logic Gates Circuits...... .. ... ...... ..... ........... . .. ... .. ... .... .... . ....... .... . .. .. 1-10 a. Diode Logic (DL) Circuit

b. Resistor-Transistor Logic (RTL) Circuit

c. Diode-Transistor Logic (DTL) Circuit

d. Transistor-Transistor Logic (TTL) Circuit

e. Complementary-Metal-Oxide-Semiconductor (CMOS) Circuit

1-3 Threshold Voltage Measurement . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .. .. . 1-29 a. TTL Threshold Voltage Measurement

b. CMOS Threshold Voltage Measurement

1-4 Voltagi/C~frerit Measurement.... .. .. .. ...... ...... ... ...... .. . .. .... . ...... ...... .. .. 1-31 a. Ttl.:: II~ \!Q!~ge and Current Measurement

b. CMP$\ldtt~ge and Current Measurement

1-5 Basic Logic Gate Transmission Delay Measurement ... . ............. ....... .. . 1-36 a. TTL Gate Delay Time Measurement

b. CMOS Gate Delay Time Measurement

1-6 Measurements of Basic Logic Gates Characteristics ............. . .. .. .... .... . 1-43 a. AND Gate Characteristics Measurement

b. OR Gate Characteristics Measurement

c. INVERTER Gate Characteristics Measurement

d . NAND Gate Characteristics Measurement

e . NOR Gate Characteristics Measurement

f. XOR Gate Characteristics Measurement

I KL300-E061 229-EC

CONTENTS

1-7 Interface Between Logic Gates ......................................................... 1-55

a. TTL to CMOS Interface

b. CMOS to TTL Interface

CHAPTER 2 COMBINATIONAL LOGIC CIRCUIT$ EXPERIMENTS

2-1 NOR Gate Circuit .... . .. ...... ......... ... .... . ..... . .... .... .. .. .. .. .. . .... .. .... .. . .. .. 2-3

2-2 NAND Gate CircJ.dt:·...... ... .. .. ...... .. . .. .... .. .. .. .. .. . ... .... .. .... ... .. .. .. .. .... .. .. 2-8

::,. __ ,:::::::;:::;::::::::::::::::::;::::::::::::::::::::::::··_,:=::

2-3 XOR Gate eiflcoit . ~;}. .. . .. . . . ... . .. . . . . .. . . . . ... . . . . . . .. ... . . . . .. . .. . . . ... . . . . .. . . . . .. . . 2-13

a, Con~tryctrng )(OR Gate with NAND Gate

b . ...... C<?Q~trvGtirig . XOR Gate with Basic Gate

2-4 AND-OR-INVERTER (A-0-1) Gate Circuit.. .......... .............................. 2-19

2-5 Comparator Circuit ...................................................... ;.. ·;;-"~ 2-24

a. Comparator Constructed with Basic Logic Gates ~--· '.::::

b. Comparator Constructed with TTL IC

2-6 Schmitt Gate Circuit..................................................................... 2-31

2-7 Open-Collector Gate Circuit............. ... ....... .. ... ... ....... ........... ........... 2-34

2-8

a. High Voltage/Curr~6t<:;!r9uit b. Constructing ~oANm~lte with Open-Collector Gate

Trismre Gate«r.g:; ............................................................ . a. Truth Table rJi~~'surements

2-41

b. Constructing an AND Gate with Tristate Gate

c. Bidirectional Transmission Circuit

2-9 Half-Adder and Full-Adder Circuit........... ........................................ 2-50

a. Constructing HA with Basic Logic Gates

b. Full-Adder Circuit with IC

c. High-Speed Adder Carry Generator Circuit

d. BCD Code Adder Circuit

2-10 Half-Subtractor and Fuii-Subtractor Circuit..................................... 2-65

a. Subtracter Circuit Con~.~r~Gt~d wJth~.Basib Logic Gates

b. Full-Adder and lnverter~itcuit

II KL300-E061229-EC


1-6 Measurements of Basic Logic Gates Characteristics

OBJECTIVE

Understanding the symbols and characteristics ofvahous basic logic gates.

DISCUSSIONS

The input and output characteristics of basic logic gates are defined below :

VoH - High output voltage loH - High output current

VoL - Low output voltage loL - Low output current

VIH'" rJig.!l.input voltage I1H - High input current

V1L - Low input voltage ilL - Low input current

Characteristics of TTL gates are different from those of CMOS gates, The load and

current-limiting resistors they are connected to are different as well. For example, in

the case of an OR gate and an AND gate:

1. OR gate: input of TTL are connected to a 1 K resistor while input of CMOS gates

are connected to a 1 OK 0 resistor.

TIL with 1 KO resistor at the input

CMOS with 1 OKO resistor at the input

Resistance for the LS series TIL is approximately 5K 0. If the X input

of a TTL OR gate is grounded then the output F is equal to the input A

(F=A}, making expansion control impossible.

If the resistor is grounded and there is no signal at .. X , then X is

equivalent to being grounded and F=A. If necessary a signal could be

added to X so that F=A x X. The output can be controlled by X.

'"'

2. AND gate: TTL AND gates .are in high state when it is open or when a resistor is

connected to toe supply voltage. CMOS AND gates are in high state

when a resistor of. at least 1 OK 0 is connected to the supply voltage.

1-43

KL-300 DIGITAL LOGIC LAB EXPERIMENT MANUAL

+15V +15V

:~·?=~·?~~· "HIGH" TTL AND gate

+15V +15V

F

"HIGH" CMOS AND gate

The "Truth Table" is a table that shows a logic gate's corresponding inputs and

outputs under ideal conditions.

1. OR gate

STATE INPUT OUTPUT

A 8 F

0 0 0 0 When A=O, 8=0 the output F=O

1 0 ~ 1 When A=O, 8=1 the output F=1

2 1 0 1 When A=1 , B=O the output F=1

3 1 1 1 When A=1 , 8=1 the output F=1

In Boolean expression, F=A B+AB+AB=A+B

1-44

2.

3.


AND gate

STATE INPUT OUTPUT

A B F

0 0 0 0 When A=O, B=O the output F=O

1 0 1 0 When A=O, B=1 the output F=O

2 1 0 0 When A=1 , B=O the output F=O

3 1 1 1 When A=1 , B=1 the output F=1

In Boolean expression, F=AB

INVERTER gate

STATE INPUT OUTPUT

A F

0 0 1

1 1 0

When A=O, the output F=1

When A=1 , the output F=O

In Boolean expression, F= A

4. XORgate

STATE INPUT OUTPUT

A B F

0 0 0 0

1 0 1 1

2 1 0 1

3 1 1 0

When A=B, the output F=O

When A =F B, the output F=1

In Boolean expressipn, F= AB + AB = A Ef> B

1-45


5. NAND gate

The output of a NAND gate is the exact opposite of an AND gate.

STATE INPUT OUTPUT

A B F

0 0 0 1 When A=O, B=O the output F=1

1 0 1 1 When A=O, B=1 the output F=1

2 1 0 1 When A=1, B=O the output F=1

3 1 1 0 When A=1 , B=1 the output F=O

In Boolean expression, F=AB

6. NOR gate

The output of a NOR gate is the exact opposite of an OR gate.

STATE INPUT OUTPUT

A B F

0 0 0 1 When A=O, B=O the output F=1

1 0 1 0 When A=O, B=1 the output F=O

2 1 0 0 When A=1, B=O the output F=O

3 /'1 1 0 When A=1, B=1 the output F=O

In Boolean expression, F= A+ B =AxB

These truth tables are based on "positive" logic where positive voltage represents i'1"

and negative voltage represents "0". In case negative logic is used the output will be

reversed.

1-46


Compare the truth tables for a positive and a negative OR gate shown below:

STATE INPUT OUTPUT STATE INPUT OUTPUT

A 8 F A 8 F

0 0 0 0 0 1 1 1

1 0 1 1 1 1 0 0

2 1 0 1 2 0 1 0

3 1 1 1 3 0 0 0

Observe the truth table for a negative logic OR gate. It to equivalent to a positive

logic AND gate.

EQUIPMENTS REQUIRED

KL-31 001 Digital Logic Lab; Module KL-33001 ; Oscilloscope

PROCEDURES

(a) AND Gate Characteristics Measurement (Module KL-33001 block d)

1. Insert connection clips according to Fig. 1-6. U1a and U1b will be used in

this section.

2. Connect inputs A1 , A2 to Data Switch SWO, SW1 TTL level and output F3 to

Logic Indicator LO. Follow the input sequences below and record the

outputs.

STATE INPUT OUTPUT

A2 A1 F3

0 0 0

1 0 1

2 1 0

3 1 1

1-47


3. Connect A4 to the 10Hz TTL level output of Clock Generator. Measure and

record the input and output waveforms.

CD A3=0 @ A3=1 ® A3=1 Hz

MLLAL

Fig. 1-6 STATE

(b) OR Gate Characteristics Measurement (Module KL-33001 block d)

1. U2a and U2b of Module KL-33001 block d will be used in this section.

2. Connect inputs A3, A4 to SWO, SW1 TTL level and output F4 to L 1. Follow

the input sequences below and record output F.

STATE INPUT OUTPUT

0

1

2

3

A4 A3 F4

0

0

1

1

1-48

0

1

0

1

A1

A2


F3=A1~ A2~

A3~A3~ A4o----/..__/l-/_ ~ A4~~

3. Connect A4 to the 1OHz TTL level output of Clock Generator. Measure and

record the input and output waveforms.

Q) A3=0 ~ A3=1 ® A3=1Hz

(c) INVERTER Gate Characteristics Measurement (Module KL-33001 block d)

1. U3c of Module KL-33001 block d will be used in this section.

2. Connect input C 1 and output F6 of U3c to SWO and L 1 (LED) respectively.

Follow the input sequences below and record outputs.

C1 F6

0 0

1 1

3. Connect F6 to C2 with a test lead. Connect output F? to L2(LED). Follow the

input sequences below and record the outputs.

C2 F?

0 0

1 1

1-49


(d) NAND Gate Characteristics Measurement

(Module KL-33001 block d)

1. U1 a of Module KL-33001 block d will be us~d if) this section. Connect inputs

A 1, A2 to SWO, SW1 TTL level and output F1 to L 1 (LED). Follow the input

sequences below and record the outpyt~,

0

1

2

3

A2

0

0

1

1

A1

0

1

0

1

F1

2. Connect 1OHz TTL level square wave to A2, measure and record

input/output waveforms at the following conditions.

CD A1=0 @ A1=1 @ A1=1Hz

(e) NOR Gate Characteristics Measurement (KL-33001 block d)

1. U2a of Module KL-33001 block d will be used in this section. Connect inputs

A3, A4 to SWO, SW1 TTL level and output F2 to L 1 (LED) ~.ollow tli~ input

sequences below and record the outputs.

A4 A3 F2

0 0 0

1 0 1 · ...

2 1 0

3 ::::·:····

1 1

1-50


2. Connect TTL level 1OHz square wave to A4, observe and record inpuUoutput

waveforms under the following conditions with an oscilloscope:

<D A3=0 @ A3=1 @ A3=1Hz

(f) XOR Gate Characteristics Measurement (Module KL-33001 block d)

1. U4a of Module KL-33001 block d will be used in this section. Connect inputs

C4, C5 to SWO, SW1 TTL level and output F9 to L 1 (LED). Follow the input

sequences below and record the outputs.

0

1

2

3

C5

0

0

1

1

C4

0

1

0

1

F9

2. Connect TTL level 1OHz square wave to C4, observe and record inpuU

output waveforms under the following conditions with an oscilloscope.

<D C5=1 @ C5=0 @ C5=1Hz

1-51


RESULTS

1. Phase relationship between input and output waveforms should be compared

when square waves are added.

FAULT SIMULATIONS

Utilizing U1 , U2, U5, U6

1. The high state voltage F1 should be approximately 4.4V when there are no loads.

Measure U1 a. Connect inputs A 1, A2 and measure F1 again. Determine possible

faults.

2. Input states of A 1. A2, 81 . Connect F3 to L 1 and the output remains "1".

Determine possible faults.

3. Input states of A3. A4, 82. Connect F4 to L2 and the output remains "0".

Determine possible faults.

EXERCISE

1. Construct the circuit shown below and measure waveforms at A, 8, C. Try

adjusting the input frequency at A so that the output frequency at C is twice the

input frequency. What's the input frequency range?

2. Refer to Fig. (1) aod (2) below. Are they identical? Determine truth tables for both

circuits.

: :=JL>--o F (1)

II

:~F(2)

1-52


MULTIPLE CHOICE QUESTIONS

( ) 1. Fig. (a) is a

1. AND gate.

2. OR gate

3. NOT gate

) 2. What logic function does the circle at the output of Fig. (c) represent?

1. NOT gate

2.AND gate

3. OR gate

) 3. The corresponding input/output values of a logic gate is called :

1. Trigger table

2. Truth table

3. Specification table

( ) 4. Fig. (c) is a

1. AND gate.

2. NOR gate

3 . NAND gate

) 5. Which figure represents an OR gate?

1. Figure (a)

2. Figure (b)

3. Figure (c)

( )6. Fig. (d) is a

1. NOT gate.

2. BUFFER

3 . NAND gate

( ) 7. In Fig. (e) , F represents:

1. A+B

2.AB

3. A EB B

1-53


( ) 8. In Fig. (b), if B is to represent "0" when the circuit is open, a resistor should be

connected from B to:

1. Ground

2. Supply voltage

3. A

) 9. Fig. (d) is a

1. NOT gate.

2. NAND gate

3. AND gate

) 10. If A=O for the circuit of Fig. (a) then the output F is:

1. 0

2. 1

3. B

(a)

(b)

::crF (c:)

(d)

(e)

(f)

1-54


1-7 Interface between Logic Gates

OBJECTIVE

Understanding the techniques of interface connections.

DISCUSSIONS

TTL and CMOS are the most often-used logic gates. Their specifications are shown

below in Fig. 1M7 (a) and Table 1-7 .

. ii ········ . }i TIL COMS

·~ SUPPLY VOL TAG + 5V±0.25V 3- 18V

LOW INPUT VOLTAGE Vii <::::0.8V <... 1.5V

TTL CMOS

HIGH INPUT VOLTAGE Vih ~2.0V ~3 .5V

LOW OUTPUT VOLTAGE Vol .<:::: 0.4V OV

HIGH OUTPUT VOLTAGE Voh ? 2.4V 5V

LOW INPUT CURRENT Iii ::s:; 1.6mA ~0. 11JA

HIGH INPUT CURENT lih ~401JA ~ 0.1mA 0.4V r----~·-"_?~.!..~_L __ _

OUTPUT

O LOGIC 0 -----------LL..L...L...L.-4 ft

LOW OUTPUT CURRENT lol :;> 16mA 2::. 1mA

HIGH OUTPUT CURRENT loh ~0.41JA > Q.1mA

.......

Table 1-7 Fig. 1-7 (a)

From Table 1-7 we can see that CMOS gate's input voltage requirement is higher than

TTL gate's output voltage capability.

If a TTL gate is used to drive a CMOS gate, TTL's output voltage must be increased to

meet the input voltage requirement of CMOS. On the other hand, when Cf\10S is used

to drive TTL the output current of CMOS must be increased. This is why we must

carefully review the data books before constructing any interface circuits.

A resistor Rx connected to the supply voltage can be added to increase the input

voltage into CMOS when it is driven by TIL, as shown in Fig. 1-7 (b). The range of Rx

is 390 0 "'4. 7K 0 for Standard series TIL and 820 0 ""'12K 0 for LS series TTL.

When TTL is driven by <#MOS a buffer should be added in between to increase the

output current of CMOS. Two standards CMOS connected in parallel could drive a LS

series TTL.

1-55


+V:SV

TTL CMOS

Fig. 1-7(b)

EQUIPMENTS REQUIRED

KL-31001 Digital Logic lab; Module KL-33001 ; Multimeter

PROCEDURES

(a) TTL to CMOS interface (Module KL-33001 block d/e)

1. Insert connection clips according to Fig. 1-7 (c). U1a is a Standard series

TTL gate which will be used in this section of the experiment.

2. Using the multimeter, adjust resistance of R14 to,2.2KO .

3. Connect output of F1 to input of USa.Use +SV supply voltage for both TTL

and CMOS gates. Connect input A 1 to TTL output of Data Switch SWO.

Measure and record voltages at A 1; F1 ; AS and Y1

A1 F1 AS Y1

0

1

4. Connect F1 to R13, Vee to R14 with connection clips. Again measure and

record A 1; F1; AS; Y1 below.

A1 F1 AS Y1

0

1

1-56


Fig. 1-7 (c)

(b) CMOS to TTL interface (Module KL-33001 block d/e)

1. U7a-U7c on block e of Module KL-33001 will be used in this section. Insert

connection clips according to Fig. 1-7 (c).

2. Connect output Y8 of U7a to input A1 of U1a and C8 to Data Switch SW1

TTL level output. Measure and record Y8; A 1; F1 .

C8 Y8 A1 F1

0

1

1-57


3. Connection clips inserted between C6 ----C7, C7 ----ca will connect C6 ----C7 ---

C8 in parallel. Repeat the measurements.

C8 Y8 A1 F1

0

1

4. Connect Y8 to input C1 , C2, C3 of U3a ----U3c. C1 "'C2----C3 as well as F6-

F7 - F8 are connected in parallel. Repeat the measurements.

C8 Y8 C1 F6

0

1

RESULTS

1. The theoretical high output voltage (Voh) of TTL is ~;4V, which is the minimum

allowable voltage. However in actual applications of TTL to CMOS interface, the

output voltage of TTL is close to +5V, enough to drive CMOS.

2. The addition of a resistor to the output of a TTL gate will increase its output

voltage, as well as its tolerance to noise interference.

3. When the output state of CMOS is "1 ", its minimal output voltage is roughly 4.4V.

On the other hand, the minimal input voltage requirement of TTL is about 2V so

there is 2.4V of noise interference immunity or tolerance.

4. Can a CMOS gate drive a standard TTL gate? How about a LS series TTL gate?

EXERCISE

1. Use CMOS NAND gate to construct the circuit of Figure (a) and measure Vo

when the LED is off and on. Did Vo increase when the LED is turned on?

Construct the circuit of Figure (b) and repeat measurements of Vo. Did Vo

increase?

1-58


+SV +SV

A

A B

B

Vo

(a) (b)

2. Besides driving each other, how is TTL and CMOS applied to drive other loads

such as LED; light bulbs and motors?


( ) 1. Which of the followings consume the most energy?

1. Transistor

2. FET (Field-Effect-Transistor)

3. CMOS

) 2. Which series of TTL gate has higher speed?

1. 74LS

2. 7400

3. They have equal speed

) 3. What should be done when a CMOS gate can not drive a TTL gate?

1. Quit

2. Add an inverter

3. Increase the current

) 4. What should be done when a TTL gate can not drive a CMOS gate?

1. Add an inverter

2. Add a resistor

3. Remove a resistor

( ) 5. TTUCMOS gates are capable of driving 11 OV loads under which condition:

1. Direct drive is possible

2. Impossible

3. Possible with external interface

1-59

COMBINATIONAL LOGIC CIRCUITS

2-1 NOR Gate Circuit 2-2 NAND Gate Circuit 2-3 XOR Gate Circuit

a. Constructing XOR Gate with NAND Gate b. Constructing XOR Gate with Basic Gate

2-4 AND-OR-INVERTER (A-0-1) Gate Circuit 2-5 Comparator Circuit

a. Comparator Constructed with Basic Logic Gates b. Comparator Constructed with TTL IC

2-6 Schmitt Gate Circuit 2-7 Open-Collector Gate Circuit

a. High Voltage/Current Circuit b. Constructing an AND Gate with Open-Collector Gate

2-8 Tristate Gate Circuit a. Truth Table Measurements b. Constructing an AND Gate with Tristate Gate c. Bidirectional Transmission Circuit

2-9 Half-Adder and Full-Adder Circuit a. Constructing HA with Basic Logic Gates b. Full-Adder Circuit with IC c. High-Speed Adder Carry Generator Circuit d. BCD Code Adder Circuit

2-10 Half-Subtractor and Fuii-Subtractor Circuit a, Subtractor Circuit Constructed with Basic Logic Gates b. Full-Adder and Inverter Circuit

2-11 Arithmetic Logic Unit (ALU) Circuit 2-12 Bit Parity Generator Circuit

a. Bit Parity Generator Constructed with XOR Gates b. Bit Parity Generator IC

2-13 Encoder Circuit a. Constructing a 4-to-2 Encoder with Basic Gates b. Constructing a 9-to-4 Encoder with TTL IC

2-14 Decoder Circuit a. Constructing a 2-to-4 Decoder with Basic Gates b. Constructing a 4-to-1 0 Decoder with TTL IC

2-15 Multiplexer Circuit a. Constructing a 2-to-1 Multiplexer b. Using Multiplexers to Create Functions c. Constructing a 8-to-1 Multiplexer Circuit with TTL IC

2-16 Demultiplexer Circuit a. Constructing a 2-output Demultiplexer with Basic Logic Gates b. Constructing a 8-output Demultiplexer with CMOS IC

2-17 Digitally Controlled Analog Multiplexer/Demultiplexer Circuit a. Analog Switch Characteristics b. Bidirectional Transmission with CMOS IC Analog Switch


CHAPTER 2 COMBINATIONAL LOGIC CIRCUITS EXPERIMENTS

Combinational logic circuits are constructed with ba~ic logi<:; gates. Its output will

correspond only to the current input, previous inputs and outputs can't influence the

current output. Therefore the output of any s?mbinational logic circuits can be

expressed by Boolean functions.

The major components of a combinational logic circuit includes Input Variables; Logic

Gates and Output Variables. The input variable could be either higher or lower than

the output variable but both are binary signals, or "0" and "1".

Assuming there are "n" input variables, there will be 2 possible input combinations,

each with one corresponding output combination. Before designing and constructing

a combinational logic circuit the following information should be taken into

consideration:

1. Truth tables of logic gates

2. Boolean Function

3. Karnaugh Map

4. de Morgan's Theorem

The following combinational logic gates are used very often and they are discussed in

this chapter, along with many other combinational logic gates.

1. Combinational logic circuits with NAND and NOR gates

2. AND-OR-INVERTER (A-0 -1) gate

3. XOR gate

4. Open-collector gates

5. Tristate gate

6. Arithmetic circuits

7. Encoder and decoder circuits

8. Multiplexer and demultiplexer circuits

9. Comparator circuits

2-2


2-1 NOR Gate Circuit

OBJECTIVE

Understanding how to construct other combinational logic gates using NOR gates.

DISCUSSION

The symbol of a NOR gate is shown in Fig. 2-1. The Boolean expression for the NOR

gate is F= A+ B ; in de Morgan's theorem, F= A+ B =A x B.

When A=fl, F= A+ B =A +A= A. When B=O, F= A+ B =A+ 0 =A . Therefore, the NOR gate can>be used to construct NOT; OR; AND; NAND; and XOR gates. We will attempt to construct various logic gates in this experiment by connecting NOR gates in different ways.

Fig. 2-1 Symbol of NOR gate

EQUIPMENTS REQUIRED

KL-31 001 Digital Logic Lab; Module KL-33002

PROCEDURES

1. U1 a of Fig. 2-2 (a) will be used to construct a NOT gate.

2. Connect inputs A, B to Data Switches SWO, SW1 and output F1 to Logic Indicator

L 1. Set SWO to "0", observe states of F1 at SW1 ="0" and SW1 ="1 ".

Does the circuit act as a NOT gate? (as in Fig. 2-2 (b)?)

3. Insert a connection clip between A and B. Connect A to SWO and 171 to L 1. What

is the state of F1 when SWO=O and SW0=1?

Does the circuit act as a NOT gate?

2-3


r-----------------------------, I R3 R4 R5 ·~~~~----~~----0 I R6 I A ~a--'VV'v----. I A1 I I 1 v a-· .~ I I

: ~U1b : F2 81

I ° KL-33002 block a L-----------------------------J Fig. 2-2 (a)

A~A~F ~F~

Fig. 2-2 (b) NOR gate used as NOT gate

4. Use U 1 a and U1 c to construct a buffer shown on the left side of Fig. 2-2 (c). Insert

connection clips between A ......,B; F1 ......,A1 ; A1 ......,B1. Connect input A to SWO and

output F3 to L 1. What is the state of F3 when SWO=O and SW0=1?

Does the circuit act as a buffer?

~·~FA~.~A~ B~

Fig. 2-2 (c) NOR gate use as Buffer and OR gate

5. Use U1a and U1c to construct an OR gate shown on the right side of Fig. 2-2 (c) .

Insert connection clips between F1 ......,A 1 and A 1......, B1. Connect inputs A to SWO, B

to SW1 ; and output F3 to L 1. Follow the input sequences shown below and

record the output states in Table 2-1.

SW1 (B) SWO(A) F

0 0

0 1

1 0

1 1

Table 2-1

2-4


6. Insert connection clips according to the figure below. The circuit will act as an

AND gate.

( 1) Connect A to SWO; D to SW1 ; F 1 to A 1 ; F2 to 81 ; F3 to L 1 .

(2) Follow the input sequences given below, record the output states in Table 2-2.

RESULTS

r-----------------------------, R3 R4 R5

y

R6

F2 D

KL-33002 block a L-----------------------------~

SW1 (D) SWO(A) F3

0 0

0 1

1 0

1 1

Table 2-2

1. NOR gate can be used to construct just about any basic logic gate.

2. There are two ways to use NOR gate as an inverter. Since TTL gates have higher

current when the input is grounded, if TTL NOR gate is to be used as an inverter,

its two inputs should be connected together.

FAULT SIMULATION

1. U1 a and U1 care used as a buffer and the outputs stay in high state. Try to locate

all possible faults.

2. The outputs stay at low state when U1a and U1c are used as a buffer. Try to

locate all possible faults.

3. When U1a, U1b, U1c are ~sed as an AND gate, the output F is only affected by

the input A. What could be the fau lts?

2-5


EXERCISES

1. Try to construct various types of basic gates with CMOS NOR gates.

2. A NOR gate will act as a NOT gate if one of the two inputs is connected to "0".

What happens if one input is connected to "1"?


) 1. What is the symbol of a NOR gate?

) 2. What is the symbol of a NOT gate?

) 3. NOR gates can be used as:

) 4. What is the output F for this gate?

A~

( ) 5. What is the output F for this gate?

ALL>

) 6. F is equal to :

AD-F

2-6

1. Oper~tional amplifier

2. Buffer

3. Distributor

1. A

2. A 3. 1

1. A

2. A 3. 0

1. A

2. A

3. 0


) 7. The output F of this gate can be expressed as:

:v-F 1.A+B

2. A+B

3. A-8

( ) 8. Which of the following gate symbols can be 4sed to construct a NAND gate?

2-7


2-2 NAND Gate Circuit

OBJECTIVE

Understanding how to constructed various combinational logic gates with NAND

gates.

DISCUSSION

The symbol of a NAND gate is shown in Fig. 2-4. The Boolean expression for a

NAND gate is F= A x B ; in de Morgan's theorem, A x B =A+ B .

WhenA=B, F=A x B=A . When 8=1 , F=A x B=A x 1 =A . Like the NOR gates, NAND gates can be used to construct just about any basic logic gates. We will attempt to

construct various basic gates in this experiment by connecting NAND gates in

different ways.

::cr· Fig. 2-4 Symbol of NAND gate

EQUIPMENTS REQUIRED

KL-31001 Digital Logic Lab; Module KL-33002

PROCEDURES

1. Insert connection clips according to Fig. 2-S(a), using U2c and U2d to construct

the NOT gate shown on left side of Fig. 2-S(b).

r-A-------------------------------1 I I I I I I I l :~A1 I D ~ ! 81 "'--.J"--... I I I I I

: KL-33002 block b L---------------------------------J Fig. 2-5 (a)

2-8


~F2 "1"~ A~F2

(b) NOT gate constructed with NAND gate

(1) Connect input A to Data Switch SW1 and output F2 to A2 and Logic Indicator L 1;

connect 81 to Vee ("1"). Observe the output states.

When SW1="0", F2= __ _

When SW1="1", F2= ___ _


(2) Connect input A 1 to Vee ("1 ") and remove the connection clip between A and A 1

to create the NOT gate shown on the right side of Fig. 2-5 (b). Other connections

remain the same. Observe the output states.

When SW1="0", F2= __ _

When SW1="1", F2= __ _


(3) Remove connection clips and insert them again according to Fig. 2-6 (a) to

construct the AND gate shown in Fig. 2-6 (b). Connect A to SW1, A 1 to SW2 and

F4 to L 1. Follow the input sequences given below and record the outputs in Table

2-4.

Does the circuit act as an AND gate (F=A x B)?

Fig. 2-6 (a)

2-9


A SW2(A1) SW1(A) F4 F

B 0 0

0 1

(b) 1 0

1 1

Table 2-4

2. Insert connection clips according to Fig. 2-7 (a) to construct the circuit of Fig. 2-7

(b). Connect A to A 1 and SW1 ; F2 to A2; D to 81 and SW2; F3 to 82; F to L 1.

Follow the input sequences in Table 2-5 and record the outputs.

Does the circuit act as an OR gate (F=A+8)?

Fig 2-7 (a)

A

F

D

(b) OR gate constructed with NAND gate

SW2(D) SW1(A) F4

0 0

0 1

1 0

1 1

Table 2-5

2-10


RESULTS

1. NAND gates can be used to construct any basic logic gate.

2. There are two ways to construct inverters with NAND gates. Since the high state

of TIL consumes almost no current, if NAND gates are used to construct

inverters the spare input should be connectedJo high potential.

FAULT SIMULATION

1. The output F2 remains in low state when U2b is used to construct a NOT gate.

What could be the faults?

2. When U2b, U2c, U2d are used to construct an OR gate, the output F remains in

high state. What could be the faults?

EXERCISES

1. Construct various basic logic gates with CMOS NAND gate.

2. If one of the two inputs of a NAND gate is connected to "1", it will act as a NOT

gate. What happens if one input is connected to "0"?


( ) 1. The output F of a NAND gate is equal to:

1. A+B

2. AB

3. A+B

) 2. Which of the followings can be used to construct a NOT gate?

( ) 3. A ij is equivalent to which of the followings?

CD

2-11


( ) 4. --cD- is equivalent to which of the followings?

Q)

( ) 5. Which of the followings can be used to construct a NOR gate?

Q) @ ®

D-) 6. Which of the followings is a buffer?

Q) @

.. :.D-F ) 7. Which of the followings is a NOT gate?

Q) @ ®

2-12


2-3 XOR Gate Circuit

OBJECTIVE

Understanding the characteristics of X()R gates.

DISCUSSION

The symbol of a XOR gate is shown in Fig. 2-8. The output F is equal to ---A E.e B = .AB + AB . XOR gates can be constructed using NOT, OR, AND, NOR or NAND gat~s or by using four NAND gates, as shown in Fig. 2-9 (a) and (b).

Fig. 2-8 Symbol of XOR gate

F F

(a) with basic gates (b) ;Jith NAND gates only

Fig. 2-9 XOR gate circuits

Since F = AB+ A§ , wh~n 8=0 F = A x 0 + A x 0 = A x 1 = 1 and the circuit act as buffer. When 8=1 , F = A x 1 +Ax 1 = A x 1 = A, the circuit act as an inverter. In other words, the if'lput state of a XOR gate determines whether it will act as a buffer or an inverter. In this experiment, we will use basic logic gates to construct XOR gates and study the relationship between the inputs and outputs.

EQUIPMENTS REQUIRED

KL-31001 Digital Logic Lab, Module KL-33002

PROCEDURES

(a) Constructing XOR gate with NAND gate (Module KL-33002 block b)

1. Insert connection clips according to Fig. 2-10 (a) to construct the circuit of Fig.

2-10 (b). Co nne~ j!'}puts A to ?W1, D to SW2; outputs F1 to L 1, F2 to L2; F3

to L3 and F4 to L4.

2-13


r---------------------------------, I A I o-~--------~ I I I I I I I I D I I I I I

l KL-33002 block b L---------------------------------J Fig. 2-10 (a)

F

02:7400

(b) equivalent circuit

2. Follow the input sequences for A and Din Table 2~6 and record the outputs.

INPUT OUTPUT

D A F1 F2 F3 F4

0 0

0 1

1 0

1 1

Table 2-6 :·: '>:····

3. Determine the Boolean expression for F1, F2, F3, F4.

2-14


(b) Constructing XOR Gate with Basic Gate (Module KL-33002 block c)

1. Insert connection clips according to Fig. 2-11 (a) to construct the equivalent

circuit of Fig. 2-11 (b).

2. Connect inputs A, B to SW1, SW2; outputs F1, F2; F3 to L 1, L2, L3.

r----------------------------------, ~ A : I I

: A1 : I I I F4 I I F7 I I I I I I I

.·< I I . 1 B I

I I I I I I I I I I I I I I

: KL-33002 block c I ~----------------------------------J

Fig.2-11 (a)

F3

-l} U3b+U4c

U3:7400 U4:7416

(b) equivalent circuit

3. Follow the input sequences for A and Bin Table 2-7 and record the outputs.

INPUT OUTPUT

SW2(8) SW1 (A) F1 F2 F3

0 0

0 1

1 0 1 . 1

2-15


RESULTS

1. XOR gate can be constructed with either basic gates or four NAND gates with the

same results. However, using four NAND gates is much simpler.

2. By adding a NOT gate to the output of a XOR gaJe it can be converted into an

XNOR.

FAULT SIMULATIONS

1. What could be wrong if 4 NAND gates are used to construct a XOR gate and the

output F=O?

2. What could cause the output F3 of a XOR gate made with basic gates to remain

in high state?

EXERCISE

1. Can a XOR gate be constructed using just one NOR gate? Draw the circuit

diagram and construct the circuit ti verify the circuit.

2. What is the output F if one input is "1" for a XOR gate?

2-16



) 1. Which is the correct symbol of a XOR gate?

1. =D--

2. D

3. :D--F ..

( ) 2. Whrch of the following gates can be used to constract a XOR gate when there

are four of them?

1. OR

2. NOT

3. NAND

) 3. Which of the following gates can be used to construct XOR gate?

1. OR

2. NOT

3.AND

) 4. The output F of this logic gate can be expressed

as: ::D-" 1. AB + AB 2. A ED B

3. AB+AB

) 5. The Boolean expression for the output of a XOR gate is :

1. AB+AB

2. AB + AB

3. AB+AB

2-17


( ) 6. How many basic logic gates are required to construct a XOR gate?

1. 4

2. 5

3. 6

( ) 7. This gate symbol :::JL>-F is equal to.

1.

2.

:~F 3.

( ) 8. Which logic gate should be used if its two inputs do not equal to "1" at the

same time?

1. AND

2.XOR

3. 0R

~:

2-18


2-4 AND-OR-INVERTER (A-0-1) Gate Circuits

OBJECTIVE

Understanding the basic principled of combined logic.

DISCUSSION

AND-OR-INVERTER (A-0-1) gates consist of two AND gates, one OR gate and one INVERTER (NOT) gate. The symbol of an A-0-1 gate is shown in Fig. 2-12. The Boolean expression for the output F is

F=AB+CD' .............. Equation (1)

A

B

F

c

0

Fig. 2-12

Equation (1) can be converted into de Morgan's theorem as :

F=( A+ B )x( C +D) ......... Equation (2)

Equation (1) is also referred to as "Sum of Products".

Equation (2) is also referred to as "Product of Sum".

Basically, the A-0-1 gate is a "Sum of Products" logic combination.

EQUIPMENTS REQUIRED

KL-31001 Digital Logic Lab; Module KL-33002

PROCEDURES

1. Use U3a, U3b, U3c and U4c on block c of Module KL-33002, shown in Fig. 2-13

(a), to construct the A-0-1 gate of Fig. (b). Fig. 2-13 (c) is the equivalent A-0-1

circuit which uses U3a, U3b, U3c used as the OR gate.

2-19


(a)

A

A1

F4

B1

B

(b) actual circuit

A

A1

F4

81

B

(c) equivalent circuit

Fig. 2-13A- 0 -I circuit

2. Connect inputs A, A 1, B, B 1 to Data Switches SWO, SW1, SW2, SW3 respectively.

Connect outputs F3, F4 to Logic Indicators L 1 and L2.

3. Set BxB1 to "0", follow the input sequences for A, A1 in Table 2-8 and record the

outputs.

2-20

8x81=0

A1 A

0 0

0 1

1 0

1 1

Table 2-8


F3 F4

Does F3 act as an AND gate between A and A 1?

4. WhenBx81 =i=O, Does F3 act as an AND gate between A and A 1?

(F3=AxA1)

5. When A=A1=0, follow the input sequences for 8 , 81 in Table 2-9 and record the

outputs.

A1 xA=O

81 8

0 0

0 1

1 0

1 1

Table 2-9

F3 F4

Does F3 act as an AND gate between 8 and 81?

6. When AxA1 =i= O, Does F3 act as an AND gate between 8 and 81?

7. Does F3 equal toAxA1+8x81?

2-21


RESULTS

1. A-0-1 gate can also be constructed using two AND gates and one NOR gate.

2. The following TIL ICs has A-0-1 function : 7450~ 7451 ; 7453; 7454; 7460; 7464;

6465. Some of them are 2- input OR gates and some are multiple-input OR gates.

Some has expanded input terminals or open output gates to enable logic

combination capabilities.

FAULT SIMULATION

1. The output F4 remains in low state, regardless of the input states of A, A 1, 8 , 81 .

What could be the problem?

EXERCISES

1. Construct an A-0-1 gate with CMOS basic logic gates.

2. Construct a "Product of Sum" circuit with F=( A + 8 )x( C +D).

3. The output of an A-0-1 gate is A8 + CD, what is the output if C= A ·· .. and D= 8?


) 1. What logic does the A in A-0-1 represent?

1<AND

2. NAND

3.AN

) 2. What is the output of an A-0-1 gate?

1. A8+CD 2. (A+8)x(C+D)

3. A8CD

( ) 3. "Sum of Products" is expressed as :

1. A8+CD

2. (A+8)x(C+D)

3.A8CD

2-22


) 4. The abbreviation for "Sum of Products" is :

1. POS

2. SOP

3. PSO

) 5. The abbreviation for "Product of Sum" is :

1. POS

2. SOP

3. PSO

( ) 6. A~d21 is basically a :

1. POS gate

2. SOP gate

3. Either

) 7. If C= A and D= B for the output F ( AB + CD) of an A~O~I gate, it is equivalent to a :

1. OR gate

2. XOR gate

3. NAND gate

) 8. What does the 0 in A-0-1 represent?

1. ON

2. OR

3. OF

2-23


2-9 Half-Adder and Full-Adder Circuit

OBJECTIVE

Understanding the characteristics of half-adder and full-adder in the arithmetic unit.

DISCUSSIONS

Adders can be divided into "Half-Adder'' (HA) and "Full-Adder'' (FA). Half-adders

follow the rules of binary addition and consider only the addition of 1 bit. The result of

addition is a "carry" and a "sum". In binary additions, a "carry" is generated when the

sum of two numbers are greater than 1. Refer to the half-adder addition below :

1 + 1 10

Carry _j Lsum

1 ~Previous Carry 1 0 ~Augent

+ 1 0 ~Addend 10 0

Carry _j L Sum

When "1" and "1" are added the sum is 0 and the carry is 1. The half-adder is limited

to the addition of 1-bit numbers.

The full-adder can perform additions of numbers greater than 2-bits in length. Refer to

the full-adder operation shown below. It can be constructed using two half-adder. Fig.

2-37 (a) and (b) shows half-adder and full-adder circuits and symbols respectively.

(a) Half-adder

s ASS H.A B C c

(b) Full-adder

Ci 5

Fig. 2-37 Half-adder/Full-adder

2-50


To perform additions of numbers greater than 2-bits in length, the connection shown

in Fig. 2-38, or "Parallel Input" should be used to generate sums simultaneously.

However, the sum of the next adder will be stable only after the previous adder's carry

has stablized. For example, in Fig. 2-38, the sum of FA2 will not be stable unless the

carry of FA 1 is stable.

B4 A4 83 A3 82 A2 81 A1

C4 co

54 53 52 51

-:~ Fig. 2-38

.·. "

\1\J!len FA1 adds A1 and 81, a sum S1 and a carry C1 is generated. C1 will be added

to A2 and 82 by FA2, generating another sum S2 and another carry C2. In the case of

Fig. 2-38,sum of the four adders do not stablize at the same time, dalaying the adding

process. This delay can be eliminated by using the "Look-Ahead" adder.

Look-ahead adders do not have to wait for the previovs adder ~o stablize before :-.·.· ...

performing the next addition, saving valuable time,> lh Boolean expression we

assume :

Pi =Ai EB Bi

Gi =Ai xBi

The output and carry can be expressed as :

Si = Pii\Cj

Ci+1 = Gi + PiCi

Gi is called "Carry Generate". When Ai and Bi are both "1", Gi is "1" and unrelated to

the carry input.

Pi is called "Carry Transmit", related to the carry transmit between Ci and Ci+1 .

If we substitute the carry function of each stage by the previous carry we get :

C2 = G1 + P1 C1

C3 = G2 + P2 C2 = G2 + P2 G1 + P2 P1 C1

C4=G3+P3C3=G3+P3P2G1+P3P2P1C1

2-51


Fig. 2-39 shows the carry path of a look-ahead adder. The 7 4182 is a look-ahead

adder TTL I C.

P2 ___ ~--4-+-~_J G2--t---tt~~~ P1 --~---4-+--~~

G1 ------~~--------~

C1 --------'

', .. t Previous Carry

Fig. 2-39

C4 ...

C3

C2

Binary adders can be converted into BCD adders. Since BCD has 4 bit~> with the

largest number being 9; and the largest 4 bit binary number is equivalent to 15, there

is a difference of 6 between the binary and the BCD adder: Under th~following

conditions 6 must be added when binary adders are used to add seb cod~s : 1. When there is any carry

2. When the sum is larger than 9

If the order of priority is S8, S4, S2, S1 and the sum is larger than 9 then

SB x S4+S8u x S?. If anyg~r[X)~ involved, assuming the carry is CY, under this term,

6 must be added i/ ·

CY + S8 X S4 + S8 X S2

2-52


Fig. 2-40 is the circuit of a BCD adder.

Addend Augent I I I I I I I I

cyiB4B3B2B1 A4A3A2A11 CO

_ _!~....---,.-~ Previous Carry

Final carry

B4B382B1A4A3A2A1Co

4-bit ADDER

Fig. 2-40

EQUIPMENTS REQUIRED

KL-31001 Digital Logic Lab, Module KL-33003/KL-33004

PROCEDURES

(a) Constructing HA with Basic Logic Gates

1. Insert connection clips according to Fig. 2-41, using U2a and U3a to

assemble the half-adder circuit of Fig. 2-42. Connect Vee to +SV.

2-53


~. t1 C I

2. Connect inputs A and 8 to Data Switches SWO and SW1.Connect

outputs F1 and F2 to Logic Indicator L 1 and L2. Follow the input sequences

for A and 8 in Table 2-16 and record the output states. Determine which

output is the sum and which is the carry

INPUT OUT SW1(B) SWO(A) F1 F2

o o I 0 0

F2 1. <> I I

0 ' l

0 1 1

1 0 1

Fig. 2;42 Table 2-16

3. Reassemble the circuit according to Fig. 2-42 (a) to construct the full-adder

circuit shown in Fig. 2-42 (b).

Connect A, 8, C to SW1, SW2 and SW3. A and 8 are augends while C is the

previous carry. Connect F3 to L 1, FS to L2. Follow the input sequences in

Table 2-17 and record output states. Determine which output is sum and which is the carry.

OUTPUT OUT _.

SW3(C) SW2(8) SW1(A) F3L FSL

0 0 0

0 0 1 \ t L2("A..)

0 1 0 ' -L)._ (

0 1 1 \ lr

1 0 0 '~ \ tl..

1 0 1 / L1

1 1 o/ l , 1 1 1 L\ l"\.-

Table 2-17

2-54


r--------------------, I U1a FO I I I I /~ I I I I F3 I I I I I I A I I I I I IB F2 / A2 I I F4 I I I I c I I FS I I I I I I I I A3 I I D I I I I E I I I I KL-33004 block a I L--------------------~

(a)

U2:7486 U3:7408 U4:7432

F3

}------<>FS

(b)

Fig. 2-43 Full-adder circuit

(b) Full-Adder Circuit with IC

1. U5 on block b of module KL-33004 is used as a 4-bit adder. Connect input Y5

to "0", so the XOR gates U6a-U6d, which are connected to YO-Y3, will act as

buffers.

Connect inputs XO-X3 (addends}, YO-Y3 (augends) to DIP Switches

DIP2.0-2.3 and DIP1.0-1 .3 respectively. Connect F1 , ro, r1, r2. r3 to

L 1-L5. Follow input sequences in Table 2-18, record F1 and r in hexadecimal

numbers.

(X and Y can also be connected to the Thumbwheel Switches)

X= X3 X2 X1 XO

Y = Y3 Y2 Y1 YO

r = r3 u n ro

2-55


---------------------------, • U5,U9:7483 Y3 Y2 Y1 YO I I U8:7486 I 1 U3:7408 I I U4:7432 I I I I I I I I I I I I I I F1 Y4 I I Cln

13 I I I I 0 0 D m I I 15 2 s 9 I I F10 I I I I I I F8 I I I I F9 I I I I I I I I I I I 1 10 16 4 7 11 1 I 83 B2 81 80 1 I 14 1 I I FJ U9 Cln

3 I I .,.. I I I I 1s 2 6 9 I I I I F7 F6 F5 F4 block b I L--------------------------~

Fig. 2-44

INPUT OUTPUT y X r F1(CARRY)

0 0

0 1 0 / 6

0 9

0 F

1 3

1 6

1 8

3 6

4 8

4 F

8 7

9 9

A 8

c E

F F

Table 2~18

2-56


(c) High-Speed Adder Carry Generator Circuit

1. U3 (74182) on block a of module KL-33003 is used to construct a carry

generator circuit. Fig. 2-45 (b) is the truth table and logic diagram for the

74182.

r--------------------, I I AOO--r-"\ I

: BO I I o---r-""' ~ A1 --1..---' I 81 : ~~.J.C';' I o---.--r-"""'\ l A2 ,....._.____,

I B2 I o-J~-IC.':" I 'o---f"~ I A3 I .-t-t..---'

I Bl I o-JI--+L.:/ I 1 U1:74l.500 I U2:74LS266

L2~~~1~---~~~~~0J~!~~~J

Fig. 2-45 (a)

~~~~)---~(7~)-....1 PorX

Pi or X2 !..:(1~5)+.+-4-+4-~,...., GzorY2(14)

Fig.2-45 (b)

2-57

or Cn+z

Cn+x


TRUTH TABLE

INPUT OUTPUTS

Cn - - -

Cn+z Go Po G1 p1 G2 p2 G3 P3 G p

X H H

L H X

X L X

H X L

X X X H H L

X H H H X L

L H X H X L

X X X L, .. / :X H .. ::·· t X L X x.······· H

H X X L H

X X X X H H L

X X X H H H X L

X H H H X H X L

L H X H X H X

X X X X X L X

X X X L X X L

X L X X L X L

H X L X L X L

X X X X X H H H

X X X H H H X H

X H H H X H X H

H H x .. H X H X H

X X .X X L X L

X ·~::::::·:

X X L X X L L \:~·:>

X L X X L X L L

L X L X L X L L

H X X X

X H X X

X X H X

X X X H

L L L L L

H=HIGH Voltage Level

L=LOW Voltage Level

X=lmmaterial

2-58

83

0

0

0

0

1

1

1

0

1


2. Connect inputs AO-A3 (addends) to DIP Switches 1.0-1.3; 80-83 (augends)

to DIP2.0-2.3, G and Pare triggered by "0".

Cn + x = GO + POxCn

Cn + y = G1 + P1 xGQ + P1 xPOxCn

Cn + z = G2 + P2xG1 + P2xP1 xGQ + P2xP1 xPOxCn

G = G3+P3xG2 + P3 x P2 x G1 P2xP1 x PO x GO -P = P3 x P2 xP1 x PO

If Cn = 0, then

Cn +X= AOx80

Cn + y =A 1 x81 + (AOEB80)x(AOx80)

Cn + z = A2x82 + (A2EB82)x(A1 x81) + (A2 EB 82)x(A1 EB 81)x(AOx80)

G = A3 X 83 + (A3 ffi 83) X (A2 x 82) + (A3 ffi 83) x (A2 ffi 82) x (A 1 x 81)

+ (A3 ffi 83) x (A2 Ef) 82) x (A 1 Ef) 81) x (AO x 80)

P = P3x P2 x P1 xPO

Follow the input sequences in Table 2-19 and record output states .

. :,

INPUT OUTPUT -

82 81 80 A3 A2 A1 AO Cn+x Cn+y Cn+z G p

0

0

0

0

0

1

1

1

0

0 1 0 0 0 1

1 0 0 0 1 0

0 0 0 0 1 0

1 1 0>0 1 1

1 0 1) 0 0 0

1 0 1 1 1 1 .;;.

1 1 1 1 0 1

1 1 0 1 1 0

0 1 0 1 0 1

Table 2-19

Compare the results vAth the truth table. Are they identical?

Since Cn= 0, the last carry CY =G.

2-59


(d) BCD Code Adder Circuit

1. The circuit shown in Fig. 2-46 will act as a BCD code adder. r-----------------------------, 1 n n n ~

I I I I I I I I I I F1 14 13 Y4 I Cin t-=---<~-0

9

F10

F8

I F9 I

I I I I

I I 1 10 16 4 1 11 1 I 83 82 81 BO I I 14 13 I I F3 U9 Cln I I I I I I I I I I F7 F6 Fs F4 KL-33004 block b 1 L-----------------------------J

Fig. 2-46

2. Connect inputs XO-X3 to DIP1.0-1 .3; YO-Y3 to DIP2.0-2.3; Y5 to "0". Fig.

2-47 is the equivalent circuit.

2-60

F1

F3


Y3 Y2 Y1 YO

Cin 13

t3 E2 I1 EO

F8 F11

F9

10 16 4 7 11 83 B2 81 BO

F7 F6 F5 F4

Fig. 2-47

13 C in

Y4

U5 and U9 are 7483 look-ahead 4-bit BCD adders, connect outputs F8-F11

of U5 the inputs of one of the 7-Segment Digital Display. F8-F11 should also

be connected to L 1 ..... L4. Connect F1 , F2 to Logic Indicators L5, L6.

Connect outputs F4-F7 of U9 to another 7 -segment display. Also connect

F4-F7 to L7-L 10 and F3 to L 11 .

3. F11-F8 are the sum of XO-X3 added to YO-Y3 while F1 is the carry. Follow

the input sequences for XO-X3 and YO-Y3 in Table 2-20 and record the

output tates.

2-61


INPUT OUTPUT( US) LAST(U9)

X3 X2 X1 xo Y3 Y2 Y1 YO F1 F11 F10 F9 FS F2 F3 F7 F6 F5 F4

0 0 0 0 0 0 0 0

0 0 0 1 0 0 1 1 ,.. .

0 0 1 1 0 1 0 0 ·---.. ~:..-

0 0 1 0 0 0 1 0 i \. ..

0 0 1 0 1 0 0 0

0 0 1 1 0 1 1 0

0 1 0 0 0 0 1 0

0 1 0 0 0 1 0 1

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 0

0 1 1 0 0 1 1 1

0 1 1 1 1 0 0 0

0 1 1 1 1 0 0 1

1 0 0 0 1 0 0 1

1 0 0 1 1 0 0 1 1 '

-------------------- ---- ---------------- ---------------------------- --------- -- -----~-----------------1 0 1 0 1 0 1 0

_l ~~ 1 0 1 0 1 0 1 1 \ 1 0 1 0 1 1 0 0

··. ~

1 0 1 1 1 1 1 0

1 1 1 1 1 1 1 1

Table 2-20

4. Connect inputs XO-X3, YO-Y3 to the Thumbwheel Switches and outputs

F7 -F4 to the 7.;$egment digital display. Adjust the inputs randomly and

observe the outputs.

RESULTS

1. Adders can be further classified into "half-adder" and "full-adder".

2. Binary adders can be converted into BCD code adder.

3. The circuitry of "look-ahead" adder is quite complicated. Unless very high speed

is required, it is not used very often.

FAULT SIMULATION

1. Locate the problem(s) if F1 remains at "1" for a full-adder.

2. During BCD code adding operation, F2=F 1 when F1 =1 . What could cause this

problem?

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) 1. What can be constructed with one XOR and one AND gate?

1. Full-subtracter

2. Half-adder

3. Full-adder

( ) 2. F.A. is the abbreviation for :

1. Half-subtracter

2. Full-adder

3. Full-subtracter

( ) 3. What is the correct compensation when binary adding is converted to BCD

code adding?

1. Add 6

2. Subtract 6

3. Subtract 9

( ) 4. If S= A EB B, C =Ax B for a half-adder, S could be expressed as :

-1. S =AB+AB

2. S =AB+AB

S =AB+.AB

) 5. What the final sum (S) and carry (C) for a F.A. if both inputs A and B are

equal to 1 and the previous carry is "1 "?

1. C=1,S=1

2. c = 0, s = 1

3. c = 1, s = 0

) 6. Which of the following equations is true for inputs A , B, su~ S and carry C?

-1. s = A ffi B, c = A X B

2. S = A+B,C = AxB

3. S = A $8,C=AxB

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( ) 7. Which of the following statements is true for BCD adding?

1. It can't be done using binary adding operation

2. It can be done using binary ~sl:~ing q~ration but has to be

compensated

3. A new decimal adder circuit have to be designed

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2-10 Half-Subtractor and Fuii-Subtractor Circuit

OBJECTIVE

Understanding the theory of complements and construction of subtractor circuits.

DISCUSSION

Half-subtractor and full-subtractor circuits can be built by referring to the truth tables

and the Boolean expressions, or Karnaugh's map of logic gates. In this experiment we

will use the theory of complement to assemble full and half subtractor circuits.

Binary subtraction are usually performed by 2's complement. Two steps are required

to obtain 2's complement. First, the subtrachend is inverted to its 1's complement, i.e.

an "1" to a "0" and a "0" to an "1". Secondly, an "1" is added to the least significant

digit of the subtrahend in 1's complement.

In general subtraction the subtrahend is directly subtracted from the minuend but in

2's complement, the two numbers are added. Hence an adder also can be used as a

subtractor.

EXAMPLE:

What is the equivalent in 2's complent for the decimal subtraction of 11 - 1 0?

MINUEND 11 (DECIMAL) = 1011 (BINARY)

SUBTRAHEND : 10 (DECIMAL) = 1010 (BINARY)

= 0101 (1'S COMPLEMENT)

= 0110 (2'S COMPLEMENT)

DECIMAL BINARY 1'S COMPLEMENT 2'S COMPLEMENT

11 1011 1011 1011

10 1010 1011 + 0110

1 1 0 10001

A carry of "1" is generated in the 2's complement subtraction.

2-65


A half-subtracter execute its task of subtraction 1-bit at a time regardless of whether

the minuend is greater or less than the subtrahend. The true table and logic diagram

of a half-sub tractor is shown in Fig. 2-48. "Borrow" from previous subtraction are not

taken into consideration.

Subtrahend ,.. Minuend

A B 0 1 0 0 1 1 1 0

pitference Borrow

DF BW 0 0 1 1 1 0 0 0

A o-----t----~~

B o---1--t-----:~f-1

(a) Truth table

(b) Schematics

Fig. 2-48 Half- subtracter

DF

BW

Compare the logic diagrams of half-subtracter with half-adder and we can see that

the only difference is the inverter at the input of the half-subtracter. This inverter gate

represent the borrow.

The full-subtracter has to consider borrow(s) from previous stages. Its truth table and

logic diagram are shown in Figure 2-49. When C = "0" it is equivalent to a

half-subtracter.

Previous borrow Minuend

Subtrahend Difference

Borrow c A B DF BW 0 0 1 0 0 0 0 0 1 1 0 1 1 1 0

A

0 1 0 0 0 1 0 0 1 1

B

1 0 1 0 1 1 1 0 0 0 c 1 1 1 1 1

(a) Truth table (b) Schematics

Fig. 2-49 Full-subtracter

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From a 4-bit adder circuit we can assemble subtractor circuits of 4-bit or longer. Fig.

2-50 shows a dual-purpose adder/ subtractor circuit. When Bn-1 ="0" additions are

performed and all XOR gates act as buffers. When Bn-1="1" subtractions will be

performed and all XOR gates act as NOT gates. Y inputs uses 1's complement and

adds an "1" from Cin. The outputs are Cn (carry) and Bn (borrow), Cn and Bn are

dependent on Bn-1 .

Fig. 2-50

EQUIPMENTS REQUIRED

KL-31001 Digital Logic Lab, Module KL-33004

PROCEDURES

(a) Subtractor Circuit Constructed with Basic Logic Gates

1. Insert connection clips sccording to Fig. 2-51 .

2. Connect inputs A-C to Data Switches SWO-SW2;outputs F2 to Logic

Indicator L 1; F1 to L2; F3 to L3; F5 to L4. When C=O the circuit is a

half-subtractor. F1 is the borrow output; F2 is the difference and F5=F2; F4=0;

F3=F1 . When C=1 the circuit is a full-subtractor. F3 is the borrow output and

F5 is the difference output.

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D~----------A-3~ ~ i~-------~-

KL-33004 block a L--------------------J Fig. 2-51 Half-adder/Full-adder

3. Follow the input sequences in Table 2-21 and record output states.

Input

C A

Half- subtracter [ g Half-adder 0

0

Full-subtracter [ ~ Full-adder 1

l

(b) Full-Adder and Inverter Circuit

0 0 1 l 0 0 1 l

Difference

Borrow j Sum j B Fl F2 F3 F5 1 0 1 0 0 l 0 1

Table 2-21

1. The circuit of Module KL-33004 block b (Fig. 2-52) is equivalent to the adder/

subtracter circuit of Fig. 2-53.

2-68


r-----------------------------, I Y3 Y2 Y1 YO I I Y5 I I I I I I I I I I I I I I I I A3 A1 AO 80 I I F1 Y4 I I Cln

13 I I I I to I I I I F10 I I I I I I F8 I I I I " I I I I I I I I I I I 1 1 6 4 1 11 1 I 83 82 81 80 I I I I F3 U9 Cln

13 I I I I I I I I I I F7 Fe Fs F4 KL-33004 block b I L-----------------------------~

F1

U5:7483 06:7486

U5

Fig. 2-53 Adder/subtracter

2. Connect inputs X3-XO to DIP Switch 1.3-1 .0; Y3-YO to DIP 2.3-DIP2.0; Y5

to SWO.

Connect outputs F1 to L 1; F11-F8 to L5-L2. To execut~ > the subtract

operation, connect Y5 to "1" (orCin of U5=1). Follow the input sequences

below and record the output states in Table 2-22.

2-69


RESULTS

INPUT OUTPUT X3 X2 X1 XO Y Y2 Y1 YO F1 F11 F10 F9 F8 01000100 01000011 10000011 10000001 10011000 10010111 10100110 10100101 10111010 11111010

Table2-22

1. A half-~Gh~r:ctor is a half-adder with reversed minuend input.

2. A full-subtracter is a full-adder with reversed minuend input.

3. IC adder uses the "2's complement" method.

FAULT SIMULATION

When Y5="1 ", the circuit of Fig. 2-52 is supposed to execute the subtraction

operation. When Y5="1" the addition operation is supposed to bJexecuted. If Y5="0"

and an extra "1" is generated, whatcould be the problem(s)?

MULTIPLE CHOICE.Ql:JESTIONS

) 1. The differ~?mrr p .~~.eEm inputs A and B of a half subtracter is :

1. AB

2. AB

3. AB

( ) 2. Half-subtracter is simply a half-adder with :

1. INVERTER gate

2.AND gate

3. XOR gate

2-70


) 3. What is binary 11 01 in 1's complement?

1. 1100

2. 0010

3. 0001

) 4. Which method of complement should be used so that the result of "A-B" = "A+B"

1. 1's complement

2. 2's complement

3. 3's complement

( ) 5. What is binary 1110 in 2's complement?

1. 0010

2. 0001

3. 1110

) 6. If a half-adder circuit is to be used as a half-subtracter circuit, A is the

minuend and B is the subtrahend, which of the following statements is

true?

1. A mustbe reversed

2. B must be reversed

3. No modification required

) 7. Thejflpi.Jts of a full~subtractor includes :

1. borrow, minuend

2. subtrahend, borrow

3. Minuend, subtrahend, borrow

( ) 8. To convert a full-adder into a full-subtracter, which of these logic gates is

required?

1. AND gate

2. OR gate

3. XOR gate

2-71

Digital Logic LAB Manual KL-300 [Shorted]

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