Digital Logic Circuits
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CHAPTER 13 Digital Logic Circuits
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CHAPTER 13. Digital Logic Circuits. Figure 13.1. Voltage analog of internal combustion engine in-cylinder pressure. Figure 13.1. 13-1. Digital representation of an analog signal. Figure 13.2. Figure 13.2. 13-2. A binary signal. Figure 13.3. Figure 13.3. 13-3. Table 13.1. - PowerPoint PPT Presentation
Transcript of Digital Logic Circuits
CHAPTER
13
Digital Logic Circuits
Figure 13.1
13-1
Voltage analog of internal combustion engine in-cylinder pressure
Figure 13.1
Digital representation of an analog signal
Figure 13.2
Figure 13.2
13-2
A binary signalFigure 13.3
13-3
Figure 13.3
Table 13.1
Complements and Negative Numbers
Sign-magnitude convention
Example of Twos Complement Operation
( cf : 92 – 114 = - 22)
Digital Code Systems
Hexadecimal code
BCD code
Three-bit Gray code
Figure 13.11, Table
13.9
Logical addition and the OR gateFigure 13.11
13-4
Rules for logical addition (OR)Table 13.9
Figure 13.12, Table 13.10
Logical multiplication and the AND gateFigure 13.12
13-5
Rules for logical multiplication (AND)
Table 13.10
Figure 13.13
Example of logic function implementation with logic gatesFigure 13.13
13-6
Table 13.11
Figure 13.17
De Morgan’s lawsFigure 13.17
13-7
Figure 13.18
Sum-of-products and product-of-sums logic functionsFigure 13.18
13-8
Figure 13.21
Equivalence of NAND and NOR gates with AND and OR gatesFigure 13.21
13-9
Figure 13.23
Figure 13.23
13-10
Figure 13.24
NOR gate as an inverterFigure 13.24
13-11
Figure 13.27, 13.28
XOR gateFigure 13.27
13-12
Realization of an XOR gateFigure 13.28
Figure 13.29
Figure 13.30
Truth table and Karnaugh map representations of a logic functionFigure 13.30
13-13
Figure 13.31
Karnaugh map for a four-variable expressionFigure 13.31
13-14
One- and two-cell subcubes for the Karnaugh map of Figure 13.31
Figure 13.32
13-15
Figure 13.32
Figure 13.34
Karnaugh map for the function W · X · Y · Z + W · X · Y · Z + W · X · Y · Z + W · X · Y · ZFigure 13.34
13-16
Figure 13.46, 13.47
Figure 13.55
4-to-1 MUXFigure 13.55
13-17
Figure 13.56
Internal structure of the 4-to-1 MUXFigure 13.56
13-18
Figure 13.57, Table
13.13
Functional diagram of four-input MUXFigure 13.57
13-19
Table 13.13
Figure 13.58
Read-only memoryFigure 13.58
13-20
Figure 13.59
A 2-to-4 decoder
Internal organization of SRAM
An example of PLD (Programmable Logic Device; GAL16V8)
OLMC (Output Logic Macrocell):Register Mode
Simple Mode Logic Diagram
Figure 13.65
Programming Example by using a HDL (Hardware description language)
