Digital Logic and Circuits

8/11/2019 Digital Logic and Circuits

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ECE Ph.D. preliminary examDigital Logic and Circuits Problem Library


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1. You are given 16 request lines, REQ15 REQ0, where REQ15 is the highest priority request line and REQ0 isthe lowest priority one. You need to encode the number of the highest active priority request using four bits, R3 R0, where R3 is the MSB and R0 is the LSB. R3 R0 are active high.

a) Why can you use four bits to encode the number of the active request line? b) Design a circuit that will implement the encoding using two 74x148 chips and any external logic you need.Draw the logic diagram of your circuit.c) How can you disable your circuit?d) What is the output (R3 R0) of your circuit when the circuit is disabled? What is the output when there are noactive requests? If the outputs are the same for these two cases how can you add one more output to help distinguish between the two cases? Hint: Look at the x148 truth table for an idea.

The 74x148 logic symbol and its truth table are shown in Figure 1.

Inputs OutputsEI_L I0_L I1_L I2_L I3_L I4_L I5_L I6_L I7_L A2_L A1_L A0_L GS_L EO_L

1 x x x x x x x x 1 1 1 1 10 x x x x x x x 0 0 0 0 0 10 x x x x x x 0 1 0 0 1 0 10 x x x x x 0 1 1 0 1 0 0 10 x x x x 0 1 1 1 0 1 1 0 10 x x x 0 1 1 1 1 1 0 0 0 10 x x 0 1 1 1 1 1 1 0 1 0 10 x 0 1 1 1 1 1 1 1 1 0 0 10 0 1 1 1 1 1 1 1 1 1 1 0 10 1 1 1 1 1 1 1 1 1 1 1 1 0

Figure 1 74x148 logic symbol and truth table


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2. You have two 16-bit inputs, A and B, where A15 and B15 are the MSBs of the two inputs. You want tocompare the two inputs and wish to have active-high outputs corresponding to the following relationships betweenthe inputs: A>B, A


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3. Use 74x85 comparators to create one 12-bit comparator. You have to decide how many 74x85 devices touse, how to connect them, as well as whether to use external gates. If external gates are needed you can useany gate in any number. The logic symbol and the truth table for the 74x85 are given below. Give a word

explanation of the operation of your circuit.

Figure 3 Logic symbol for the 74x85 4-bit comparator

Cascading inputs Comparing inputs Outputs

AGTBIN ALTBIN AEQBIN A3,B3 A2,B2 A1,B1 A0,B0 AGTBOUT ALTBOUT AEQBOUT

x x x A3>B3 x x x 1 0 0

x x x A3B2 x x 1 0 0

x x x A3=B3 A2B1 x 1 0 0

x x x A3=B3 A2=B2 A1B1 1 0 0

x x x A3=B3 A2=B2 A1=B1 A0


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4. Design a 4-input 1-bit multiplexer with enable as a sum-of-products circuit. Your multiplexers logic symbol isshown in Figure 4. Its data inputs are I0, I1, I2 and I3. The multiplexer should implement the function table shownin Table 2. Hint: Dont use Karnaugh maps. Rearrange your circuit to implement the multiplexer using five 4-input

NAND gates and no other logic, assuming the available inputs are EN, S0, S0, S1, S1, I0, I1, I2 and I3. Explainhow the circuit works.

Figure 4 Multiplexer logic symbol

EN S1 S0 Y0 x x 01 0 0 I01 0 1 I11 1 0 I21 1 1 I3

Table 2 Multiplexer function table


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5. Construct a 16-to-1 multiplexer using your choice of the devices shown below and logic gates. You mayuse any quantity of the available devices. Each available device and its truth table is shown in a separaterow. There is no restriction on the type and number of logic gates you may use. Label your select lines as

S3, S2, S1, and S0, where S3 is the MSB. Label your inputs as I15 through I0, where I15 is the MSB.Provide a simple word description of how your circuit works.


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6. You are given a 6-bit bus signal. The six bits are A5, A4, A3, A2, A1, and A0, where A5 is the MSB and A0the LSB. Three devices are enabled or disabled based on the 6-bit binary number on the bus, as described in thefollowing truth table:

A5 A4 A3 A2 A1 A0 device 0 device 1 device 20 x x x x x disabled disabled disabledx 1 x x x x disabled disabled disabledx x 1 x x x disabled disabled disabled1 0 0 0 0 0 enabled disabled disabled1 0 0 0 0 1 disabled enabled disabled1 0 0 0 1 0 disabled disabled enabled1 0 0 0 1 1 disabled disabled disabled1 0 0 1 x x disabled disabled disabled

a) Does the truth table above cover all possible combinations for the 6 bits of the bus? Explain your answer. b) Assume that device 0, device 1, and device 2 are enabled by pulling their respective EN pins low. Design a

circuit that will implement the truth table above using one 74x138 and no external logic. Draw the logicdiagram of your circuit using the following logic symbol for the three devices, 0, 1, and 2:

EN

device x

x=1,2,3

The 74x138 is described by the following logic symbol and truth table:


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7. Party line circuit.a) Explain the circuit in Figure 2. You should describe the type of devices being used and the functionality of thecircuit.

Fi gure 5 Party-line circuit

b) Is the circuit in Figure 6 designed properly? Explain your answer.

Fi gure 6 Another party line circuit


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8. A D flip-flop with enable is described by the function table and logic symbol in Figure 7. What is thecharacteristic equation of this flip-flop?

Figure 7 Function table and logic symbol for D flip-flop with enable


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11. A combinational circuit is shown below.

a) Find the expression for f , without simplifying, as a sum of products. (5 points)

b) Create a Karnaugh map that describes the circuit (draw the map and find the 1-cells). Circle and label the product terms found in a) on the map. (5 points)c) Find the minimal sum-of-products expression for f using the Karnaugh map minimization. Show and explain all

your work. Draw a new Karnaugh map, and circle and label the product terms. (6 points)d) Find the minimal product-of-sums expression for f using the Karnaugh map minimization. Show and explain all

your work. One step will again be to draw a new Karnaugh map, and find product terms. Make sure you circleand label these product terms. (6 points)

e) Based on c) and d) what is the cheapest way to implement the circuit? Draw the circuit diagram of this circuitusing AND and OR logic gates. You can assume that the four signals ( a, b, c, d ) and their complements ( a, b,c, d ) are available (as in the figure below). (3 points)

c'ba

dcb

dc'a'

cb'a'

d

cba

d'

f


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12. A combinational circuit implements the following function:

caed cbaed baed cbad cbad cba f (1)

a) Create a Karnaugh map that shows the above product terms (draw the map and find the 1-cells). At this point donot simplify the expression. Circle and label the product terms of equation (1) on the map. (5 points)

b) Draw a new Karnaugh map and find the minimal sum-of-products expression for f using the Karnaugh mapminimization technique. Circle and label the product terms. (10 points)

c) Based b) draw the circuit diagram of this circuit using NAND logic gates. You can assume that the four signals(a, b, c, d, e ) and their complements ( a, b, c, d, e ) are available. (5 points)


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13. Using a Karnaugh map find the minimal sum-of-products expression for the following logic function:

)7,0()6,3,2( ,,,, Z Y X Z Y X d F


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14. For the Karnaugh map given in Figure 10, provide a minimum logic expression using groupings of maxterms.Clearly show the groupings that you make.

A BC D

d d

d

d

d

1

0d 0

0 0 0

0

1

1 1

00

00

01 11 10

01

11

10

Figure 10 Karnaugh map


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15. Expand the following Boolean expressions to both Canonical Sum-of-Products and Product-of-Sums forms.Indicate clearly which expression is SOP and which one is POS.

f y x y z


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16. Design a clocked synchronous state machine with the state/output table shown in Table 3, using D flip-flops.Use two state variables, Q1 Q0 (where Q1 is the MSB), with the state assignment A=00, B=01, C=11, D=10 (that isfor D your state variables will be Q1 = 1 and Q0 = 0). Draw and label the designed circuit. Explain the steps you

take.

Table 3 State/output table


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17. Given the excitation/output table in Table 4, derive the sum-of-products excitation equation for J2.

Table 4 Excitation/output table


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18. Draw a 2-input gate, with a data input and a control input, which passes complemented data when thecontrol input is logic zero. Write down the truth-table for this gate. What is the name of the gate you havedrawn?


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19. Prove the following equality:

W Y X X W Y X Y X )()(

Use the theorems of Boolean algebra listed below. At each step of your derivation state which theorem you areusing.


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20. Prove the following theorem:

T10: ( ) ( ) X Y X Y X

Use the following theorems in your proof:

Distributivity theorem (T8): ( ) ( ) X Y X Z X Y Z ;Complement theorem (T5): 0 X X ;Identity theorem (T1): 0 X X .

Show and explain your work.


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21. Prove the dual of theorem T10 from problem 20 using the duals of theorems T8, T5 and T1. Use thePrinciple of Duality.

Principle of Duality: Any theorem or identity in switching algebra remains true if 0 and 1 are swapped and

and + are swapped throughout.



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22. Prove the following theorem:

T1: X Y X Y X

Use the following theorems in your proof:

Distributivity theorem: X Y X Z X Y Z Complements theorem: 1 X X



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23. Prove DeMorgans theorems using finite induction.

DeMorgans theorems:

DMT: 1 2 1 2( )n n X X X X X X

DMT: 1 2 1 2( )n n X X X X X X


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24. Prove the following Shannons expansion theorem:

T15: 1 2 1 2 1 2( , , , ) (1, , , ) (0, , , )n n n F X X X X F X X X F X X



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25. Prove that a twos complement number can be converted to a representation with more bits by signextension . That is, given an n-bit twos complement number X , show that the m-bit twos complementrepresentation of X , where m>n , can be obtained by appending m-n copies of X s sign bit to the left of the n-

bit representation of X . Use the following formula in your derivation: M

m

M m

aa

a0

1

11

(Hint: Start by writing down the expressions for the values of X and Y . Continue by rewriting the value of X as afunction of Y (this may take a few steps). Finally, look at when the equation X = Y will hold.)


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26. All the numbers below are unsigned. Perform the required conversions showing all your work.

a) (1 point) 0.510 = ?2

b) (2 points) 3410 = ?2

c) (2 points) F1.2 16 = ?10 (NOTE: 1/16 = 0.0625)

d) (2 points) 100.11 2 = ?16 ( Hint: remember the trick to convert between base-2 and base-16 numbers. Youhave to group a certain number of the base-2 numbers )


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27. The figure below shows four 27256 ROM devices connected to a three-state bus. The devices have chip-select (CS) inputs as well as output-enable (OE) inputs, both of which must be asserted to enable theoutputs.

a) (5 points) How many 8-bit words (bytes) can each 27256 hold? (We know that the devices hold 8-bit words bylooking at the number of data outputs 8.)

b) (5 points) What is the size of the memory space of the microprocessor? ( Hint: how many address lines arethere? )

c) (10 points) The memory map of the circuit is shown in Figure 13 on the following page. The memory map hasto indicate which addresses will access a given device. Complete the memory map by indicating where in thismemory space the four ROM devices (U2, U3, U4, and U5) are located. On the lines indicate the first addressthat will access a given device. Use hexadecimal numbers. To determine the location of the ROM devices inthe memory map look at what address lines have to be active for a given ROM to be selected (use the truth tablefor the 74x139 in Figure 12 ). Assume that A19 is the MSB of the address bus. Two addresses are shown inFigure 13 : 00000 16, which is accessed when all of the microprocessors address lines are 0, and FFFFF 16, whichis accessed when all address lines are 1. Note that FFFFF 16 is the last location in the memory space and that itaccesses U5.

Figure 11 Address decoding and ROM enabling in a microprocessor system


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Figure 12 74x139 logic symbol and truth table

U5

U4

U3

U2

0000016

FFFFF16

Figure 13 Memory map


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28. You are a Mayan first grade teacher. You are teaching your students addition. You assign the followingequation as a homework assignment.

+ = ?

One of your students submits the following work.

+ =

Is the students solution for the equation correct? If it is not, make the necessary correction(s). Explain your answer and include the decimal version of the solution for the equation.

Hint: The Maya used a posit ional number system. The radix of their system was 20. They denoted numbers

using dots and bars. Each dot had a value of one and each bar had a value of five. The Maya also had a symbol for zero: . The Maya wrote numbers in columns. The bottom position in a column was the least significant position.


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29. Figure 14 shows the logic symbol and state table for the 74x163 4-bit binary counter. Using this counter and any gates of your choosing design a modulo-8 counter with the counting sequence5,6,7,8,9,10,11,12,5,6, Explain the operation of your circuit in words.

Figure 14 74x163 logic symbol and state table


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30. An n-bit shift register with the complement of the serial output fed back into the serial input is a counter with 2n states and is called a twisted-ring, Moebius, or Johnson counter.

a) Using a 74x194 universal shift register and any number of external gates implement a simple 4-bit Johnsoncounter. Your counter should not be self-correcting. Give a word explanation of the operation of your circuit. b) Include a timing diagram showing the CLK, CLR, QD, QC, QB, and QA lines. Assume that the contents of the

74x194 are cleared by pulling the CLR line low and then setting it high at the beginning of your timing diagram.c) Design a 4-bit self-correcting Johnson counter. In order to be self-correcting your circuit should load 0001 as

the next state whenever the current state is 0xx0. Give a word explanation of the operation of your circuit.d) Draw the state diagram of the circuit to show that the circuit is indeed self-correcting. Give a short word

explanation of the state diagram and why it proves that the circuit is self-correcting. Note that there are 2 4 = 16states in the state diagram.

Figure 15 Logic symbol for the 74x194 4-bit universal shift register

Table 5 Function table for the 74x194 4-bit universal shift register


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31. The circuit shown in Figure 16 is a 3-bit counter with outputs Q1, Q2, and Q3. What is the counter outputsequence assuming an initial system clear? Provide your answer in .

CLK

Q3

Q3

D3

CLR

Q2

Q2

D2

CLR

Q1

Q1

D1

CLR

SystemClear

CountOutput

MSB

LSB

Figure 16 3-bit counter circuit

Clock Pulse Counter Output

Q3 Q2 Q10 0 0 012345678910

Table 6 Fill in the table with the counter output sequence


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32. For the circuit given in question 31 complete the timing diagram in Figure 17 for a single complete counter sequence. Cover as many clock cycles as necessary for the counter sequence to repeat.

CLK

Q 1

Q 2

Q 3

Figure 17 Complete the timing diagram


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33. Obtain the timing diagram for the sequential circuit shown in Figure 18 for at least six clock cycles. Assume aninitial condition state of Q1Q2=00 for the flip-flop pair. The characteristic equation of the edge-triggered J-K flip-flops used in the circuit is Q* = JQ + KQ.

CLK

J

K

Q1

Q1

J

K

Q2

Q2

CLK

Q1

Q2

Figure 18 Circuit diagram (top) and timing diagram to be filled in (bottom)


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35. Given the block diagram in Figure 19, draw the connections necessary to implement the shift right function anda parallel load of data. Be sure to label the four blank boxes with the proper device name.

Clock

Q3

Q3

D3 Q2

Q2

D2 Q1

Q1

D1Q4

Q4

D4

Input 0Input 1Input 2Input 3

Shift Input

Loador

Shift Right

ShiftOutput

Figure 19 Complete the block diagram to implement the shift right and parallel load functions


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36. One method to derive an n-bit Gray code is to write down the n-bit binary code and follow the steps below:

a) The bits of an n-bit binary or Gray-code code word are numbered from right to left, from 0 to n - 1.

b) Bit i of a Gray-code code word is 0 if bits i and i+1 of the corresponding binary code word are the same, else biti is 1. (When i + 1 = n , bit n of the binary code word is considered to be 0.)

Using this method complete Table 7.

Decimal number Binary code Gray code0 0001 0012 0103 0114 100

5 1016 1107 111

Table 7 Gray code

Digital Logic and Circuits

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