Jan M. Rabaey Digital Integrated Circuits A Design Perspective.
Digital Integrated Circuits A Design Perspective
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Transcript of Digital Integrated Circuits A Design Perspective
© Digital Integrated Circuits2nd Interconnect
Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective
Coping withCoping withInterconnectInterconnect
Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolic
December 15, 2002
© Digital Integrated Circuits2nd Interconnect
Impact of Interconnect ParasiticsImpact of Interconnect Parasitics
• Reduce Robustness
• Affect Performance• Increase delay• Increase power dissipation
Classes of Parasitics
• Capacitive
• Resistive
• Inductive
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INTERCONNECTINTERCONNECT
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Capacitive Cross TalkCapacitive Cross Talk
X
YVX
CXY
CY
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Capacitive Cross TalkCapacitive Cross TalkDynamic NodeDynamic Node
3 x 1 m overlap: 0.19 V disturbance
CY
CXY
VDD
PDN
CLK
CLK
In1
In2
In3
Y
X
2.5 V
0 V
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Capacitive Cross TalkCapacitive Cross TalkDriven NodeDriven Node
XY = RY(CXY+CY)
Keep time-constant smaller than rise time
0
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
010.80.6
t (nsec)
0.40.2
X
YVXRY
CXY
CY
tr↑
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Dealing with Capacitive Cross Dealing with Capacitive Cross TalkTalk
Avoid floating nodes Protect sensitive nodes Make rise and fall times as large as possible Differential signaling Do not run wires together for a long distance Use shielding wires Use shielding layers
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ShieldingShielding
GND
GND
Shieldingwire
Substrate (GND )
Shieldinglayer
VDD
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Cross Talk and PerformanceCross Talk and Performance
Cc
- When neighboring lines switch in opposite direction of victim line, delay increases
DELAY DEPENDENT UPON ACTIVITY IN NEIGHBORING WIRES
Miller EffectMiller Effect
- Both terminals of capacitor are switched in opposite directions (0 Vdd, Vdd 0)
- Effective voltage is doubled and additional charge is needed (from Q=CV)
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Impact of Cross Talk on Delay Impact of Cross Talk on Delay
r is ratio between capacitance to GND and to neighbor
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Structured Predictable InterconnectStructured Predictable Interconnect
S
S SV V S
G
S
SV
G
VS
S SV V S
G
S
SV
G
VExample: Dense Wire Fabric ([Sunil Kathri])Trade-off:• Cross-coupling capacitance 40x lower, 2% delay variation• Increase in area and overall capacitance Also: FPGAs, VPGAs
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Interconnect ProjectionsInterconnect ProjectionsLow-k dielectricsLow-k dielectrics
Both delay and power are reduced by dropping interconnect capacitance
Types of low-k materials include: inorganic (SiO2), organic (Polyimides) and aerogels (ultra low-k)
The numbers below are on the conservative side of the NRTS roadmap
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Encoding Data Avoids Worst-CaseEncoding Data Avoids Worst-CaseConditionsConditions
Encoder
Decoder
Bus
In
Out
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Driving Large CapacitancesDriving Large Capacitances
V in Vout
CL
VDD
• Transistor Sizing• Cascaded Buffers
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Using Cascaded BuffersUsing Cascaded Buffers
CL = 20 pF
In Out
1 2 N
0.25 m processCin = 2.5 fFtp0 = 30 ps
F = CL/Cin = 8000fopt = 3.6 N = 7tp = 0.76 ns
(See Chapter 5)
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Output Driver DesignOutput Driver Design
Trade off Performance for Area and Energy
Given tpmax find N and f Area
Energy
minminmin12
1
1
1
1...1 A
f
FA
f
fAfffA
NN
driver
22212
11
1...1 DD
LDDiDDi
Ndriver V
f
CVC
f
FVCfffE
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Delay as a Function of F and NDelay as a Function of F and N
101 3 5 7
Number of buffer stages N
9 11
10,000
1000
100
F = 100F = 1000
F = 10,000t p
/tp
0
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Output Driver DesignOutput Driver Design
Transistor Sizes for optimally-sized cascaded buffer tp = 0.76 ns
Transistor Sizes of redesigned cascaded buffer tp = 1.8 ns
0.25 m process, CL = 20 pF
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How to Design Large TransistorsHow to Design Large Transistors
G(ate)
S(ource)
D(rain)
Multiple
Contacts
small transistors in parallel
Reduces diffusion capacitanceReduces gate resistance
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Bonding Pad DesignBonding Pad DesignBonding Pad
Out
InVDD GND
100 m
GND
Out
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ESD ProtectionESD Protection
When a chip is connected to a board, there is unknown (potentially large) static voltage difference
Equalizing potentials requires (large) charge flow through the pads
Diodes sink this charge into the substrate – need guard rings to pick it up.
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ESD ProtectionESD Protection
Diode
PAD
VDD
R D1
D2
X
C
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Chip PackagingChip Packaging
ChipL
L ´
Bonding wire
Mountingcavity
Leadframe
Pin
•Bond wires (~25m) are used to connect the package to the chip
• Pads are arranged in a frame around the chip
• Pads are relatively large (~100m in 0.25m technology),with large pitch (100m)
•Many chips areas are ‘pad limited’
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Pad FramePad Frame
Layout Die Photo
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Chip PackagingChip Packaging An alternative is ‘flip-chip’:
Pads are distributed around the chip The soldering balls are placed on pads The chip is ‘flipped’ onto the package Can have many more pads
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Tristate BuffersTristate Buffers
InEn
En
VDD
Out
Out = In.En + Z.En
VDD
In
En
En
Out
Increased output drive
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Reducing the swingReducing the swing
tpHL = CL Vswing/2
Iav
Reducing the swing potentially yields linear reduction in delay Also results in reduction in power dissipation Delay penalty is paid by the receiver Requires use of “sense amplifier” to restore signal level Frequently designed differentially (e.g. LVDS)
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Single-Ended Static Driver and Single-Ended Static Driver and ReceiverReceiver
CL
VDD
VDD VDD
driver receiver
VDDL
VDDLIn
OutOut
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Dynamic Reduced Swing NetworkDynamic Reduced Swing Network
fIn2.fIn1.
f M2
M1 M3
M4
Cbus Cout
Bus Out
VDD VDD
f
Vbus
Vasym
Vsym
2 4 6time (ns)
8 10 120
0.5
1
1.5
2
2.5
0
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INTERCONNECTINTERCONNECT
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Impact of ResistanceImpact of Resistance
We have already learned how to drive RC interconnect
Impact of resistance is commonly seen in power supply distribution: IR drop Voltage variations
Power supply is distributed to minimize the IR drop and the change in current due to switching of gates
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RI Introduced NoiseRI Introduced Noise
M1
X
I
R9
RDV
fpre
DV
VDD
VDD 2 DV9
I
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ASP DAC 2000
Power Dissipation TrendsPower Dissipation Trends
Power consumption is increasingPower consumption is increasing Better cooling technology neededBetter cooling technology needed
Supply current is increasing faster!Supply current is increasing faster!
OnOn--chip signal integrity will be a major chip signal integrity will be a major issueissue
Power and current distribution are criticalPower and current distribution are critical
Opportunities to slow power growthOpportunities to slow power growth Accelerate Accelerate VddVdd scalingscaling
Low κ dielectrics & thinner (Cu) Low κ dielectrics & thinner (Cu) interconnectinterconnect
SOI circuit innovations SOI circuit innovations
Clock system designClock system design
micromicro--architecturearchitecture
Power Dissipation
020406080
100120140160
EV4 EV5 EV6 EV7 EV8
Po
we
r (W
)
0
0.5
1
1.5
2
2.5
3
3.5
Vol
tage
(V
)
Supply Current
0
20
40
60
80
100
120
140
EV4 EV5 EV6 EV7 EV8
Curr
ent (
A)
0
0.5
1
1.5
2
2.5
3
3.5
Vo
ltag
e (
V)
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Resistance and the Power Resistance and the Power Distribution ProblemDistribution Problem
Source: Cadence
• Requires fast and accurate peak current predictionRequires fast and accurate peak current prediction• Heavily influenced by packaging technologyHeavily influenced by packaging technology
BeforeBefore AfterAfter
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Power DistributionPower Distribution
Low-level distribution is in Metal 1 Power has to be ‘strapped’ in higher layers of
metal. The spacing is set by IR drop,
electromigration, inductive effects Always use multiple contacts on straps
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Power and Ground DistributionPower and Ground Distribution
GND
VDD
Logic
GND
VDD
Logic
GND
VDD
(a) Finger-shaped network (b) Network with multiple supply pins
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3 Metal Layer Approach (EV4)3 Metal Layer Approach (EV4)3rd “coarse and thick” metal layer added to the
technology for EV4 designPower supplied from two sides of the die via 3rd metal layer
2nd metal layer used to form power grid
90% of 3rd metal layer used for power/clock routing
Metal 3
Metal 2
Metal 1
Courtesy Compaq
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4 Metal Layers Approach (EV5)4 Metal Layers Approach (EV5)4th “coarse and thick” metal layer added to the
technology for EV5 designPower supplied from four sides of the die
Grid strapping done all in coarse metal
90% of 3rd and 4th metals used for power/clock routing
Metal 3
Metal 2
Metal 1
Metal 4
Courtesy Compaq
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2 reference plane metal layers added to thetechnology for EV6 designSolid planes dedicated to Vdd/Vss
Significantly lowers resistance of gridLowers on-chip inductance
6 Metal Layer Approach – EV66 Metal Layer Approach – EV6
Metal 4
Metal 2Metal 1
RP2/Vdd
RP1/Vss
Metal 3
Courtesy Compaq
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Electromigration (1)Electromigration (1)
Limits dc-current to 1 mA/m
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Electromigration (2)Electromigration (2)
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Resistivity and PerformanceResistivity and Performance
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50
0.5
1
1.5
2
2.5
time (nsec)
volta
ge
(V
)
x= L/10
x = L/4
x = L/2
x= L
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50
0.5
1
1.5
2
2.5
time (nsec)
volta
ge
(V
)
x= L/10
x = L/4
x = L/2
x= L
Diffused signal Diffused signal propagationpropagation
Delay ~ LDelay ~ L22
CN-1 CNC2
R1 R2
C1
Tr
Vin
RN-1 RN
The distributed rc-lineThe distributed rc-line
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The Global Wire ProblemThe Global Wire Problem
Challenges No further improvements to be expected after the
introduction of Copper (superconducting, optical?) Design solutions
Use of fat wires Insert repeaters — but might become prohibitive (power, area) Efficient chip floorplanning
Towards “communication-based” design How to deal with latency? Is synchronicity an absolute necessity?
outwwdoutdwwd CRCRCRCRT 693.0377.0
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Interconnect Projections: CopperInterconnect Projections: Copper
Copper is planned in full sub-0.25 m process flows and large-scale designs (IBM, Motorola, IEDM97)
With cladding and other effects, Cu ~ 2.2 -cm vs. 3.5 for Al(Cu) 40% reduction in resistance
Electromigration improvement; 100X longer lifetime (IBM, IEDM97) Electromigration is a limiting factor
beyond 0.18 m if Al is used (HP, IEDM95)
Vias
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Interconnect:Interconnect:# of Wiring Layers# of Wiring Layers
# of metal layers is steadily increasing due to:
• Increasing die size and device count: we need more wires and longer wires to connect everything
• Rising need for a hierarchical wiring network; local wires with high density and global wires with low RC
substrate
poly
M1
M2
M3
M4
M5
M6
Tins
H
WS
= 2.2 -cm
0.25 m wiring stack
Minimum Widths (Relative)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
M5
M4
M3
M2
M1
Poly
Minimum Spacing (Relative)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
M5
M4
M3
M2
M1
Poly
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Diagonal WiringDiagonal Wiring
y
x
destination
Manhattan
source
diagonal
• 20+% Interconnect length reduction• Clock speed Signal integrity Power integrity • 15+% Smaller chips plus 30+% via reduction
Courtesy Cadence X-initiative
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Using BypassesUsing Bypasses
DriverPolysilicon word line
Polysilicon word line
Metal word line
Metal bypass
Driving a word line from both sides
Using a metal bypass
WL
WL K cells
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Reducing RC-delayReducing RC-delay
Repeater
(chapter 5)
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Repeater Insertion (Revisited)Repeater Insertion (Revisited)
Taking the repeater loading into account
For a given technology and a given interconnect layer, there exists For a given technology and a given interconnect layer, there exists an optimal length of the wire segments between repeaters. The an optimal length of the wire segments between repeaters. The delay of these wire segments is delay of these wire segments is independent of the routing layer!independent of the routing layer!
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INTERCONNECTINTERCONNECT
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L di/dtL di/dt
Impact of inductance on supply voltages:• Change in current induces a change in voltage• Longer supply lines have larger LCL
V’DD
VDD
L i(t)
VoutVin
GND’
L
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L di/dt: SimulationL di/dt: Simulation
0 0.5 1 1.5 2
x 10-9
0
0.5
1
1.5
2
2.5V
out (
V)
0 0.5 1 1.5 2
x 10-9
0
0.02
0.04
i L (A
)
0 0.5 1 1.5 2
x 10-9
0
0.5
1
VL (
V)
time (nsec)
0 0.5 1 1.5 2
x 10-9
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2
x 10-9
0
0.02
0.04
0 0.5 1 1.5 2
x 10-9
0
0.5
1
time (nsec)
Input rise/fall time: 50 psec Input rise/fall time: 800 psec
decoupled
Without inductorsWith inductors
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Dealing with Ldi/dtDealing with Ldi/dt
Separate power pins for I/O pads and chip core. Multiple power and ground pins. Careful selection of the positions of the power
and ground pins on the package. Increase the rise and fall times of the off-chip
signals to the maximum extent allowable. Schedule current-consuming transitions. Use advanced packaging technologies. Add decoupling capacitances on the board. Add decoupling capacitances on the chip.
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Choosing the Right PinChoosing the Right Pin
ChipL
L ´
Bonding wire
Mountingcavity
Leadframe
Pin
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Decoupling CapacitorsDecoupling Capacitors
SUPPLY
Boardwiring
Bondingwire
Decouplingcapacitor
CHIPCd
1
2
Decoupling capacitors are added: • on the board (right under the supply pins)• on the chip (under the supply straps, near large buffers)
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De-coupling Capacitor RatiosDe-coupling Capacitor Ratios
EV4 total effective switching capacitance = 12.5nF 128nF of de-coupling capacitance de-coupling/switching capacitance ~ 10x
EV5 13.9nF of switching capacitance 160nF of de-coupling capacitance
EV6 34nF of effective switching capacitance 320nF of de-coupling capacitance -- not enough!
Source: B. Herrick (Compaq)
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EV6 De-coupling CapacitanceEV6 De-coupling CapacitanceDesign for Idd= 25 A @ Vdd = 2.2 V, f = 600
MHz 0.32-µF of on-chip de-coupling capacitance was
added– Under major busses and around major gridded clock
drivers– Occupies 15-20% of die area
1-µF 2-cm2 Wirebond Attached Chip Capacitor (WACC) significantly increases “Near-Chip” de-coupling
– 160 Vdd/Vss bondwire pairs on the WACC minimize inductance
Source: B. Herrick (Compaq)
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EV6 WACCEV6 WACC
587 IPGA
MicroprocessorWACC
Heat Slug
389 Signal - 198 VDD/VSS Pins389 Signal Bondwires
395 VDD/VSS Bondwires
320 VDD/VSS Bondwires
Source: B. Herrick (Compaq)
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The Transmission LineThe Transmission Line
The Wave Equation
V in Voutr
g c
r r x
g c
r
g c g c
l l l l
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Design Rules of ThumbDesign Rules of Thumb
Transmission line effects should be considered when the rise or fall time of the input signal (tr, tf) is smaller than the time-of-flight of the transmission line (tflight).
tr (tf) << 2.5 tflight Transmission line effects should only be considered when the
total resistance of the wire is limited:R < 5 Z0
The transmission line is considered lossless when the total resistance is substantially smaller than the characteristic impedance,
R < Z0/2
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Should we be worried?Should we be worried?
Transmission line effects cause overshooting and non-monotonic behavior
Clock signals in 400 MHz IBM Microprocessor(measured using e-beam prober) [Restle98]
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Matched TerminationMatched Termination
Z 0 Z L
Z0
Series Source Termination
Z 0 Z 0
Z S
Parallel Destination Termination
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Segmented Matched Line DriverSegmented Matched Line Driver
Z0
c1 c2
s0 s1 s2 sn
cn
ZL
GND
VDD
In
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Parallel Termination─Parallel Termination─Transistors as ResistorsTransistors as Resistors
0.5 1
PMOS with-1V bias
NMOS-PMOS
PMOS only
NMOS only
1.5VR (Volt)
2 2.50
1.11
1.21.31.41.51.61.71.81.9
2
Out
M r
Vdd
Out
M r
Vdd
Vbb
Out
M rp M rn
Vdd
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Output Driver with Varying Output Driver with Varying TerminationsTerminations
1 2 3 4
time (sec)
Revised design with matched driver impedance
Vs
Vd
Vin
5 6 7 80
1
0
1
2
3
4
1 2 3 4
Initial design
Vs
Vd
Vin
5 6 7 80
1
0
1
2
3
4
V in
L= 2.5 nH
VDD
V s V d
V DD
ClampingDiodes
CL= 5 pF CL
L = 2.5 nH
L = 2.5 nH Z 0 = 50
275
120
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The “Network-on-a-Chip”The “Network-on-a-Chip”
EmbeddedProcessorsEmbeddedProcessors
MemorySub-system
MemorySub-system
AccelatorsAccelatorsConfigurableAcceleratorsConfigurableAccelerators
PeripheralsPeripherals
Interconnect Backplane