Digital Integrated Circuits A Design Perspective
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Transcript of Digital Integrated Circuits A Design Perspective
© Digital Integrated Circuits2nd Inverter
Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective
The InverterThe Inverter
Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolic
July 30, 2002
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The CMOS Inverter: A First GlanceThe CMOS Inverter: A First Glance
V in Vout
CL
VDD
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CMOS InverterCMOS Inverter
Polysilicon
In Out
VDD
GND
PMOS 2
Metal 1
NMOS
OutIn
VDD
PMOS
NMOS
Contacts
N Well
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Two InvertersTwo Inverters
Connect in Metal
Share power and ground
Abut cells
VDD
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CMOS InverterCMOS InverterFirst-Order DC AnalysisFirst-Order DC Analysis
VOL = 0VOH = VDD
VM = f(Rn, Rp)
VDD VDD
Vin = VDD Vin = 0
VoutVout
Rn
Rp
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CMOS Inverter: Transient ResponseCMOS Inverter: Transient Response
tpHL = f(Ron.CL)
= 0.69 RonCL
VoutVout
Rn
Rp
VDDVDD
Vin= VDDVin= 0
(a) Low-to-high (b) High-to-low
CLCL
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Voltage TransferVoltage TransferCharacteristicCharacteristic
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PMOS Load LinesPMOS Load Lines
VDSp
IDp
VGSp=-2.5
VGSp=-1VDSp
IDnVin=0
Vin=1.5
Vout
IDnVin=0
Vin=1.5
Vin = VDD+VGSpIDn = - IDp
Vout = VDD+VDSp
Vout
IDnVin = VDD+VGSpIDn = - IDp
Vout = VDD+VDSp
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CMOS Inverter Load CharacteristicsCMOS Inverter Load Characteristics
IDn
Vout
Vin = 2.5
Vin = 2
Vin = 1.5
Vin = 0
Vin = 0.5
Vin = 1
NMOS
Vin = 0
Vin = 0.5
Vin = 1Vin = 1.5
Vin = 2
Vin = 2.5
Vin = 1Vin = 1.5
PMOS
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CMOS Inverter VTCCMOS Inverter VTC
Vout
Vin0.5 1 1.5 2 2 .5
0.5
11.
52
2.5
NMOS resPMOS off
NMOS satPMOS sat
NMOS offPMOS res
NMOS satPMOS res
NMOS resPMOS sat
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Switching Threshold as a function Switching Threshold as a function of Transistor Ratioof Transistor Ratio
n
satnDSATn
LV
satnoxnDSATnoxnn
nDSATnn CWVC
L
WVk
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Switching Threshold as a function of Switching Threshold as a function of Transistor RatioTransistor Ratio
100
101
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
MV
(V
)
Wp
/Wn
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Determining VDetermining VIHIH and V and VILIL
VOH
VOL
Vin
Vout
VM
VIL VIH
A simplified approach
IL IH
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Inverter GainInverter Gain
0 0.5 1 1.5 2 2.5-18
-16
-14
-12
-10
-8
-6
-4
-2
0
Vin
(V)
gain
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Simulated VTCSimulated VTC
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5
Vin
(V)
Vou
t(V)
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Impact of Process VariationsImpact of Process Variations
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5
Vin (V)
Vo
ut(V
)
Good PMOSBad NMOS
Good NMOSBad PMOS
Nominal
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Propagation DelayPropagation Delay
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CMOS Inverter Propagation DelayCMOS Inverter Propagation DelayApproach 1Approach 1
VDD
Vout
Vin = VDD
CLIav
tpHL = CL Vswing/2
Iav
CL
kn VDD
~
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CMOS Inverter Propagation DelayCMOS Inverter Propagation DelayApproach 2Approach 2
VDD
Vout
Vin = VDD
Ron
CL
tpHL = f(Ron.CL)
= 0.69 RonCL
t
Vout
VDD
RonCL
1
0.5
ln(0.5)
0.36
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CMOS InvertersCMOS Inverters
Polysilicon
InOut
Metal1
VDD
GND
PMOS
NMOS
1.2 m=2
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0 0.5 1 1.5 2 2.5
x 10-10
-0.5
0
0.5
1
1.5
2
2.5
3
t (sec)
Vou
t(V)
Transient ResponseTransient Response
tp = 0.69 CL (Reqn+Reqp)/2
?
tpLHtpHL
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Design for PerformanceDesign for Performance
Keep capacitances small Increase transistor sizes
watch out for self-loading!
Increase VDD (????)
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Delay as a function of VDelay as a function of VDDDD
0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.41
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VDD
(V)
t p(nor
mal
ized
)
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2 4 6 8 10 12 142
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8x 10
-11
S
t p(sec
)
Device SizingDevice Sizing
(for fixed load)
Self-loading effect:Intrinsic capacitancesdominate
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1 1.5 2 2.5 3 3.5 4 4.5 53
3.5
4
4.5
5x 10
-11
t p(sec
)
NMOS/PMOS ratioNMOS/PMOS ratio
tpLH tpHL
tp = Wp/Wn
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Impact of Rise Time on DelayImpact of Rise Time on Delayt p
HL(n
sec
)0.35
0.3
0.25
0.2
0.15
trise (nsec)10.80.60.40.20
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Inverter SizingInverter Sizing
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Inverter ChainInverter Chain
CL
If CL is given:- How many stages are needed to minimize the delay?- How to size the inverters?
May need some additional constraints.
In Out
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Inverter DelayInverter Delay
• Minimum length devices, L=0.25m• Assume that for WP = 2WN =2W
• same pull-up and pull-down currents• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays• Analyze as an RC network
WNunit
Nunit
unit
PunitP RR
W
WR
W
WRR
11
tpHL = (ln 2) RNCL tpLH = (ln 2) RPCLDelay (D):
2W
W
unitunit
gin CW
WC 3Load for the next stage:
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Inverter with LoadInverter with Load
Load (CL)
Delay
Assumptions: no load -> zero delay
CL
tp = k RWCL
RW
RW
Wunit = 1
k is a constant, equal to 0.69
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Inverter with LoadInverter with Load
Load
Delay
Cint CL
Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)= Delay (Internal) + Delay (Load)
CN = Cunit
CP = 2Cunit
2W
W
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Delay FormulaDelay Formula
/1/1
~
0int ftCCCkRt
CCRDelay
pintLWp
LintW
Cint = Cgin with 1f = CL/Cgin - effective fanoutR = Runit/W ; Cint =WCunit
tp0 = 0.69RunitCunit
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Apply to Inverter ChainApply to Inverter Chain
CL
In Out
1 2 N
tp = tp1 + tp2 + …+ tpN
jgin
jginunitunitpj C
CCRt
,
1,1~
LNgin
N
i jgin
jginp
N
jjpp CC
C
Cttt
1,
1 ,
1,0
1, ,1
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Optimal Tapering for Given Optimal Tapering for Given NN
Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N
Minimize the delay, find N - 1 partial derivatives
Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1
Size of each stage is the geometric mean of two neighbors
- each stage has the same effective fanout (Cout/Cin)- each stage has the same delay
1,1,, jginjginjgin CCC
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Optimum Delay and Number of Optimum Delay and Number of StagesStages
1,/ ginLN CCFf
When each stage is sized by f and has same eff. fanout f:
N Ff
/10N
pp FNtt
Minimum path delay
Effective fanout of each stage:
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ExampleExample
CL= 8 C1
In Out
C11 f f2
283 f
CL/C1 has to be evenly distributed across N = 3 stages:
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Optimum Number of StagesOptimum Number of Stages
For a given load, CL and given input capacitance Cin
Find optimal sizing f
ff
fFtFNtt pN
pp lnln
ln1/ 0/1
0
0ln
1lnln2
0
f
ffFt
f
t pp
For = 0, f = e, N = lnF
f
FNCfCFC in
NinL ln
ln with
ff 1exp
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Optimum Effective Fanout Optimum Effective Fanout ffOptimum f for given process defined by
ff 1exp
fopt = 3.6for =1
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Impact of Self-Loading on Impact of Self-Loading on tptp
1.0 3.0 5.0 7.0u
0.0
20.0
40.0
60.0
u/l
n(u
)
x=10
x=100
x=1000
x=10,000
No Self-Loading, =0 With Self-Loading =1
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Normalized delay function of Normalized delay function of FF
/10N
pp FNtt
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Buffer DesignBuffer Design
1
1
1
1
8
64
64
64
64
4
2.8 8
16
22.6
N f tp
1 64 65
2 8 18
3 4 15
4 2.8 15.3
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Power DissipationPower Dissipation
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Where Does Power Go in CMOS?Where Does Power Go in CMOS?
• Dynamic Power Consumption
• Short Circuit Currents
• Leakage
Charging and Discharging Capacitors
Short Circuit Path between Supply Rails during Switching
Leaking diodes and transistors
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Dynamic Power DissipationDynamic Power Dissipation
Energy/transition = CL * Vdd2
Power = Energy/transition * f = CL * Vdd2 * f
Need to reduce CL, Vdd, and f to reduce power.
Vin Vout
CL
Vdd
Not a function of transistor sizes!
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Modification for Circuits with Reduced Swing
CL
Vdd
Vdd
Vdd -Vt
E0 1 CL Vdd Vdd Vt– =
Can exploit reduced swing to lower power(e.g., reduced bit-line swing in memory)
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Node Transition Activity and PowerNode Transition Activity and PowerConsider switching a CMOS gate for N clock cycles
EN CL Vdd 2 n N =
n(N): the number of 0->1 transition in N clock cycles
EN : the energy consumed for N clock cycles
Pavg N lim
ENN
-------- fclk= n N
N------------
N lim
C
LVdd
2fclk
=
0 1
n N N
------------N
lim=
Pavg = 0 1 C
LVdd
2 fclk
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Transistor Sizing for Minimum Transistor Sizing for Minimum EnergyEnergy
Goal: Minimize Energy of whole circuit Design parameters: f and VDD
tp tpref of circuit with f=1 and VDD =Vref
1Cg1
In
fCext
Out
TEDD
DDp
pp
VV
Vt
f
Fftt
0
0 11
(VTE=VT+VDSAT/2)
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Transistor Sizing (2)Transistor Sizing (2) Performance Constraint (=1)
Energy for single Transition
13
2
3
2
0
0
F
fF
f
VV
VV
V
V
F
fF
f
t
t
t
t
TEDD
TEref
ref
DD
refp
p
pref
p
F
Ff
V
V
E
E
FfCVE
ref
DD
ref
gDD
4
22
112
12
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1 2 3 4 5 6 70
0.5
1
1.5
2
2.5
3
3.5
4
f
vdd
(V
)
1 2 3 4 5 6 70
0.5
1
1.5
f
no
rma
lize
d e
ne
rgy
Transistor Sizing (3)Transistor Sizing (3)
F=1
2
5
10
20
VDD=f(f) E/Eref=f(f)
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Short Circuit CurrentsShort Circuit Currents
Vin Vout
CL
Vdd
I VD
D (m
A)
0.15
0.10
0.05
Vin (V)5.04.03.02.01.00.0
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How to keep Short-Circuit Currents Low?How to keep Short-Circuit Currents Low?
Short circuit current goes to zero if tfall >> trise,but can’t do this for cascade logic, so ...
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Minimizing Short-Circuit PowerMinimizing Short-Circuit Power
0 1 2 3 4 50
1
2
3
4
5
6
7
8
tsin
/tsout
Pno
rm
Vdd =1.5
Vdd =2.5
Vdd =3.3
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LeakageLeakage
Vout
Vdd
Sub-ThresholdCurrent
Drain JunctionLeakage
Sub-Threshold Current Dominant FactorSub-threshold current one of most compelling issuesin low-energy circuit design!
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Reverse-Biased Diode LeakageReverse-Biased Diode Leakage
Np+ p+
Reverse Leakage Current
+
-Vdd
GATE
IDL = JS A
JS = 1-5pA/m2 for a 1.2m CMOS technology
Js double with every 9oC increase in temperature
JS = 10-100 pA/m2 at 25 deg C for 0.25m CMOSJS doubles for every 9 deg C!
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Subthreshold Leakage ComponentSubthreshold Leakage Component
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Static Power ConsumptionStatic Power Consumption
Vin=5V
Vout
CL
Vdd
Istat
Pstat = P(In=1).Vdd . Istat
• Dominates over dynamic consumption
• Not a function of switching frequency
Wasted energy …Should be avoided in almost all cases,but could help reducing energy in others (e.g. sense amps)
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Principles for Power ReductionPrinciples for Power Reduction
Prime choice: Reduce voltage! Recent years have seen an acceleration in
supply voltage reduction Design at very low voltages still open question
(0.6 … 0.9 V by 2010!) Reduce switching activity Reduce physical capacitance
Device Sizing: for F=20– fopt(performance)=3.53, fopt(energy)=4.47