Điện tử số thầy Phạm Ngọc Nam.

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© R.LauwereinsImec 2001

Digitaldesign

Combina-torialcircuits

Sequentialcircuits

FSMDdesign

VHDL

Course contents

• Digital design• Combinatorial circuits: without status• Sequential circuits: with status• FSMD design: hardwired processorsLanguage based HW design: VHDL

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VHDL

Language based HW design:a VHDL primer

• Introduction• A first look at VHDL• Signals and data types• VHDL operators• Concurrent versus sequential statements• Sequential construction statements• Higher performance, less portability:

e.g. synthesis issues for Xilinx

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Introduction• A first look at VHDL• Signals and data types• VHDL operators• Concurrent versus sequential statements• Sequential construction statements• Higher performance, less portability:


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VHDL primer: Introduction

• Acronym: VHDL = VHSIC Hardware Description Language VHSIC = Very High Speed Integrated Circuit

• What is VHDL? A programming language for describing the behavior of

digital systems Design entry language, used for

Unambiguous specification at behavioral and RTL level

Simulation (executable specification…)SynthesisDocumentation

• Standardisation: IEEE 1076 First version: 1986 Second version: 1993 New version about to appear

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• When to use VHDL instead of schematics? Drawbacks:

VHDL is easy to learn but hard to master (semantics are quite different from software languages)

VHDL has a difficult syntax (Language sensitive editors with templates for all language constructs)

VHDL is very ‘wordy’: lots of code to type for just a few simple things

A list of instructions is less intuitive to understand than a block diagram for a human being

VHDL is designed to make simulation efficient: contains aspects that have hardly anything to do with hardware behavior, but is useful to speed-up event driven simulation

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• When to use VHDL instead of schematics? Easier to capture complex circuits: higher level of

abstraction with automated synthesis

you specify ‘add’ instead of jotting down a specific type of adder: the synthesis tool will instantiate the best type of adder under timing, area & power constraints

easy to parametrise (e.g. word length, queue depth)

easy to specify arrays of components Portable across many tools for simulation,

synthesis, analysis, verification, … of different vendors (e.g. Synopsys, Mentor Graphics, …)

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• Limitations of VHDL The standard only describes syntax and semantics,

but not the coding styleyou can specify the same behavior (e.g. MUX) in an

almost unlimited number of wayseach leading to a completely different implementation

(e.g. Multiplexor or tri-state bus)which is synthesis tool dependent.You should do lots of experimentation with style-tool

combinations to be able to predict how the hardware will look like that will be synthesised. Is prediction necessary? You also do not predict the ASM generated by C; C is less efficient than ASM but faster to write. Currently, it is hard to tolerate the inefficiency caused by the higher level specification for hardware.

Note: for DSP processors programmed in C, we do predict ASM and have to experiment with style-compiler combinations for efficiency reasons!!

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• Limitations of VHDL (ctud) Only a subset of VHDL can be automatically

synthesised; each vendor supports a different subset

Only digital; special extension (not yet widely adopted) for analog: VHDL-AMS (acronym for VHDL Analog and Mixed Signal)

IEEE standard 1076.1-1999is a super-set of the full IEEE VHDL

1076-1993 standard for digital design

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• Abstraction levels Behavioral

Interconnected functionsOnly info on functions or algorithms

(what)Only timing needed to let the function

work correctlyOK for VHDLBehavioral synthesisers immature; used

for high level executable specification in top-down design and manual synthesis into RTL

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• Abstraction levels RTL

Interconnected registers and combinatorial unitsInfo on function (what) and architecture (how)Cycle accurateNo technology dependent timing infoOK for VHDLGood synthesisers

Gate levelInterconnected gates and flip-flopsInfo on function and architectureInfo on technology dependent timing (gate delays)

LayoutInfo on layout on siliconContinuous timingAnalog effects

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• Other hardware description languages (HDL) Verilog

More widespread in USA than in EuropeOften required for gate level or RTL

level ASIC sign-offNever ending discussion which is better

PLD languages like ABEL, PALASM, …

These are more at the gate level, capturing also technology dependent features (e.g. detailed timing)

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• Difference between HDLs and traditional software programming languages Concurrency: all hardware components operate in

parallel Data types: support is needed for arbitrary size

integers, bit vectors, fixed point numbers Concept of time

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FSMDdesign

VHDL


• IntroductionA first look at VHDL• Signals and data types• VHDL operators• Concurrent versus sequential statements• Sequential construction statements• Higher performance, less portability:


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A First look at VHDL:Example 1 task description

• Design a circuit named ‘Test’ with 3 8-bit inputs (In1, In2, In3) and two boolean outputs (Out1, Out2). The first output equals ‘1’ when the first and second input are equal; the second output equals ‘1’ when the first and third input are equal.

• Let’s first make a schematic design:

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A First look at VHDL:Schematic specification

• The circuit will be hierarchically decomposed into a top level component ‘Test’ containing 2 instantiations of a comparator component ‘Compare’

In1

In2

In3

Test

Out1

Out2

Compare

A

B

EQ

Compare

A

B

EQ

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A

B

EQ

Compare

A First look at VHDL:Schematic specification

• The comparator is then hierarchically decomposed into a gate level combinatorial circuit

A[0]

B[0]

A[1]

B[1]

A[7]

B[7]

EQ

XNOR

AND

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A First look at VHDL:Entity and Architecture

• Declaration of the ‘Compare’ design entity:

-- Eight bit comparator--entity Compare is

port( A,B: in bit_vector(0 to 7);EQ: out bit);

end entity Compare;

architecture Behav1 of Compare isbegin

EQ <= ‘1’ when (A=B) else ‘0’;end architecture Behav1;

‘Entity’ specifiesthe interface

to the circuit, theblack box of a

schematic

Input and outputsignals are called

‘ports’

‘Architecture’ describesthe behavior and structure

of the entity,the internals of the boxNotes:

- Multiple architectures per entity are possible: different waysof implementing same behavior

- This architecture specifies behavior at RTL level and notthe actual structure of gates; synthesis tool will automaticallytranslate this RTL behavioral description into gate level

- Ports have an explicit direction and are (vectors of) bits

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A First look at VHDL:Component and Instantiation

• Specification of the next higher level in the circuit hierarchy: ‘Test’

-- Dual comparator Test component--entity Test is

port( In1,In2,In3: in bit_vector(0 to 7);Out1,Out2: out bit);

end entity Test;

architecture Struct1 of Test iscomponent Comparator is

port( X,Y: in bit_vector(0 to 7);Z: out bit);

end component Comparator;begin

Compare1: component Comparator port map (In1,In2,Out1);Compare2: component Comparator port map (In1,In3,Out2);

end architecture Struct1;

Two instantiationsof the same component

‘Comparator’ with itssignal binding

Notes:- The two ‘comparator’ components work concurrently!!!- This architecture describes structure, i.e. how this entityconsists of an interconnection of lower level components

Virtual device: allowsfor concurrent

development of bothhierarchical levels,

by different persons.‘Comparator’ will bebound to ‘Compare’

later

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A First look at VHDL:Comparison with C

• This is very similar to software programming languages, e.g. C

/* Eight bit comparator*/int Compare

(int A, int B)

{return (A == B);}

Interface to the function

Behavior of the function

Notes:

- Only one behavior per function possible

- Behavior is specified at rather high level and will beautomatically translated by the compiler into ASM instructions

- Function arguments do not have a direction and are of type int

Inputs and outputs arecalled ‘arguments’

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A First look at VHDL:Comparison with C

• This is how the higher hierarchical level looks like in C

/* Dual comparator Test program*/

main(){int In1, In2, In3;int Out1, Out2;

Out1 = Compare(In1, In2);Out2 = Compare(In1, In3);}

Two calls to the function‘Compare’ with itsargument binding

Notes:- The two ‘compare’ function calls are executed sequentially

- This main program is executed once and stops. In VHDL, allcomponents describe relations that are valid continuously andforever

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A First look at VHDL:Configuration

• When an entity has multiple architectures, how do you indicate which one to use?

• How do you bind ‘Components’ to ‘Entities’?

-- Configuration information: architecture selection-- and component-entity binding

configuration Build1 of Test isfor Struct1

for Compare1: Comparator use entity Compare(Behav1)port map (A => X, B => Y, EQ => Z);

end for;for others: Comparator use entity Compare(Behav1)

port map (A => X, B => Y, EQ => Z);end for;

end for;end configuration Build1;

Note: ‘configuration’ corresponds in SW to ‘linking’

Both ‘use entity’s couldbe combined in one:for All: Comparator ...

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A First look at VHDL:Syntax

ENTITY:

entity Entity_name isport( Signal_name: in Signal_type;

Signal_name: out Signal_type);end entity Entity_name;

ARCHITECTURE:

architecture Architecture_name of Entity_name islocal_signal_declarations;component_declarations;

beginstatements;

end architecture Architecture_name;

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COMPONENT:component Component_name is

port( Signal_name: in Signal_type;Signal_name: out Signal_type);

end component Component_name;

COMPONENT INSTANTIATION:-- component instantiationInstance_name: component Component_name

port map (Signal_list);or

-- direct instantiationInstance_name: entity Entity_name(Architecture_name)

port map (Signal_list);

SIGNAL LIST:-- two variants:-- variant 1: ordered list of signals as in software languages-- e.g. (In1,In2,Out1)-- variant 2: named list-- e.g. (B => In2, EQ => Out1, A => In1)

Locally used name

Name used incomponent declaration

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CONFIGURATION:

configuration Config_name of Entity_name isfor Architecture_name

for Instance_name: Component_name use entityEntity_name(Architecture_name)port map (Signal_list);

end for;end for;

end configuration Config_name;

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A First look at VHDL:Example 2

• Declare a 3-input AND gate

ABC

Y

-- 3-input AND gate

entity AND3 isport ( A,B,C: in bit;

Y: out bit);end entity AND3;

architecture RTL of AND3 isbegin

Y <= ‘1’ when ((A=‘1’) and (B=‘1’) and (C=‘1’)) else ‘0’;end architecture RTL;

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• Declare a 3-input OR gate

ABC

Y

-- 3-input OR gate

entity OR3 isport ( A,B,C: in bit;

Y: out bit);end entity OR3;

architecture RTL of OR3 isbegin

Y <= ‘0’ when ((A=‘0’) and (B=‘0’) and (C=‘0’)) else ‘1’;end architecture RTL;

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• Declare an INV gate

-- INV gate

entity INV isport ( A: in bit;

Y: out bit);end entity INV;

architecture RTL of INV isbegin

Y <= ‘1’ when (A=‘0’) else ‘0’;end architecture RTL;

A Y

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• Build a 2-to-1 MUX using both a behavioral as well as a structural description

A

S

BY

entity MUX21 isport ( A,B,S: in bit;

Y: out bit);end entity MUX21;

The black boxinterface

architecture Behav of MUX21 isbegin

Y <= A when (S=‘1’) else B;end architecture Behav;

Behavioral description

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architecture Struct of MUX21 issignal U,V,W : bit;component AND2 is

port ( X,Y: in bit;Z: out bit);

end component AND2;component OR2 is

port ( X,Y: in bit;Z: out bit);

end component OR2;component INV is

port ( X: in bit;Z: out bit);

end component INV;begin

Gate1: component INV port map (X=>S,Z=>U);Gate2: component AND2 port map (X=>A,Y=>S,Z=>W);Gate3: component AND2 port map (X=>U,Y=>B,Z=>V);Gate4: component OR2 port map (X=>W,Y=>V,Z=>Y);

end architecture Struct;


• Build a 2-to-1 MUX using both a behav. as well as a structural description A

S

BY

Structural description

A

S

B

Y

U V

W

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• Assume that we want to use the previously declared AND3, OR3 and INV for this structural description of MUX

configuration Use3InputGates of MUX21 isfor Behavend for;for Struct

for Gate1:INV use entity INV(RTL)port map (A=>X,Y=>Z);

end for;for All:AND2 use entity AND3(RTL)

port map (A=>X,B=>Y,C=>’1’,Y=>Z);end for;for Gate4:OR2 use entity OR3(RTL)

port map (A=>X,B=>Y,C=>’0’,Y=>Z);end for;

end for;end configuration Use3InputGates;

Entities

ABC

Y

A Y

Components

X Y

Z

X Z

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A First look at VHDL:Test bench

• How can we verify the circuit that we made? We have to apply representative stimuli to the circuit and check whether the outputs are correct

• A VHDL ‘test bench’ can be considered to be the top level of a design It instantiates the Design Under Test (DUT) applies stimuli to it checks whether the stimuli are correct

or captures the outputs for visualisation in a waveform

viewer

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A First look at VHDL:Test bench

• Create a test bench for the behavioral version of the MUX

MUX21

A

BY

S

entity Testbench isend entity Testbench;

Testbench isself-contained:

no ports

architecture BehavTest of Testbench isSignal In1,In2,Select,Out : bit;

beginDUT: entity MUX21(Behav) port map (In1, In2, Select, Out);Stimulus: process is

beginIn1<=‘0’;In2<=‘1’;Select<=‘0’; wait for 20 ns;Select<=‘1’; wait for 20 ns;In1<=‘1’;In2<=‘0’; wait for 20 ns;...end process Stimulus;

end architecture BehavTest;

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A First look at VHDL:Re-use

• Often, parts of a design can be re-used in another design

• New products in industry often contain 95% of re-used parts and 5% is newly designed: evolutionary design

• VHDL encourages this by the concept of ‘Packages’

• A ‘Package’ contains definitions of constant values, component declarations, user data types, and sub-programs of VHDL code

• But first the concept ‘Library’: a library is name of directory into which the binary code resulting from analysis/compilation is stored. Default: WORK

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A First look at VHDL:Re-use

Package interface declaration:

package Package_name is-- constants-- user defined types-- component declarations-- sub programs

end package Package_name;

How to use a package?

use Library_name.Package_name.all;

…

U1: entity Package_name.Entity_name(Architecture_name);

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• Introduction• A first look at VHDLSignals and data types• VHDL operators• Concurrent versus sequential statements• Sequential construction statements• Higher performance, less portability:


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Signals and Data Types:Predefined signal types

package Standard istype Bit is (‘0’,’1’);type Boolean is (False, True);type Character is (--ASCII set);type Integer is range implementation_defined;type Real is range implementation_defined;type Bit_vector is (--array of bits);type String is (--array of characters);type Time is range implementation_defined;

end package Standard;

Bit, Boolean and Character are enumeration types

All standard types are ‘unresolved’ (see later for the meaningof this)

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Examples of integer declarations:type Year is range 0 to 99;type Memory_address is range 65535 downto 0;

Examples of real declarations:type Probability is range 0.0 to 1.0;type Input_level is range -5.0 to 5.0;

A Bit_vector is a collection of bits; a value is specified betweendouble quotes:

constant State1: bit_vector(4 downto 0) := “00100”;

A String is a collection of characters; a value is specifiedbetween double quotes:

constant Error_message: string:= “Unknown error: ask your poor sysop for help”;

Checked by simulator

MSB, bit 4 LSB

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Time is a physical type:type Time is range implementation_defined

unitsfs;ps = 1000 fs;ns = 1000 ps;us = 1000 ns;ms = 1000 us;sec = 1000 ms;min = 60 sec;hr = 60 min;

end units;

Primary unit:resolution limit

Secondary units

Examples of use:wait for 20 ns;constant Sample_period: time := 2 ms;constant Clock_period: time := 50 ns;

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Signals and Data Types:User defined physical types

The user may define his/her own physical types:type Length is range 0 to 1E9

unitsum;mm = 1000 um;m = 1000 mm;km = 1000 m;mil = 254 um;inch = 1000 mil;foot = 12 inch;yard = 3 foot;

end units;

Primary unit:resolution limit

Metric secondary units

Imperial secondary units

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Signals and Data Types:User defined enumeration types

The user may define his/her own enumeration types:type FSM_states is (reset, wait, input, calculate, output);

Not all synthesis tools support enumerated types

When they do support them, the default encoding is oftenstraightforward encoding using the minimum number of bits

Often, the default encoding may be over-written by somewherespecifying something like “encoding_style is gray_code” or byexplicitly specifying the encoding for each possible value:

constant reset: bit_vector := “10000”;constant wait: bit_vector := “01000”;constant input: bit_vector := “00100”;constant calculate: bit_vector := “00010”;constant output: bit_vector := “00001”;

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Signals and Data Types:Array types

The user may define arrays of types:type 1D_array is array (1 to 10) of integer;type 2D_array is array (5 downto 0, 1 to 10) of real;

Keep in mind that a vector of bits has NO numerical meaningand that hence arithmetic operations on vectors of bits makeno sense:

signal Bus,Address : bit_vector (0 to 3);

Bus <= Address + 1; -- This makes no sense!!!

Solution: via operator overloading (cf. C++):- two functions ‘+’ will exist, one working on integers andone working on vectors of bits- the latter is defined in a vendor specific ‘vectorarithmetic package’ that should be use’d at the beginningof your VHDL

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Signals and Data Types:Standard logic

• We have seen that we need more logic levels than just ‘0’ and ‘1’ (e.g. don’t care, unknown after setup violation, …)

• Therefore the IEEE defined in standard number 1164 9-valued logic signals and operations on them: use always those instead of ‘bit’!!

• Exists in unresolved form (std_ulogic) and resolved form (std_logic) -- again: see later for meaning

• Exists in single bit and array form: constant A: std_ulogic := ‘U’; -- unitialized constant B: std_logic := ‘U’; constant C: std_ulogic_vector (0 to 15); constant D: std_logic_vector (15 downto 0);

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Signals and Data Types:Standard logic

library IEEE;use IEEE.Std_logic_1164.All;

type std_logic is (‘U’, -- uninitialized e.g. after power-up‘X’, -- strongly driven unknown e.g. after setup violation‘0’, -- strongly driven logic zero‘1’, -- strongly driven logic one‘Z’, -- high impedance e.g. not driven at all‘W’, -- weakly driven unknown‘L’, -- weakly driven logic zero‘H’, -- weakly driven logic one‘-’); -- don’t care

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Signals and Data Types:Assignment to signals

Is the following code valid?

signal Z,A,B: std_ulogic;

Z <= A;Z <= B;

No, because:- all statements are concurrently valid and are not executedsequentially as in SW languages- when A=‘0’ and B=‘1’, we have a short circuit

A

BZ

A

B ZR

Resolvercircuit

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• VHDL is a single assignment language for unresolved data types

• For resolved data types (std_logic & std_logic_vector), the resolver circuit is inferred by the synthesis tool

A

B ZR

Resolvercircuitsignal Z,A,B: std_logic;

Z <= A;Z <= B;

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• When an array is assigned to another array, both arrays must have same size

• Assignment is by position, not by index!!!

signal Down: std_logic_vector (3 downto 0);signal Up: std_logic_vector (0 to 3);

Up <= Down;

Which of the two following interpretations is correct?

Up(0)

Up(1)

Up(2)

Up(3)

Down(3)

Down(2)

Down(1)

Down(0)

OR

Up(0)

Up(1)

Up(2)

Up(3)

Down(0)

Down(1)

Down(2)

Down(3)

Correspondence by position!

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• Assignment to a part of an array is possible• Make sure that the direction (to or downto) is

the same as in the declaration

signal Bus: std_logic_vector (7 downto 0);signal A: std_logic_vector (0 to 3);

Which of the following VHDL codes is correct?

Bus(0 to 3) <= A;

Bus <= A;

Bus(3 downto 0) <= A;

Bus(5 downto 4) <= A(0 to 1);

Bus(5 downto 4) <= A(0 to 1);Bus(4 downto 3) <= A(2 to 3);

Direction of Bus differs from declaration

Array sizes do not match

OK! Bus(3) is driven by A(0)

OK! Bus(5) is driven by A(0)

OK! Bus(4) is driven by A(1)and by A(2): resolved data

type… use with care!!

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• ‘Concatenation’: bring wire bundles together to assign them to a bigger arraysignal Byte_bus: std_logic_vector(7 downto 0);signal Nibble_busA, Nibble_busB: std_logic_vector(3 downto 0);

Byte_bus <= Nibble_busA & Nibble_busB;

Byte_bus(7)Byte_bus(6)Byte_bus(5)Byte_bus(4)Byte_bus(3)Byte_bus(2)Byte_bus(1)Byte_bus(0)

Nibble_busA(3)Nibble_busA(2)Nibble_busA(1)Nibble_busA(0)

Nibble_busB(3)Nibble_busB(2)Nibble_busB(1)Nibble_busB(0)

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• ‘Aggregation’: alternative method to assign multiple small arrays to a bigger array

• Not supported by all synthesis tools!!

signal X,Y,Z,T: std_logic_vector(3 downto 0);signal A,B,C: std_logic;

X <= (A,B,C,C); -- correspondence by position

Y <= (3 => A, 1 downto 0 => C, 2 => B);

Z <= (3 => A, 2 => B, others => C);

T <= (others => ‘0’); -- initialization irrespective of width of T

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Signals and Data Types:Generic constants

• Allows to parameterize behavior• Enables re-use of entities in slightly changing

environments• Makes VHDL much more powerful than

schematic entry• Generic constants need to have a value at

synthesis time!

entity General_mux isgeneric (width : integer);port ( Input : in std_logic_vector (width - 1 downto 0);

Select : in integer range 0 to width - 1;Output : out std_logic);

end entity General_mux;

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Generic constantsentity General_mux is

generic (width : integer);port ( Input : in std_logic_vector (width - 1 downto 0);



architecture Behav of General_mux isbegin

Output <= Input(Select);end architecture Behav;

entity Testbench isend entity Testbench;

architecture Build1 of Testbench isconstant Input_size : integer := 8;signal A : std_logic_vector (Input_size-1 downto 0);signal S : integer range 0 to Input_size - 1;signal B : std_logic;

beginDUT: entity General_mux(Behav)

generic map (width => Input_size)port map (Input => A, Select => S, Output => B);

...end architecture Build1;

This is not valid VHDL:index is not known atdesign time! We willreplace this by valid

code later!

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• Introduction• A first look at VHDL• Signals and data typesVHDL operators• Concurrent versus sequential statements• Sequential construction statements• Higher performance, less portability:


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Logical Operators

• List of logical operators: not, and, or, xor, nand, nor

• Precedence: ‘not’ has highest precedence all others have equal precedence, lower than ‘not’

• Logical operators are predefined for following data types: bit, bit_vector, boolean, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector

• A logical operator may work on an array: arrays should have same size elements are matched by position

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Logical Operators

library IEEE;use IEEE.Std_Logic_1164.All;

entity Gate isport( A,B,C: in std_logic;

Z: out std_logic);end entity Gate;

architecture Logical of Gate isbegin

Z <= A and not(B or C);end architecture Logical;

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Logical Operators

library IEEE;use IEEE.Std_Logic_1164.All;

entity Gate isgeneric(width : integer range 0 to 31);port( A,B,C: in std_logic_vector(width-1 downto 0);

Z: out std_logic_vector(width-1 downto 0));end entity Gate;

architecture Logical of Gate isbegin

Z <= A and not(B or C);end architecture Logical;

5/56


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VHDL

Relational Operators

• List of relational operators: <, <=, =>, >, =, /=

• Relational operators return a boolean• Both operands need to be of the same type• A relational operator may work on an array:

arrays may have different size!! They are left alligned and the number of bits equal

to the smallest array are compared; the comparison is done bit by bit, from left to right

Remember: vectors of bits do not have a numerical meaning!! However, this comparison works on vectors of bits with the meaning of an unsigned integer when both vectors have equal length

5/57


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Relational Operatorslibrary IEEEuse IEEE.Std_Logic_1164.All;

entity Compare isport( A: in std_logic_vector(3 downto 0);

B: in std_logic_vector(0 to 4);Z: out boolean);

end entity Compare;

architecture Relational of Compare isbegin

Z <= TRUE when A<B else FALSE;end architecture Relational;

entity Testbenchend entity Testbench;

architecture Build1 of Testbench issignal A: std_logic_vector(3 downto 0) := “1110”;signal B: std_logic_vector(0 to 4) := “10111”;signal Z: boolean;begin

DUT: entity Compare(Relational)port map (A => A, B => B, Z => Z);

end architecture Build1;

What is thevalue of Z?

TRUE?

FALSE?

1110is compared to

1011by bit position

from left toright;

in the 2nd position

A(2) > B(1)hence (A<B)

is FALSE

5/58


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VHDL

Arithmetic Operators

• List of arithmetic operators: +, -, *, /, ** (exponential), abs (absolute value), mod (modulus), rem (remainder)

• They are defined on types integer and real (except mod and rem) and not on vectors of bits; use overloading package for the latter (vendor dependent)

• Both operands have to be of same type; different ranges are allowed

• A variable of physical type (e.g. time) may be multiplied by an integer or real and will still return a variable of the physical type

5/59


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Arithmetic Operators

entity Add isport ( A,B: in integer range 0 to 7;

Z: out integer range 0 to 14);end entity Add;

architecture Behav of Add isbegin

Z <= A + B;end architecture Behav;

5/60


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• Introduction• A first look at VHDL• Signals and data types• VHDL operatorsConcurrent versus sequential statements• Sequential construction statements• Higher performance, less portability:


5/61


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VHDL

Concurrent Statements

• All statements are concurrent and are continuously valid: this mimics the behavior of hardware, where all gates operate concurrently

entity Concurrent isport ( A,B,C,D: in std_logic;

Y,Z: out std_logic);end entity Concurrent;

architecture Struct of Concurrent isbegin

NAND1: entity NAND2 port map (A,B,Y);NAND2: entity NAND2 port map (C,D,Z);


A

B

C

D

Y

Z

Schematic:

What is the difference in behavior when NAND1 is specifiedafter NAND2?

5/62


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• All statements are concurrent and are continuously valid: this mimics the behavior of hardware, where all gates operate concurrently

entity Concurrent isport ( A,B,C,D: in std_logic;

Y,Z: out std_logic);end entity Concurrent;

architecture Struct of Concurrent isbegin

NAND2: entity NAND2 port map (C,D,Z);NAND1: entity NAND2 port map (A,B,Y);


A

B

C

D

Y

Z

Schematic:

Behavior is exactly the same!!!

5/63


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VHDL


A

B

DZ

Schematic:

T1

Does this schematic specify sequential Behavior?

Yes

No

entity Concurrent isport ( A,B, D: in std_logic;

Z: out std_logic);end entity Concurrent;

architecture Struct of Concurrent issignal T1: std_logic;begin

NAND2: entity NAND2 port map (T1,D,Z);NAND1: entity NAND2 port map (A,B,T1);


Both gates continuously update their outputs

5/64


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VHDL

Simulation

• This continuously updating of outputs poses problems to the simulator: even if nothing in the circuit changes, the simulator has to compute continuously the ‘new’ outputs of all gates

• Solution: event-driven simulation a statement is only re-evaluated when one or more

of its input signals changes (i.e. when an event occurs at one of its inputs)

we say that a statement is sensitive to all its input signals, because an event at any input signals triggers a re-evaluation

keep in mind that this mechanism is only for making simulation fast while maintaining the same behavior as in reality, where all gates work continuously!!

5/65


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Simulation

• How is an event-driven simulator practically implemented?

1. Put all statements with at least one changed input in the‘process execution queue’

2. Execute all statements in the process execution queueone by one (or concurrently if the simulator is executedon a parallel computer) without updating the output signals

3. After all statements in the process execution queue areprocessed, update the output signals

4. Add all statements to the process execution queue thathave an event because of the updated output signals

6. Advance system time to the next time where a timedevent is planned (e.g. testbench: waitfor 20 ns)

5. Repeat until the process execution queue is empty

Delta cycleDelta cycle convergence

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Simulationentity Flipflop is

port ( A,B: in std_logic;Q,Q’: out std_logic);

end entity Flipflop;

architecture Struct of FlipFlop isbegin

NAND2: entity NAND2 port map (Q’,B,Q);NAND1: entity NAND2 port map (A,Q,Q’);


Step 1: Put statements with inputevent in PEQ

ProcessExecution

QueueT1

ProcessExecution

QueueT2

A

BQ

Q’

A

B

Q

Q’

T1 T2

NAND1 NAND1

NAND2

5/67


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Step 2: Execute statements in PEQand remember output

ProcessExecution

QueueT1

ProcessExecution

QueueT2

A

BQ

Q’

A

B

Q

Q’

T1 T2

NAND1 NAND1

NAND2

NAND1

RememberedOutputs

Q’ <= 1

5/68


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Step 3: Update outputs

ProcessExecution

QueueT1

ProcessExecution

QueueT2

A

BQ

Q’

A

B

Q

Q’

T1 T2

NAND1 NAND1

NAND2

NAND2

RememberedOutputs

Q’ <= 1

5/69


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Step 4: Add statements with eventto PEQ

ProcessExecution

QueueT1

ProcessExecution

QueueT2

A

BQ

Q’

A

B

Q

Q’

T1 T2

NAND1

NAND2

NAND2

End Delta cycle 1 of T1

5/70


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ProcessExecution

QueueT1

ProcessExecution

QueueT2

A

BQ

Q’

A

B

Q

Q’

T1 T2

NAND1

NAND2

NAND2NAND2

RememberedOutputs

Q <= 0

5/71


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ProcessExecution

QueueT1

ProcessExecution

QueueT2

A

BQ

Q’

A

B

Q

Q’

T1 T2

NAND1

NAND2

NAND2NAND2

RememberedOutputs

Q <= 0

5/72


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ProcessExecution

QueueT1

ProcessExecution

QueueT2

A

BQ

Q’

A

B

Q

Q’

T1 T2

NAND1

NAND2

NAND1


5/73


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ProcessExecution

QueueT1

ProcessExecution

QueueT2

A

BQ

Q’

A

B

Q

Q’

T1 T2

NAND1

NAND2

NAND1NAND1

RememberedOutputs

Q’ <= 1

5/74


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ProcessExecution

QueueT1

ProcessExecution

QueueT2

A

BQ

Q’

A

B

Q

Q’

T1 T2

NAND1

NAND2

NAND1NAND1

RememberedOutputs

Q’ <= 1

Output does not change

5/75


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ProcessExecution

QueueT1

ProcessExecution

QueueT2

A

BQ

Q’

A

B

Q

Q’

T1 T2

NAND1

NAND2

End Delta cycle 3 of T1: convergence

5/76


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Step 6: Advance system time

ProcessExecution

QueueT1

ProcessExecution

QueueT2

A

BQ

Q’

A

B

Q

Q’

T1 T2

NAND1

NAND2

5/77


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ProcessExecution

QueueT1

ProcessExecution

QueueT2

A

BQ

Q’

A

B

Q

Q’

T1 T2

NAND1

NAND2

NAND1

RememberedOutputs

Q’ <= 1NAND2NAND2

Q <= 1

NAND2 computed using this Q’, not the remembered

5/78


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ProcessExecution

QueueT1

ProcessExecution

QueueT2

A

BQ

Q’

A

B

Q

Q’

T1 T2

NAND1

NAND2

NAND1

RememberedOutputs

Q’ <= 1NAND2NAND2

Q <= 1

5/79


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ProcessExecution

QueueT1

ProcessExecution

QueueT2

A

BQ

Q’

A

B

Q

Q’

T1 T2

NAND1


5/80


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ProcessExecution

QueueT1

ProcessExecution

QueueT2

A

BQ

Q’

A

B

Q

Q’

T1 T2

NAND1NAND1

RememberedOutputs

Q’ <= 0

5/81


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ProcessExecution

QueueT1

ProcessExecution

QueueT2

A

BQ

Q’

A

B

Q

Q’

T1 T2

NAND1NAND1

RememberedOutputs

Q’ <= 0

5/82


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ProcessExecution

QueueT1

ProcessExecution

QueueT2

A

BQ

Q’

A

B

Q

Q’

T1 T2

NAND2


5/83


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ProcessExecution

QueueT1

ProcessExecution

QueueT2

A

BQ

Q’

A

B

Q

Q’

T1 T2

NAND2NAND2

RememberedOutputs

Q <= 1

5/84


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ProcessExecution

QueueT1

ProcessExecution

QueueT2

A

BQ

Q’

A

B

Q

Q’

T1 T2

NAND2NAND2

RememberedOutputs

Q <= 1

Output does not change

5/85


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ProcessExecution

QueueT1

ProcessExecution

QueueT2

A

BQ

Q’

A

B

Q

Q’

T1 T2

End Delta cycle 3 of T2: convergence

5/86


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Step 6: Advance system time

ProcessExecution

QueueT1

ProcessExecution

QueueT2

A

BQ

Q’

A

B

Q

Q’

T1 T2

5/87


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Process

• Sometimes, the combinatorial equation in a single statement becomes very complicated:

entity Complex isport( A,B,C,D,E,F,G,H,I,J:

in std_logic;Y,Z: out std_logic);

end entity Complex;

architecture Struct of Complex isbegin

Y <= ((A nand B) nand (C nand D))when (S = ‘1’) else((E nand F) nand (G nand H));

Z <= I nand J;end architecture Struct;

A

B

C

D

E

F

G

H

S

Y

I

J

Z

5/88


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VHDL

Process

• Therefore a process has been defined: a process acts as a single statement that is

executed concurrently with all other statements inside a process, commands are executed

sequentially in the order they are listed. This makes it easy to break down a very complicated statement into a list of smaller commands

to pass data from one command to the other, we may declare temporary variables; they do not have necessarily a physical realization

a statement, and hence also a process, is sensitive to all its input signals; to facilitate finding out what the input signals of a process are, since they can occur in any command, we have to explicitly add them to a sensitivity list. A process is recalculated when a signal in the sensitivity list has an event.

Unfortunately, in VHDLterminology they are

also called ‘Statements’

5/89


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VHDL

Process

Syntax of process:

Process_name: process (sensitivity_list) is-- variable declarations;

begin-- sequential commands

end process Process_name;

Syntax of variable declaration:

variable Variable_name: type;

Syntax of variable assignment:

Variable_name := expression;

When assigning to variable :=When assigning to signal <=

5/90


Digitaldesign


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VHDL

Process

• Rewrite the example using a process:

entity Complex isport( A,B,C,D,E,F,G,H,I,J:

in std_logic;Y,Z: out std_logic);

end entity Complex;

architecture Struct of Complex isbegin

Y_process: process (A,B,C,D,E,F,G,H,S) isvariable T1,T2: std_logic;beginif (S=‘1’) then

T1 := A nand B;T2 := C nand D;

elseT1 := E nand F;T2 := G nand H;

end if;Y <= T1 nand T2;

end process Y_process;Z <= I nand J;


A

B

C

D

E

F

G

H

S

Y

I

J

Z

T1 and T2 have no physical meaning since each refers

to 2 different physical wires

T1 T2

Sensitivity list

5/91


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Process

• Processes and delta cycle convergence. What is the behavior of following process:

Example: process (A,B,M) isbegin

Y <= A;M <= B;Z <= M;

end process Example;

1. Assume event at B with new value B’

2. Process Example is executed once sequentially. Followingoutputs are remembered: Y’ <= A; M’ <= B’; Z’ <= M;

Old M!!! M getsonly new value

at end of process

3. Process Example suspends (i.e. is executed once completely).Y, M and Z get their new values Y’, M’, Z’.

4. Since M is in the sensitivity list, the Example process isplaced again in the Process Execution Queue.

5. Process Example is executed: Y” <= A; M” <= B’; Z” <= M’;

6. Outputs Y, M and Z get their new values Y”, M”, Z”.

7. No signals of the sensitivity list changed => delta cycleconvergence

5/92


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VHDL

Process

• Processes and delta cycle convergence. What is the behavior of following process:

Example: process (A,B,C,D) isbegin

Z <= A + B;Z <= C + D;

end process Example;

1. Assume event at B with new value B’2. The commands of Process Example are executed

sequentially. First following output is remembered:Z’ <= A + B’;

3. Next, the second command is executed and following outputis remembered: Z’ <= C + D. This overwrites the previouslyremembered Z’

4. Process Example suspends and hence signal Z is updatedwith its new value C + D

When the same two statements would have occurred outside aprocess, both would drive signal Z and a resolver would benecessary

5/93


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• Introduction• A first look at VHDL• Signals and data types• VHDL operators• Concurrent versus sequential statementsSequential construction statements• Higher performance, less portability:


5/94


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Sequential construction statements

• Sequential construction statements are only allowed within a process!!!• There are 3 sequential construction statements: IF, CASE, FOR

IF statement:

if condition then-- sequential statements

else-- sequential statements

end if;

multiple IF statements:

if condition1 then-- sequential statements

elseif condition2 then-- sequential statements

elseif condition3 then-- sequential statements

else-- sequential statements

end if;

The first condition whichturns out to be TRUE

determines whichsequential statements areexecuted: built-in priority

5/95


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case Expression iswhen Value_1 =>

-- sequential statementswhen Value_2 =>

-- sequential statements-- etc.

end case;

Example: process (A,B,C,X) isbegin

case X iswhen 0 to 4 =>

Z <= B;when 5 =>

Z <= C;when 7 | 9 =>

Z <= A;when others =>

Z <= ‘0’;end process Example;

Requirements:

1. All possible values shouldbe specified

2. The values should beconstant and known atdesign time

3. The values should have thesame type as theexpression

5/96


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VHDL


for I in 0 to 3 loop-- sequential statements

end loop;

1. The loop variable must not be declared

Remarks:

2. The synthesis tool will unfold the loop and create logic foreach iteration of the loop. Then, it will start minimizing thecomplete circuit

5/97


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Output <= Input(Select);end architecture Behav;

We indicated that this is not valid VHDL:index is not known atdesign time! We willreplace this now byvalid code using the

loop construct.

5/98


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Selector: process (Input, Select) isbegin

for I in 0 to width-1 loopif Select=I then

Output <= Input(I);end if;

end loop;end process Selector;

end architecture Behav;

5/99


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VHDL

Variables

• A variable can only be used within a process• A variable is updated immediately; a signal is

stored in the signal update queue till the process suspends

• Variables may be assigned to signals and vice versa

• Variables are used as intermediate values to facilitate the specification of the process; when the value of a variable needs to be accessible outside the process, it should be assigned to a signal

5/100


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VHDL

Variables

With which hardware schematic does following code correspond?

entity Parity isgeneric (width : integer);port (A: in std_logic_vector (0 to width-1);

Odd: out std_logic);end entity Parity;

architecture Struct of Parity isbegin

Parity: process(A) isvariable Temp: std_logic;

beginTemp := ‘0’;for I in A’low to A’high loop

Temp := Temp xor A(I);end loop;Odd <= Temp;

end process Parity;end architecture Struct;

0

A(0)

A(1)

A(2)

Temp

Temp

Odd

This is the HW structureas it is given to the synthesis

tool. The synthesis toolwill optimize away the xor

with constant ‘0’ inputand will transform it to

a binary tree of less depth

5/101


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Rising clock edgeWith which function does following code correspond?

entity What isport (D,Clk: in std_logic;

Q: out std_logic);end entity What;

architecture RTL of What isbegin

process (D, Clk) isbegin

if (Clk=‘1’) thenQ <= D;

end if;end process;

end architecture RTL;

With a latch, not with a D-flip-flop!!

When a Clk-event occurs and Clk is low, nothing happens

When a Clk-event occurs and Clk is high, the D input is copiedto the Q output

When a D-event occurs and Clk is high, the D input is copied tothe Q output => hence a latch: when Clk is high, Q follows D

Since there is no ELSE partthe previous Q value has

to be remembered for the casewhere Clk=‘0’.

The synthesis tool will henceinfer a latch instead of just

combinatorial logic!!!

Beware of unintended latcheswhen ELSE parts are omitted

5/102


Digitaldesign


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VHDL

Rising clock edge

How do we describe a rising clock edge?

Method 1: WAIT UNTIL

entity DFlipFlop isport (D,Clk: in std_logic;

Q: out std_logic);end entity DFlipFlop;

architecture RTL of DFlipFlop isbegin

process isbegin

wait until Clk’event and Clk=‘1’;Q <= D;

end process;end architecture RTL;

This is not synthesisable

5/103


Digitaldesign


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Rising clock edgeHow do we describe a rising clock edge?

Method 2: Sensitivity list

entity DFlipFlop isport (D,Clk: in std_logic;



process (D,Clk) isbegin

if (Clk’event and Clk=‘1’) thenQ <= D;

end if;end process;


Preferred method!

5/104


Digitaldesign


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VHDL

Rising clock edge

How do we describe combinatorial circuits with registered outputs?

Method 1: WAIT UNTIL

entity RegisteredCircuit isport (A,B,C,D,Clk: in std_logic;

Z: out std_logic);end entity RegisteredCircuit;

architecture RTL of RegisteredCircuit isbegin

process isbegin

wait until Clk’event and Clk=‘1’;-- combinatorial circuitZ <= (A and B) or (C and D);

end process;end architecture RTL;

A

B

C

D

Z

‘Wait until’ has to befirst line of process,

followed bythe description of thecombinatorial circuit

5/105


Digitaldesign


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VHDL

Rising clock edge

How do we describe combinatorial circuits with registered outputs?

Method 2: Sensitivity list

entity RegisteredCircuit isport (A,B,C,D,Clk: in std_logic;

Z: out std_logic);end entity RegisteredCircuit;

architecture RTL of RegisteredCircuit isbegin

process (A,B,C,D,Clk) isbegin

if (Clk’event and Clk=‘1’) then-- combinatorial circuitZ <= (A and B) or (C and D);

end if;end process;


A

B

C

D

Z

‘if Clk’event’ has to befirst line of process,with the descriptionof the combinatorialcircuit in the THENpart and with no

ELSE part

5/106


Digitaldesign


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VHDL

Rising clock edge

• The amount of logic we describe in the combinatorial part, determines the combinatorial delay

• It hence determines the maximum clock frequency with which we can clock the flip-flop

• Re-timing requires re-writing the VHDL code

5/107


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Rising clock edge

How do we describe flip-flops with asynchronous reset?

entity DFlipFlop isport (D,Clk, Reset: in std_logic;



process (D, Clk, Reset) isbegin

if (Reset = ‘1’) thenQ <= ‘0’;

elseif (Clk’event and Clk=‘1’) thenQ <= D;

end if;end process;


5/108


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Rising clock edge

How do we describe flip-flops with synchronous reset?

entity DFlipFlop isport (D,Clk, Reset: in std_logic;



process (D, Clk, Reset) isbegin

if (Clk’event and Clk=‘1’) thenif (Reset=‘1’) then

Q <= 0;else

Q <= D;end if;

end if;end process;


5/109


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VHDL

Finite State Machine

Wait00

Up101

Up210

Up311

Down311

Down210

Down101

Start=0

Start=1Up=0

Start=1Up=1

UpStart

Nextstatelogic

Output

logic

StateReg

ResetOutput

NextState

CurrentState

5/110


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Wait00

Up101

Up210

Up311

Down311

Down210

Down101

Start=0

Start=1Up=0

Start=1Up=1

entity FSM isport ( Start, Up, Reset, Clk: in std_logic;

Output: out std_logic_vector(0 to 1));end entity FSM;

architecture Behav of FSM istype FSM_States = (Wait,Up1,Up2,

Up3,Down1,Down2,Down3);signal CurrentState, NextState :

FSM_States;begin

OutputLogic:process(CurrentState) is

…end process OutputLogic;NextStateLogic:process(CurrentState,Start,Up) is

…end process NextStateLogic;StateRegister:process(NextState,Clk,Reset) is

…end process StateRegister;

end architecture Behav;

5/111


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VHDL


Wait00

Up101

Up210

Up311

Down311

Down210

Down101

Start=0

Start=1Up=0

Start=1Up=1

OutputLogic:process(CurrentState) isbegin

case CurrentState iswhen Wait =>

Output <= “00”;when Up1|Down1 =>



Output <= “11”;end case;

end process OutputLogic;

5/112


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Wait00

Up101

Up210

Up311

Down311

Down210

Down101

Start=0

Start=1Up=0

Start=1Up=1

NextStateLogic:process(CurrentState,Start,Up) isbegin

case CurrentState iswhen Wait =>

if (Start=‘0’) thenNextState <= Wait;

elseif (Up=‘1’) then NextState <= Up1;

elseNextState <= Down3;

end if;when Up1 =>

NextState <= Up2;when Up2 =>

NextState <= Up3;when Up3|Down1 =>

NextState <= Wait;when Down3 =>

NextState <= Down2;when Down2 =>

NextState <= Down1;end case;

end process NextStateLogic;

5/113


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VHDL


Wait00

Up101

Up210

Up311

Down311

Down210

Down101

Start=0

Start=1Up=0

Start=1Up=1

StateRegister:process(NextState,Clk,Reset) isbegin

if Reset=‘1’ thenCurrentState <= Wait;

elseif (Clk’event and Clk=‘1’) thenCurrentState <= NextState;

end if;end process StateRegister;

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• Introduction• A first look at VHDL• Signals and data types• VHDL operators• Concurrent versus sequential statements• Sequential construction statementsHigher performance, less portability:


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Resource sharing

What is the circuit corresponding to:

if Sel = ‘1’ thenZ <= A + B;

elseZ <= A + C;

end if;

+ +

MUX

A B CA

Sel

Z

This is kind of stupid, since bothadditions are mutually exclusive:it is hence not necessary toimplement 2 adders.

Some synthesis tools are capableto recognize this (often only withinthe scope of a process) andtransform this into the shared useof one adder for both additions.Xilinx Foundation Series performsthis optimization within ahierarchical level.

+

MUX

B C A

Z

Sel

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Resource sharing

If the synthesis tool does not dothis optimization automatically,you should re-write your code:

+

MUX

B C A

Z

Sel

if Sel = ‘1’ thenX := B;

elseX := C;

end if;Z <= A + X;

The VHDL coding style together with the capabilities of thesynthesis tool determine the circuit that is eventuallysynthesized.

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Using LogiBLOX in VHDL

• LogiBLOX modules lead to highly efficient FPGA implementations

• The LogiBLOX module generator creates, apart from the FPGA implementation, also a behavioral level VHDL module for simulation!

• How to use LogiBLOX modules in your VHDL code: use the package containing the LogiBLOX modules:

library My_Library; use My_Library.My_Package.all; instantiate the entity

• Using LogiBLOX makes your VHDL implementation more efficient on Xilinx FPGA but less portable to other devices!!

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Encoding of State Machines

• The default encoding in Foundation Express is one-hot since this matches well with the structure of a CLB (little bit of combinatorial logic in front of a D-flip-flop)

• The encoding can be specified in the VHDL code:

type State_Type is (S1, S2, S3, S4);attribute ENUM_ENCODING: string;attribute ENUM_ENCODING of State_Type: type is “11 10 01 00”;

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Safe state machines

• Assume a state machine of three states, encoded with 2 bits

• What would happen when the state machine enters the 4th state, due to some error (noise, power-up, …)? Will it be able to recover?

• Make provisions for this situation in your VHDL code:

NextStateLogic:process(CurrentState) isbegin

case CurrentState iswhen Idle =>

NextState <= S1;when S1 =>

NextState <= S2;when S2 =>

NextState <= Idle;when others =>

NextState <= Idle;end case;

end process NextStateLogic;

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Family specific issues

• Not all families provide per flip-flop both asynchronous set as well as reset.

• Check what your family provides before you write VHDL

process (Clk, Rst, Set) isbeginif Rst = ‘1’ then

Q <= ‘0’;elseif Set = ‘1’ then

Q <= ‘1’;elseif Clk’event and Clk = ‘1’ then

-- actionsend if;

end process;

Can only be implementedefficiently when thefamily has both anasynchronous setas well as reset

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Family specific issues

• Always use LogiBLOX for RAM, because RAM would otherwise be created out of separate flip-flops

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I/O buffer types

• Put all the core logic in one entity• In a higher hierarchical level, instantiate the

I/O buffers as well as the core logic• The hierarchy hence becomes

Top level: test bench instantiating DUT DUT: Instantiation of core logic and I/O buffers Core logic: real design

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I/O buffer types

How to force a 3-state output buffer:

if (Enable = ‘1’) thenOut_pad <= Bus_out;

elseOut_pad <= ‘Z’;

end if;

How to force a bidirectional buffer:

Bus_in <= Bidi_pad;process (Enable, Bus_out) isbegin

if (Enable = ‘1’) thenBidi_pad <= Bus_out;

elseBidi_pad <= ‘Z’;

end if;end process;

Enable

Bus_outOut_pad

Enable

Bus_outBidi_pad

Bus_in

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I/O buffer typesHow to force a bidirectional buffer with registered output:

Bus_in <= Bidi_pad;process (Enable,Q) is begin

if (Enable = ‘1’) thenBidi_pad <= Q;

elseBidi_pad <= ‘Z’;

end if;end process;process (Clk, Bus_out) isbegin

if Clk’event and Clk = ‘1’ thenQ <= D;

end if;end process; Enable

Bus_outBidi_pad

Bus_in

QD

Clk

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I/O buffer typesHow to force a pull-up resistor at an input:

entity Pullup_in isport ( In_pad: in std_logic;

Core_in: out std_logic);end entity Pullup_in;

architecture RTL of Pullup_in is

component PULLUPport (O: out std_logic);

end component PULLUP;

component IBUFport (I: in std_logic; O: out std_logic);

end component IBUF;

signal Dummy: std_logic;

beginDummy <= In_pad;PU: component PULLUP port map (Dummy);Buf: component IBUF port map (Dummy,Core_in);


Core_inIn_pad

Vcc

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Using the Global Set Reset block

entity OneHot isport ( Rst, Clk: in std_logic;

Q: out std_logic_vector (0 to 3));end entity OneHot;

architecture Behav of OneHot is

component STARTUPport (GSR: out std_logic);

end component STARTUP;

beginU1: component STARTUP port map (Rst => GSR);if Rst = ‘1’ then

Q <= “0001”;elseif Clk’event and Clk = ‘1’ then

Q <= Q(1 to 3) & Q(0);endif;


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Clock Networks

• Foundation Express synthesizes automatically clock buffers

• Check whether you do not need more clock buffers than are available in the target family

Điện tử số thầy Phạm Ngọc Nam.

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Transcript of Điện tử số thầy Phạm Ngọc Nam.