Principle Investigators: Prof. Chenming Hu and Prof. Ali Niknejad

Current Team: Sriramkumar V., Yogesh Chauhan, Muhammed Karim

Previous Graduates: Darsen Lu, Chung-Hsun Lin, Mohan Dunga

UC Berkeley

BSIM-CMG A Turnkey Compact Model for Common Multi Gate Devices

Dec. 16, 2011

Nano-Tera Workshop, EPFL, Lausanne

Why next generation transistors?

Gate cannot control the leakage paths far from the gate

Thinning the oxide down was not enough

Dopant fluctuations => Increased variability

Leakage!

Scaling

UC Berkeley- 2

New MOSFET Structures

Leakage!

UC Berkeley- 3

Bulk Planar MOSFET

FinFET UTBSOI

Substrate/ Back Gate

New MOSFET Structures - Demonstration

K. Cheng et al. IEDM 2009 - (IBM / ST)

UC Berkeley - 4

Y. Choi et al. IEEE EDL 2000- (UC Berkeley) X. Huang et al. IEDM 1999 (UC Berkeley)

C.C. Wu et al. IEDM 2010 (TSMC)

FinFET UTBSOI

Advantages for SoC Design

No doping required in the channel

Superior short channel control

Lower DIBL

Steeper on-off

Improved mobility

Lower vertical field needed

Less scattering in the channel

Lower gate-induced drain leakage

Next Gen.: Scale by thinning body

UC Berkeley- 5

FinFET

UTBSOI

Improves lower-Vdd

logic operations

Stand-by power

savings in HVT

devices

Substrate / Back Gate

Another MOSFET architecture

UC Berkeley- 6

DRAM Cell Transistor – 4F2 layout

Versatile Multi-Gate Compact Model: BSIM-MG

Fin

BOX

Gate

1

Gate

2

BOX

p-sub

P+ back-gate

BSIM-IMG

BSIM-CMG

UTBSOI

BG-ETSOI

UC Berkeley - 7

FinFETs on Bulk and

SOI Substrates

Vertical Fin

IMG

Challenges in developing a new model

New Physics

Fully depleted channel

Quantum confinement etc.

When to include them?

Support Multiple Device architectures

Inertia with BSIM4

Large user base

Familiarity with the parameters -> a language in itself

Speed

Convergence – Model behavior in extreme cases

Balance Physics and Flexibility

Balance Speed and Accuracy

UC Berkeley - 8

BSIM-CMG

UC Berkeley - 9

Introduction

Core Model

Surface Potential Equation

Drain Current

Capacitance Model

Real Device Effects

Model Validation & QA

Conclusion

BSIM-CMG Core Models

Four device architectures

Three core models

Intrinsic Double Gate Core (Y. Taur et al, IEEE EDL, 2004)

Perturbation based DG Core for high-doping

Cylindrical Gate Core

Bulk and SOI Substrate

Double Gate Double Gate /

Trigate / FinFET

Quadruple Gate Cylindrical Gate /

Nanowire FET

UC Berkeley - 10

NANA

Surface Potential Core – Double Gate

Surface potential is obtained from the solution of Poisson’s equation and Gauss’s Law.

Poisson’s equation inside the body can be written as (Vch is channel potential)

Body doping complicates the solution of the Poisson’s equation.

Perturbation approach is used to solve this problem.

M. Dunga et al., IEEE TED, Vol. 53, No. 9, 2006

M. Dunga et al., VLSI 2007

Mohan Dunga, PhD Dissertation, UC Berkeley UC Berkeley - 11

Start with a long channel transistor

Assumptions Gradual Channel Approximation

No influence of holes (SOI like structure)

Fully Depleted Body

Gauss Law + Correction for Polysilicon Gate-Depletion

Implicit equation in Qi (channel charge)

Surface Potential Equation

1-D Poisson’s Equation

Surface Potential Core – Cylindrical Gate

S.Venugopalan et. al., SSE, Vol 67, Issue 1, Jan 2012

UC Berkeley - 12

Core Drain Current Model

Drain Current (Pao-Sah, No charge sheet approximation)

0.0 0.2 0.4 0.6 0.8 1.0

-2

-1

0

1

2

Vds=1.0V

Ids E

rro

r R

ela

tive

to

TC

AD

(%

)

Gate Voltage (V)

v104.0 and prior

v105.0

0.0 0.2 0.4 0.6 0.8 1.0

-2

-1

0

1

2

Vds=1.0V

Gm

Err

or

Re

lative

to

TC

AD

(%

)

Gate Voltage (V)

v104.0 and prior

v105.0

0.0 0.5 1.0 1.50.0

0.4

0.8

1.2

1.6

2D TCAD

I-V Model

Vg = 0.9V

Vg = 1.2V

Vg = 1.5V

Tsi = 20nm

Tox = 2nm

Na = 3e18cm-3

Dra

in C

urr

ent (m

A)

Drain Voltage (V)

UC Berkeley - 13

Core Capacitance Model

Model inherently exhibits symmetry Cij = Cji @ Vds= 0 V

Model overlies TCAD results

No tuning parameters used

Accurate short channel behavior – RF Design

Needs additional tuning parameter flexibility

Symbols: TCAD Results; Lines: Model UC Berkeley - 14

BSIM-MG

UC Berkeley - 15

Introduction

Core Model

Surface Potential Equation

Drain Current

Capacitance Model

Real Device Effects

Model Validation & QA

Conclusion

Short Channel (2D) Effects

Along the channel – 2D

Quasi-2D analysis

Similar expression for Double Gate and FinFET/Trigate

Analytical expressions model

Threshold Voltage roll off

Drain induced barrier lowering (DIBL)

Sub-threshold swing degradation

Auth and Plummer, IEEE EDL, 2007

Symbols: TCAD Results; Lines: Model

si

acfbgsc qNVV

dy

d

22

2

Characteristic Length

UC Berkeley - 16

Quantum Mechanical Effects

Predictive model for confinement induced Vth shift due to band splitting present in the model

Can choose to use an effective tox that accounts for charge centroid behavior with bias

Effective Width model that accounts for reduction in width for a triple / quadruple / surround gate structure

Width reduction due to structural confinement of inversion charge. (Dotted lines represent the effective width perimeter)

BOX

UC Berkeley - 17

Asymmetric Device Model

S/D under-lapped FinFETs used as PU and AX transistors in SRAMS show

Improved RSNM at same WSNM

Decreased Time-to-Write (but increased cell read access time)

Asymmetric Halo could be used to create I/O FinFETs for special applications

V.P.Hu et al VLSID 2006

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Asymmetry Model : Parameters Identified

Identified five existing parameters and created their reverse mode equivalents

Doping Gradient in Channel

On-current degradation parameter

Source-side barrier different – DIBL parameter

Output conductance parameter

Top/Bottom Electrode Asymmetry

Quasi-saturation amplification / suppression – Rs/d Parameters

UC Berkeley - 19

S. Venugopalan et al., NVMTS 2011

n1

nwell

ni

STI STI

p+

n1

nwell

ni

STI STI

FinFETs on Bulk require an implant positioned just below the fin to prevent punch-through (and a retrograde profile).

Creates S/D junctions to have two metallurgical junctions of the form p+-n1-nwell or n+-p1-psub.

Simulations indicate that the depletion region beneath the junction could traverse the second junction too.

Source/Drain Junctions in FinFETs

Punch-through

implant

Cross-section at

middle of channel

Cross-section

at S/D junction

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Enhanced BSIM4 style junction charge model with just 2 additional parameters – Cj02 and m2

S/D Junction Cap in FinFETs - Model

Cross-section at S/D junction

1

1

1

/

101,1

11

1

m

V

CQ

m

b

dbs

bjrevjn

2

1

2

/

202

1

1

1

1011

11

1

11

21

m

V

Cm

V

C

m

b

dbs

bj

m

b

bc

bj

1

1

1

1

101

2102

2

1

02

01

1

1

1

m

b

bcj

bj

b

m

j

j

bbc

VmC

mC

C

CV

where,

Vbc<=Vbs/d<=0

Vbs/d<= Vbc

n1

nwell

ni

STI STI

p+

Vbc: the voltage at when the depletion

edge reaches the n1-nwell boundary

UC Berkeley - 21

0.0E+00

5.0E+28

1.0E+29

1.5E+29

2.0E+29

2.5E+29

3.0E+29

0 0.5 1 1.5 2

Retrograde Profile

|Vbs/d|

1/C

jn2

Unified Framework for FinFET Parasitic Resistances and Capacitances

Source Drain

Source Drain

Extension (under

spacer)

Gate

Gate

UC Berkeley - 22

In sub-45nm tech.

Parasitic Resistance – significant portion of RON

Total Parasitic Caps ~ Intrinsic Gate Capacitance

Geometrically scalable parasitic resistance and capacitance model present in BSIM-CMG

FinFET Rds Modeling

UC Berkeley - 23

Darsen Lu, PhD Dissertation, UC Berkeley

Contact Resistance

Spreading Resistance

Extension Resistance

Silicide contact

Heavily-doped S/D

regions (HDD)

Rcon

Gate

Gate

Oxide

S/D Extension

Region Channel Region

Gate

Rsphdd Rext

-60 -30 0 30 60 900

250

500

750

1000

1250

Rch (

-m

)

Lg (nm)

Vgs - Vth = 0.1V . . . 0.45V

in steps of 0.05V

Decreasing

Vgs - Vth

Cfg: fin gate

Ccg=Ccg1+Ccg2+Ccg3: contact gate

Both Cfg and Ccg agree well with 2D numerical simulations

0 10 20 30 40 50 60 70 800.16

0.18

0.20

0.22

0.24

0.26

Lext

=20nm Lext

=25nm

Lext

=30nm Lext

=35nm

Lext

=40nm

Cfg

(fF

)

Wg (nm)

20 25 30 35 40 45 500.06

0.09

0.12

0.15

Ccg (

fF)

Wg (nm)

Tc = 20nm --> 40nm

in steps of 2nm

Increasing Tc

Fin

Epi

-Si

Gate

Cfg

Ccg2

Ccg1

Wg

Lext

Tc

Ccg3

0 25 50 75 1000.0

0.1

0.2

0.3

0.4

0.5

Tc (nm)

Ccg

1 (

fF)

Increasing Lext

Lext = 15nm --> 40nm

in steps of 5nm

Tc = Wg + Tox

Tox = 1nm

Wfin=1um

UC Berkeley - 24

FinFET Cfr Modeling – TCAD Verification

Real Device Effects

Core

SPE

I-V C-V

Short

Channel

Effects

GIDL Current

Channel Length

Modulation and

DIBL

Mobility

Degradation

Direct tunneling

gate current Overlap

capacitances

Temperature

Effects

Velocity

Saturation

S/D Resistance/

Parasitic

Resistance

Fringe

Capacitances

Noise models

Impact Ionization

current

Quantum

Effects

UC Berkeley - 25

BSIM-CMG

UC Berkeley - 26

Introduction

Core Model

Surface Potential Equation

Drain Current

Capacitance Model

Real Device Effects

Model Validation & QA

Conclusion

SOI FinFET Fitting

-0.5 0.0 0.5 1.00.0

300.0µ

600.0µ

900.0µ

1.2m

GIDLVds=50mV

Vds=1V

Vds=50mV

Vds=1VLg = 90nm

Dra

in C

urr

ent (A

)

Gate Voltage (V)

1n

100n

10µ

1m

0.0 0.2 0.4 0.6 0.8 1.00.0

0.4

0.8

1.2

1.6

Lg = 90nm

Vgs = 0.4V

Vgs = 0.6V

Vgs = 0.8V

Vgs = 1.0V

Dra

in C

urr

ent (m

A)

Drain Voltage (V)

0.0 0.2 0.4 0.6 0.8 1.00.0

0.2

0.4

0.6

Vds = 50mV

Vds = 1V

Lg = 90nm

Tra

nsco

nd

ucta

nce

(m

S)

Gate Voltage (V)

0.0

0.6

1.2

1.8

2.4

SOI FinFETs are fabricated at TI

TFIN=22nm, HFIN=60nm, TOX=2nm

Drain Current v.s Vgs

(Lg = 90nm) Drain Current v.s. Vds

(Lg = 90 nm)

Transconductance

(Lg = 90nm)

Symbols: Data

Lines: Model

0.2 0.4 0.6 0.8 1.00

20

40

60

Vds

= 50 mV

Vds

= 1 V

L = 1m

gm E

ffic

ien

cy, g

m/I

d (

V-1)

Gate Voltage (V)0.0 0.2 0.4 0.6 0.8 1.0

1n

1

1m

Lg = 90nm

Vgs = 1.0V --> 0.0V

(in steps of 0.2V)

Ou

tpu

t C

on

du

cta

nce

(S

)

Drain Voltage (V)0.0 0.2 0.4 0.6 0.8 1.0

1p

1n

1

1m

Lg = 1m

Vgs = 1.0V --> 0.2V

(in steps of 0.2V)

Ou

tpu

t C

on

du

cta

nce

(S

)

Drain Voltage (V)

Gm / Ids (Lg = 1 μm) Output Conductance (Lg = 90 nm) Output Conductance (Lg = 1 μm)

µ

UC Berkeley - 27

Bulk FinFET Fitting

Bulk FinFETs are fabricated by TSMC

TFIN=25nm, HFIN=27.5nm, EOT=2.42nm

Drain Current vs. Vgs (Lg = 50nm) Drain Current vs. Vds (Lg = 50 nm) Output Conductance (Lg = 50nm)

0.3 0.6 0.9 1.20

10µ

20µ

30µ

40µ

50µ

Vds = 1.2V

Vds = 50mV

Vds = 1.2V

Vds = 50mV

Lg = 50nm

Dra

in C

urr

ent (A

)

Gate Voltage (V)

1p

1n

1µ

1m

0.0 0.3 0.6 0.9 1.20

10

20

30

40

50

Lg = 50nm

Vgs

= 0.4V

Vgs

= 0.8V

Vgs

= 0.6V

Vgs

= 1.0V

Vgs

= 1.2V

Dra

in C

urr

ent (

A)

Drain Voltage (V)0.0 0.3 0.6 0.9 1.2

10n

1

100 Vgs = 1.2V --> 0.2V

(in steps of 0.2V)

Lg = 50nm

Outp

ut C

on

du

cta

nce (

S)

Drain Voltage (V)

Symbols: Data

Lines: Model

0.0 0.3 0.6 0.9 1.21p

1n

1

1m

Vgs = 1.2V --> 0.4V

(in steps of 0.2V)

Lg = 0.97m

Ou

tpu

t C

on

du

cta

nce

(S

)

Drain Voltage (V)

0.0 0.3 0.6 0.9 1.20

200n

400n

600n

800n

L = 0.97m

Vds = 1.2V

Vds = 50mV

Tra

nsco

nd

ucta

nce

, g

m (

S)

Gate Voltage (V)

0

2µ

4µ

6µ

8µ

10µ

0.0 0.3 0.6 0.9 1.21p

10p

100p

Vds = 1.2V

Lg = 50nm

Su

bstr

ate

Curr

ent (A

)

Gate Voltage (V)

Transconductance (Lg = 0.97μm) Output Conductance (Lg = 0.97 μm) Substrate Current (Lg = 50nm)

µ

µ

UC Berkeley - 28

Vertical GAAFET Overlay

Transconductance

Output Conductance Temperature Dependence

Drain Current vs. Vds

Drain Current vs. Vgs

Lg=120nm, D=80nm, Tox=3nm Symbols: Data

Lines: Model

UC Berkeley - 29

Global Extraction Procedure

θSAT[L] = θSAT0 × (1 + CθSAT х exp ( - Leff / DθSAT ) )

mobility & series

resistance

short channel

effect

velocity

saturation DIBL output conductance

...

e.g.

...

UC Berkeley - 30

Shijing Yao et al., ICMTS 2010

Dra

in C

urr

ent

(mA)

Gate Voltage(V)

0.05

0.10

0.15

0.20

0.25

Dra

in C

urr

ent

(A)

0.1

0.2

0.3

0.4

0.5

0.6

Tra

nsc

onduct

ance

(mA/V

)

Gate Voltage(V)

0.2

0.6

1.0

1.4

0.0

0.4

0.8

1.2

Dra

in C

urr

ent

(mA)

0.5

1.0

1.5

2.0

2.5

0 0

0.0

Tra

nsc

onduct

ance

(mA/V

)

Gate Voltage(V) Gate Voltage(V)

Vds=0.05V Vds=0.05V

Vds=1.0V Vds=1.0V

Dra

in C

urr

ent

(A)

NMOS Leff from 30nm to 10um

Leff Leff

Leff Leff

Symbols: Data

Lines: Model

UC Berkeley - 31

0.1

0.2

0.3

0 Dra

in C

urr

ent

(mA)

Gate Voltage(V)

0.1

0.2

0.3

0.4

0.5

0.6

1E-13

1E-8

1E-3

1E-18

Tra

nsc

onduct

ance

(mA/V

)

Dra

in C

urr

ent

(A)

Gate Voltage(V)

0.0

0.5

1.0

1.5

2.0

5E-16

1E-11

1E-2

1E-20

5E-7

Gate Voltage(V)

Dra

in C

urr

ent

(A)

Dra

in C

urr

ent

(mA)

1.0

2.0

3.0

Tra

nsc

onduct

ance

(mA/V

)

Gate Voltage(V)

0

0.0

PMOS Leff from 35nm to 10um

Leff

Leff

Leff Leff

Symbols: Data

Lines: Model

UC Berkeley - 32

Drain Voltage(V)

Drain Voltage(V)

Dra

in c

urr

en

t(m

A)

Ou

tpu

t R

esis

tan

ce

(Ω)

NMOS Leff = 30nm PMOS Leff = 35nm

Short Channel Output Characteristics

Symbols: Data, Lines: Model

Drain Voltage(V)

NMOS Leff = 250nm PMOS Leff = 250nm

Drain Voltage(V) Drain Voltage(V)

Drain Voltage(V)

Dra

in c

urr

en

t(m

A)

Drain Voltage(V) Drain Voltage(V)

NMOS Leff = 10um

PMOS Leff = 10um

UC Berkeley - 33

Symmetry / Continuity Tests

Model passes both DC and AC Symmetry Tests

Drain Current Capacitances (Cgg and Csd)

C.C.McAndrew, IEEE TED, Vol. 53, No. 9, 2006

UC Berkeley - 34

Speed Tests

Circuit # MOSFETs Model Runtime per iteration per transistor (normalized)

1-Transistor Id-Vds 1 BSIM4 BSIM-CMG

1.00 1.22

17-Stage Ring 34 BSIM4 BSIM-CMG

1.00 1.31

Coupled Rings 2020 BSIM4 BSIM-CMG

1.00 1.24

Averaged over multiple runs on the same machine

Speed of BSIM-CMG v105 and BSIM v4.5 compared

Both model compiled with the in-built Verilog-A compiler of HSpice

Note: Each model uses its own default parameter. Parameters are not extracted for a real technology.

UC Berkeley - 35

BSIM-CMG

UC Berkeley - 36

Introduction

Core Model

Surface Potential Equation

Drain Current

Capacitance Model

Real Device Effects

Model Validation & QA

Conclusion

Roadmap of BSIM-CMG

BSIM-CMG100.0 was released in October 2006

BSIM-CMG105.03 is under balloting stage at the Compact Model Council for standardization

Verilog-A and a well documented manual

Available in major commercial simulators

BSIM-CMG105.04 was released Dec 2011

UC Berkeley - 37

Summary

BSIM-CMG is a Turnkey , Production Ready model

Final Phase of Standardization at the CMC

Physical, Scalable Core Models for multiple device architectures

Supports both SOI and Bulk Substrates

Many Real Device Effects captured

Validated on Hardware Data from different technologies

Available in major EDA tools

UC Berkeley - 38

Acknowledgement

SRC, Industry Supporters, EDA Vendors